From: Haozhong Zhang <haozhong.zhang@intel.com>
To: xen-devel@lists.xen.org, Andrew Cooper <andrew.cooper3@citrix.com>
Cc: Haozhong Zhang <haozhong.zhang@intel.com>,
Kevin Tian <kevin.tian@intel.com>, Wei Liu <wei.liu2@citrix.com>,
Ian Campbell <ian.campbell@citrix.com>,
Stefano Stabellini <stefano.stabellini@eu.citrix.com>,
Jun Nakajima <jun.nakajima@intel.com>,
Ian Jackson <ian.jackson@eu.citrix.com>,
Jan Beulich <jbeulich@suse.com>, Keir Fraser <keir@xen.org>
Subject: [PATCH v2 1/2] x86/hvm: allow guest to use clflushopt and clwb
Date: Wed, 30 Dec 2015 19:48:58 +0800 [thread overview]
Message-ID: <1451476139-22148-2-git-send-email-haozhong.zhang@intel.com> (raw)
In-Reply-To: <1451476139-22148-1-git-send-email-haozhong.zhang@intel.com>
Pass CPU features CLFLUSHOPT and CLWB into HVM domain so that those two
instructions can be used by guest.
The specification of above two instructions can be found in
https://software.intel.com/sites/default/files/managed/0d/53/319433-022.pdf
Signed-off-by: Haozhong Zhang <haozhong.zhang@intel.com>
---
tools/libxc/xc_cpufeature.h | 3 ++-
tools/libxc/xc_cpuid_x86.c | 4 +++-
xen/arch/x86/hvm/hvm.c | 33 +++++++++++++++++++++------------
xen/include/asm-x86/cpufeature.h | 5 +++++
4 files changed, 31 insertions(+), 14 deletions(-)
diff --git a/tools/libxc/xc_cpufeature.h b/tools/libxc/xc_cpufeature.h
index c3ddc80..5288ac6 100644
--- a/tools/libxc/xc_cpufeature.h
+++ b/tools/libxc/xc_cpufeature.h
@@ -140,6 +140,7 @@
#define X86_FEATURE_RDSEED 18 /* RDSEED instruction */
#define X86_FEATURE_ADX 19 /* ADCX, ADOX instructions */
#define X86_FEATURE_SMAP 20 /* Supervisor Mode Access Protection */
-
+#define X86_FEATURE_CLFLUSHOPT 23 /* CLFLUSHOPT instruction */
+#define X86_FEATURE_CLWB 24 /* CLWB instruction */
#endif /* __LIBXC_CPUFEATURE_H */
diff --git a/tools/libxc/xc_cpuid_x86.c b/tools/libxc/xc_cpuid_x86.c
index 8882c01..fecfd6c 100644
--- a/tools/libxc/xc_cpuid_x86.c
+++ b/tools/libxc/xc_cpuid_x86.c
@@ -426,7 +426,9 @@ static void xc_cpuid_hvm_policy(xc_interface *xch,
bitmaskof(X86_FEATURE_RDSEED) |
bitmaskof(X86_FEATURE_ADX) |
bitmaskof(X86_FEATURE_SMAP) |
- bitmaskof(X86_FEATURE_FSGSBASE));
+ bitmaskof(X86_FEATURE_FSGSBASE) |
+ bitmaskof(X86_FEATURE_CLWB) |
+ bitmaskof(X86_FEATURE_CLFLUSHOPT));
} else
regs[1] = 0;
regs[0] = regs[2] = regs[3] = 0;
diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c
index 21470ec..9099188 100644
--- a/xen/arch/x86/hvm/hvm.c
+++ b/xen/arch/x86/hvm/hvm.c
@@ -4583,21 +4583,30 @@ void hvm_cpuid(unsigned int input, unsigned int *eax, unsigned int *ebx,
*edx &= ~cpufeat_mask(X86_FEATURE_PSE36);
break;
case 0x7:
- if ( (count == 0) && !cpu_has_smep )
- *ebx &= ~cpufeat_mask(X86_FEATURE_SMEP);
+ if ( count == 0 )
+ {
+ if ( !cpu_has_smep )
+ *ebx &= ~cpufeat_mask(X86_FEATURE_SMEP);
+
+ if ( !cpu_has_smap )
+ *ebx &= ~cpufeat_mask(X86_FEATURE_SMAP);
+
+ /* Don't expose MPX to hvm when VMX support is not available */
+ if ( !(vmx_vmexit_control & VM_EXIT_CLEAR_BNDCFGS) ||
+ !(vmx_vmentry_control & VM_ENTRY_LOAD_BNDCFGS) )
+ *ebx &= ~cpufeat_mask(X86_FEATURE_MPX);
- if ( (count == 0) && !cpu_has_smap )
- *ebx &= ~cpufeat_mask(X86_FEATURE_SMAP);
+ /* Don't expose INVPCID to non-hap hvm. */
+ if ( !hap_enabled(d) )
+ *ebx &= ~cpufeat_mask(X86_FEATURE_INVPCID);
- /* Don't expose MPX to hvm when VMX support is not available */
- if ( (count == 0) &&
- (!(vmx_vmexit_control & VM_EXIT_CLEAR_BNDCFGS) ||
- !(vmx_vmentry_control & VM_ENTRY_LOAD_BNDCFGS)) )
- *ebx &= ~cpufeat_mask(X86_FEATURE_MPX);
+ if ( !cpu_has_clflushopt )
+ *ebx &= ~cpufeat_mask(X86_FEATURE_CLFLUSHOPT);
+
+ if ( !cpu_has_clwb )
+ *ebx &= ~cpufeat_mask(X86_FEATURE_CLWB);
+ }
- /* Don't expose INVPCID to non-hap hvm. */
- if ( (count == 0) && !hap_enabled(d) )
- *ebx &= ~cpufeat_mask(X86_FEATURE_INVPCID);
break;
case 0xb:
/* Fix the x2APIC identifier. */
diff --git a/xen/include/asm-x86/cpufeature.h b/xen/include/asm-x86/cpufeature.h
index ef96514..5818228 100644
--- a/xen/include/asm-x86/cpufeature.h
+++ b/xen/include/asm-x86/cpufeature.h
@@ -162,6 +162,8 @@
#define X86_FEATURE_RDSEED (7*32+18) /* RDSEED instruction */
#define X86_FEATURE_ADX (7*32+19) /* ADCX, ADOX instructions */
#define X86_FEATURE_SMAP (7*32+20) /* Supervisor Mode Access Prevention */
+#define X86_FEATURE_CLFLUSHOPT (7*32+23) /* CLFLUSHOPT instruction */
+#define X86_FEATURE_CLWB (7*32+24) /* CLWB instruction */
/* Intel-defined CPU features, CPUID level 0x00000007:0 (ecx), word 8 */
#define X86_FEATURE_PKU (8*32+ 3) /* Protection Keys for Userspace */
@@ -234,6 +236,9 @@
#define cpu_has_xgetbv1 boot_cpu_has(X86_FEATURE_XGETBV1)
#define cpu_has_xsaves boot_cpu_has(X86_FEATURE_XSAVES)
+#define cpu_has_clflushopt boot_cpu_has(X86_FEATURE_CLFLUSHOPT)
+#define cpu_has_clwb boot_cpu_has(X86_FEATURE_CLWB)
+
enum _cache_type {
CACHE_TYPE_NULL = 0,
CACHE_TYPE_DATA = 1,
--
2.4.8
next prev parent reply other threads:[~2015-12-30 11:48 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-12-30 11:48 [PATCH v2 0/2] add support for vNVDIMM - Part 1: enable instructions Haozhong Zhang
2015-12-30 11:48 ` Haozhong Zhang [this message]
2015-12-30 11:53 ` [PATCH v2 1/2] x86/hvm: allow guest to use clflushopt and clwb Andrew Cooper
2016-01-05 7:02 ` Tian, Kevin
2016-01-07 13:49 ` Jan Beulich
2016-01-07 14:01 ` Andrew Cooper
2016-01-07 14:34 ` Jan Beulich
2016-01-08 8:27 ` Haozhong Zhang
2016-01-08 8:39 ` Jan Beulich
2015-12-30 11:48 ` [PATCH v2 2/2] x86/hvm: add support for pcommit instruction Haozhong Zhang
2015-12-30 11:57 ` Andrew Cooper
2016-01-05 7:08 ` Tian, Kevin
2016-01-05 7:15 ` Zhang, Haozhong
2016-01-05 7:19 ` Tian, Kevin
2016-01-05 7:32 ` Zhang, Haozhong
2016-01-05 7:45 ` Tian, Kevin
2016-01-07 13:53 ` Jan Beulich
2016-01-08 1:15 ` Haozhong Zhang
2016-01-08 7:54 ` Jan Beulich
2016-01-08 7:58 ` Haozhong Zhang
2016-01-04 11:10 ` [PATCH v2 0/2] add support for vNVDIMM - Part 1: enable instructions Wei Liu
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