From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm0-f49.google.com ([74.125.82.49]:34481 "EHLO mail-wm0-f49.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752032AbcAGLo1 (ORCPT ); Thu, 7 Jan 2016 06:44:27 -0500 Received: by mail-wm0-f49.google.com with SMTP id u188so94886233wmu.1 for ; Thu, 07 Jan 2016 03:44:26 -0800 (PST) From: Daniel Vetter To: DRI Development Cc: Intel Graphics Development , Daniel Vetter , =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= , Patrik Jakobsson , Imre Deak , Jani Nikula , Meelis Roos , Chris Wilson , stable@vger.kernel.org, Daniel Vetter Subject: [PATCH] drm/i915: Init power domains early in driver load Date: Thu, 7 Jan 2016 12:44:21 +0100 Message-Id: <1452167061-27252-1-git-send-email-daniel.vetter@ffwll.ch> In-Reply-To: <1452157856-27360-1-git-send-email-daniel.vetter@ffwll.ch> References: <1452157856-27360-1-git-send-email-daniel.vetter@ffwll.ch> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: stable-owner@vger.kernel.org List-ID: Since commit ac9b8236551d1177fd07b56aef9b565d1864420d Author: Ville Syrjälä Date: Fri Nov 27 18:55:26 2015 +0200 drm/i915: Introduce a gmbus power domain gmbus also needs the power domain infrastructure right from the start, since as soon as we register the i2c controllers someone can use them. v2: Adjust cleanup paths too (Chris). Cc: Ville Syrjälä Cc: Patrik Jakobsson Cc: Imre Deak Cc: Jani Nikula Cc: Meelis Roos Cc: Chris Wilson Fixes: ac9b8236551d ("drm/i915: Introduce a gmbus power domain") Cc: stable@vger.kernel.org References: http://www.spinics.net/lists/intel-gfx/msg83075.html Tested-by: Meelis Roos Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_dma.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index 988a3806512a..490d8b0d931e 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c @@ -398,7 +398,6 @@ static int i915_load_modeset_init(struct drm_device *dev) if (ret) goto cleanup_vga_switcheroo; - intel_power_domains_init_hw(dev_priv, false); intel_csr_ucode_init(dev_priv); @@ -1025,6 +1024,8 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) intel_irq_init(dev_priv); intel_uncore_sanitize(dev); + intel_power_domains_init(dev_priv); + intel_power_domains_init_hw(dev_priv); /* Try to make sure MCHBAR is enabled before poking at it */ intel_setup_mchbar(dev); @@ -1057,12 +1058,10 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) goto out_gem_unload; } - intel_power_domains_init(dev_priv); - ret = i915_load_modeset_init(dev); if (ret < 0) { DRM_ERROR("failed to init modeset\n"); - goto out_power_well; + goto out_vblank; } /* @@ -1091,8 +1090,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) return 0; -out_power_well: - intel_power_domains_fini(dev_priv); +out_vblank: drm_vblank_cleanup(dev); out_gem_unload: WARN_ON(unregister_oom_notifier(&dev_priv->mm.oom_notifier)); @@ -1103,6 +1101,7 @@ out_gem_unload: intel_teardown_gmbus(dev); intel_teardown_mchbar(dev); + intel_power_domains_fini(dev_priv); pm_qos_remove_request(&dev_priv->pm_qos); destroy_workqueue(dev_priv->gpu_error.hangcheck_wq); out_freedpwq: -- 2.6.4