From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1763678AbcALRi2 (ORCPT ); Tue, 12 Jan 2016 12:38:28 -0500 Received: from mail-sn1nam02on0053.outbound.protection.outlook.com ([104.47.36.53]:20393 "EHLO NAM02-SN1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752203AbcALRgm (ORCPT ); Tue, 12 Jan 2016 12:36:42 -0500 Authentication-Results: spf=pass (sender IP is 149.199.60.83) smtp.mailfrom=xilinx.com; york.ac.uk; dkim=none (message not signed) header.d=none;york.ac.uk; dmarc=bestguesspass action=none header.from=xilinx.com; From: Bharat Kumar Gogada To: , , , , , , , , , , , , , , CC: , , , , "Bharat Kumar Gogada" , Ravi Kiran Gummaluri Subject: [PATCH V2 3/5] PCI: xilinx: Modifying AXI PCIe Host Bridge driver to work on both Zynq and Microblaze Date: Tue, 12 Jan 2016 23:06:11 +0530 Message-ID: <1452620173-4905-4-git-send-email-bharatku@xilinx.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1452620173-4905-1-git-send-email-bharatku@xilinx.com> References: <1452620173-4905-1-git-send-email-bharatku@xilinx.com> X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.0.0.1202-22060.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:149.199.60.83;CTRY:US;IPV:NLI;EFV:NLI;SFV:NSPM;SFS:(10009020)(6009001)(2980300002)(438002)(199003)(189002)(5008740100001)(1096002)(50466002)(5001960100002)(107886002)(2906002)(103686003)(19580405001)(4001430100002)(189998001)(86362001)(87936001)(36756003)(63266004)(5001770100001)(48376002)(4326007)(19580395003)(106466001)(42186005)(81156007)(76176999)(2950100001)(36386004)(6806005)(11100500001)(586003)(47776003)(52956003)(90966002)(50226001)(2201001)(46386002)(33646002)(1220700001)(50986999)(229853001)(45336002)(92566002)(5003940100001)(107986001)(921003)(2101003)(1121003)(83996005);DIR:OUT;SFP:1101;SCL:1;SRVR:CY1NAM02HT198;H:xsj-pvapsmtpgw01;FPR:;SPF:Pass;PTR:unknown-60-83.xilinx.com;A:1;MX:1;LANG:en; MIME-Version: 1.0 Content-Type: text/plain X-MS-Office365-Filtering-Correlation-Id: e84377ac-2055-4040-e861-08d31b76eccd X-Exchange-Antispam-Report-Test: UriScan:;BCL:0;PCL:0;RULEID:(8251501002);SRVR:CY1NAM02HT198;UriScan:(192813158149592); X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-CFA-Test: BCL:0;PCL:0;RULEID:(601004)(2401047)(8121501046)(520078)(13018025)(5005006)(13015025)(13017025)(10201501046)(3002001);SRVR:CY1NAM02HT198;BCL:0;PCL:0;RULEID:;SRVR:CY1NAM02HT198; X-Forefront-PRVS: 081904387B X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Jan 2016 17:36:37.2692 (UTC) X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.60.83];Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY1NAM02HT198 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Modifying Xilinx AXI PCIe Host Bridge Soft IP driver to work on both Zynq and Microblaze Architectures. With these modifications drivers/pci/host/pcie-xilinx.c, will work on both Zynq and Microblaze Architectures. Signed-off-by: Bharat Kumar Gogada Signed-off-by: Ravi Kiran Gummaluri --- Changes: Changed Total number of MSI IRQ count logic according to both architectures. Updated MSI assigning functions accordingly to new count. Modified irq_domain_add_linear with new MSI IRQ count. Added #ifdef to pci_fixup_irqs which is ARM specific API. --- drivers/pci/host/pcie-xilinx.c | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c index 3e3757f..1981948 100644 --- a/drivers/pci/host/pcie-xilinx.c +++ b/drivers/pci/host/pcie-xilinx.c @@ -92,7 +92,12 @@ #define ECAM_DEV_NUM_SHIFT 12 /* Number of MSI IRQs */ -#define XILINX_NUM_MSI_IRQS 128 +#define XILINX_NUM_MSI_IRQS 128 +#ifdef CONFIG_ARM +#define TOT_NR_IRQS XILINX_NUM_MSI_IRQS +#else +#define TOT_NR_IRQS (NR_IRQS + XILINX_NUM_MSI_IRQS) +#endif /** @@ -238,15 +243,20 @@ static void xilinx_pcie_destroy_msi(unsigned int irq) */ static int xilinx_pcie_assign_msi(struct xilinx_pcie_port *port) { + int irq; int pos; pos = find_first_zero_bit(msi_irq_in_use, XILINX_NUM_MSI_IRQS); - if (pos < XILINX_NUM_MSI_IRQS) + irq = pos; +#ifdef CONFIG_MICROBLAZE + irq = XILINX_NUM_MSI_IRQS + pos; +#endif + if (irq < TOT_NR_IRQS) set_bit(pos, msi_irq_in_use); else return -ENOSPC; - return pos; + return irq; } /** @@ -520,7 +530,7 @@ static void xilinx_pcie_free_irq_domain(struct xilinx_pcie_port *port) free_pages(port->msi_pages, 0); - num_irqs = XILINX_NUM_MSI_IRQS; + num_irqs = TOT_NR_IRQS; } else { /* INTx */ num_irqs = 4; @@ -565,7 +575,7 @@ static int xilinx_pcie_init_irq_domain(struct xilinx_pcie_port *port) /* Setup MSI */ if (IS_ENABLED(CONFIG_PCI_MSI)) { port->irq_domain = irq_domain_add_linear(node, - XILINX_NUM_MSI_IRQS, + TOT_NR_IRQS, &msi_domain_ops, &xilinx_pcie_msi_chip); if (!port->irq_domain) { @@ -705,7 +715,9 @@ static int xilinx_pcie_probe(struct platform_device *pdev) #endif pci_scan_child_bus(bus); pci_assign_unassigned_bus_resources(bus); +#ifdef CONFIG_ARM pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci); +#endif pci_bus_add_devices(bus); platform_set_drvdata(pdev, port); -- 2.1.1 From mboxrd@z Thu Jan 1 00:00:00 1970 From: Bharat Kumar Gogada Subject: [PATCH V2 3/5] PCI: xilinx: Modifying AXI PCIe Host Bridge driver to work on both Zynq and Microblaze Date: Tue, 12 Jan 2016 23:06:11 +0530 Message-ID: <1452620173-4905-4-git-send-email-bharatku@xilinx.com> References: <1452620173-4905-1-git-send-email-bharatku@xilinx.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1452620173-4905-1-git-send-email-bharatku@xilinx.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: bhelgaas@google.com, michals@xilinx.com, lorenzo.pieralisi@arm.com, paul.burton@imgtec.com, yinghai@kernel.org, wangyijing@huawei.com, robh@kernel.org, russell.joyce@york.ac.uk, sorenb@xilinx.com, jiang.liu@linux.intel.com, arnd@arndb.de, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org Cc: devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Bharat Kumar Gogada , Ravi Kiran Gummaluri , linux-arm-kernel@lists.infradead.org List-Id: devicetree@vger.kernel.org Modifying Xilinx AXI PCIe Host Bridge Soft IP driver to work on both Zynq and Microblaze Architectures. With these modifications drivers/pci/host/pcie-xilinx.c, will work on both Zynq and Microblaze Architectures. Signed-off-by: Bharat Kumar Gogada Signed-off-by: Ravi Kiran Gummaluri --- Changes: Changed Total number of MSI IRQ count logic according to both architectures. Updated MSI assigning functions accordingly to new count. Modified irq_domain_add_linear with new MSI IRQ count. Added #ifdef to pci_fixup_irqs which is ARM specific API. --- drivers/pci/host/pcie-xilinx.c | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c index 3e3757f..1981948 100644 --- a/drivers/pci/host/pcie-xilinx.c +++ b/drivers/pci/host/pcie-xilinx.c @@ -92,7 +92,12 @@ #define ECAM_DEV_NUM_SHIFT 12 /* Number of MSI IRQs */ -#define XILINX_NUM_MSI_IRQS 128 +#define XILINX_NUM_MSI_IRQS 128 +#ifdef CONFIG_ARM +#define TOT_NR_IRQS XILINX_NUM_MSI_IRQS +#else +#define TOT_NR_IRQS (NR_IRQS + XILINX_NUM_MSI_IRQS) +#endif /** @@ -238,15 +243,20 @@ static void xilinx_pcie_destroy_msi(unsigned int irq) */ static int xilinx_pcie_assign_msi(struct xilinx_pcie_port *port) { + int irq; int pos; pos = find_first_zero_bit(msi_irq_in_use, XILINX_NUM_MSI_IRQS); - if (pos < XILINX_NUM_MSI_IRQS) + irq = pos; +#ifdef CONFIG_MICROBLAZE + irq = XILINX_NUM_MSI_IRQS + pos; +#endif + if (irq < TOT_NR_IRQS) set_bit(pos, msi_irq_in_use); else return -ENOSPC; - return pos; + return irq; } /** @@ -520,7 +530,7 @@ static void xilinx_pcie_free_irq_domain(struct xilinx_pcie_port *port) free_pages(port->msi_pages, 0); - num_irqs = XILINX_NUM_MSI_IRQS; + num_irqs = TOT_NR_IRQS; } else { /* INTx */ num_irqs = 4; @@ -565,7 +575,7 @@ static int xilinx_pcie_init_irq_domain(struct xilinx_pcie_port *port) /* Setup MSI */ if (IS_ENABLED(CONFIG_PCI_MSI)) { port->irq_domain = irq_domain_add_linear(node, - XILINX_NUM_MSI_IRQS, + TOT_NR_IRQS, &msi_domain_ops, &xilinx_pcie_msi_chip); if (!port->irq_domain) { @@ -705,7 +715,9 @@ static int xilinx_pcie_probe(struct platform_device *pdev) #endif pci_scan_child_bus(bus); pci_assign_unassigned_bus_resources(bus); +#ifdef CONFIG_ARM pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci); +#endif pci_bus_add_devices(bus); platform_set_drvdata(pdev, port); -- 2.1.1 From mboxrd@z Thu Jan 1 00:00:00 1970 From: bharat.kumar.gogada@xilinx.com (Bharat Kumar Gogada) Date: Tue, 12 Jan 2016 23:06:11 +0530 Subject: [PATCH V2 3/5] PCI: xilinx: Modifying AXI PCIe Host Bridge driver to work on both Zynq and Microblaze In-Reply-To: <1452620173-4905-1-git-send-email-bharatku@xilinx.com> References: <1452620173-4905-1-git-send-email-bharatku@xilinx.com> Message-ID: <1452620173-4905-4-git-send-email-bharatku@xilinx.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Modifying Xilinx AXI PCIe Host Bridge Soft IP driver to work on both Zynq and Microblaze Architectures. With these modifications drivers/pci/host/pcie-xilinx.c, will work on both Zynq and Microblaze Architectures. Signed-off-by: Bharat Kumar Gogada Signed-off-by: Ravi Kiran Gummaluri --- Changes: Changed Total number of MSI IRQ count logic according to both architectures. Updated MSI assigning functions accordingly to new count. Modified irq_domain_add_linear with new MSI IRQ count. Added #ifdef to pci_fixup_irqs which is ARM specific API. --- drivers/pci/host/pcie-xilinx.c | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c index 3e3757f..1981948 100644 --- a/drivers/pci/host/pcie-xilinx.c +++ b/drivers/pci/host/pcie-xilinx.c @@ -92,7 +92,12 @@ #define ECAM_DEV_NUM_SHIFT 12 /* Number of MSI IRQs */ -#define XILINX_NUM_MSI_IRQS 128 +#define XILINX_NUM_MSI_IRQS 128 +#ifdef CONFIG_ARM +#define TOT_NR_IRQS XILINX_NUM_MSI_IRQS +#else +#define TOT_NR_IRQS (NR_IRQS + XILINX_NUM_MSI_IRQS) +#endif /** @@ -238,15 +243,20 @@ static void xilinx_pcie_destroy_msi(unsigned int irq) */ static int xilinx_pcie_assign_msi(struct xilinx_pcie_port *port) { + int irq; int pos; pos = find_first_zero_bit(msi_irq_in_use, XILINX_NUM_MSI_IRQS); - if (pos < XILINX_NUM_MSI_IRQS) + irq = pos; +#ifdef CONFIG_MICROBLAZE + irq = XILINX_NUM_MSI_IRQS + pos; +#endif + if (irq < TOT_NR_IRQS) set_bit(pos, msi_irq_in_use); else return -ENOSPC; - return pos; + return irq; } /** @@ -520,7 +530,7 @@ static void xilinx_pcie_free_irq_domain(struct xilinx_pcie_port *port) free_pages(port->msi_pages, 0); - num_irqs = XILINX_NUM_MSI_IRQS; + num_irqs = TOT_NR_IRQS; } else { /* INTx */ num_irqs = 4; @@ -565,7 +575,7 @@ static int xilinx_pcie_init_irq_domain(struct xilinx_pcie_port *port) /* Setup MSI */ if (IS_ENABLED(CONFIG_PCI_MSI)) { port->irq_domain = irq_domain_add_linear(node, - XILINX_NUM_MSI_IRQS, + TOT_NR_IRQS, &msi_domain_ops, &xilinx_pcie_msi_chip); if (!port->irq_domain) { @@ -705,7 +715,9 @@ static int xilinx_pcie_probe(struct platform_device *pdev) #endif pci_scan_child_bus(bus); pci_assign_unassigned_bus_resources(bus); +#ifdef CONFIG_ARM pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci); +#endif pci_bus_add_devices(bus); platform_set_drvdata(pdev, port); -- 2.1.1