From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1763670AbcALRg7 (ORCPT ); Tue, 12 Jan 2016 12:36:59 -0500 Received: from mail-bl2nam02on0085.outbound.protection.outlook.com ([104.47.38.85]:1185 "EHLO NAM02-BL2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752067AbcALRgv (ORCPT ); Tue, 12 Jan 2016 12:36:51 -0500 Authentication-Results: spf=pass (sender IP is 149.199.60.83) smtp.mailfrom=xilinx.com; york.ac.uk; dkim=none (message not signed) header.d=none;york.ac.uk; dmarc=bestguesspass action=none header.from=xilinx.com; From: Bharat Kumar Gogada To: , , , , , , , , , , , , , , CC: , , , , "Bharat Kumar Gogada" , Ravi Kiran Gummaluri Subject: [PATCH V2 4/5] PCI: xilinx: Updating Zynq PCI binding documentation with Microblaze node. Date: Tue, 12 Jan 2016 23:06:12 +0530 Message-ID: <1452620173-4905-5-git-send-email-bharatku@xilinx.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1452620173-4905-1-git-send-email-bharatku@xilinx.com> References: <1452620173-4905-1-git-send-email-bharatku@xilinx.com> X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.0.0.1202-22060.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:149.199.60.83;CTRY:US;IPV:NLI;EFV:NLI;SFV:NSPM;SFS:(10009020)(6009001)(2980300002)(438002)(189002)(199003)(4001430100002)(5008740100001)(1096002)(42186005)(50226001)(2950100001)(5001960100002)(36756003)(50466002)(4326007)(103686003)(106466001)(189998001)(6806005)(2906002)(586003)(45336002)(63266004)(1220700001)(5001770100001)(19580405001)(52956003)(2201001)(92566002)(76176999)(107886002)(46386002)(36386004)(86362001)(48376002)(50986999)(87936001)(19580395003)(229853001)(33646002)(81156007)(11100500001)(47776003)(90966002)(5003940100001)(107986001)(921003)(1121003)(2101003)(83996005);DIR:OUT;SFP:1101;SCL:1;SRVR:BL2NAM02HT118;H:xsj-pvapsmtpgw01;FPR:;SPF:Pass;PTR:unknown-60-83.xilinx.com;MX:1;A:1;LANG:en; MIME-Version: 1.0 Content-Type: text/plain X-MS-Office365-Filtering-Correlation-Id: 959722ed-412f-445e-aec2-08d31b76f279 X-Exchange-Antispam-Report-Test: UriScan:;BCL:0;PCL:0;RULEID:(8251501002);SRVR:BL2NAM02HT118;UriScan:(192813158149592); X-Microsoft-Antispam-PRVS: <05287626c0324d7ea0ff5caac9992870@BL2NAM02HT118.eop-nam02.prod.protection.outlook.com> X-Exchange-Antispam-Report-CFA-Test: BCL:0;PCL:0;RULEID:(601004)(2401047)(520078)(13018025)(13015025)(5005006)(8121501046)(13017025)(3002001)(10201501046);SRVR:BL2NAM02HT118;BCL:0;PCL:0;RULEID:;SRVR:BL2NAM02HT118; X-Forefront-PRVS: 081904387B X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Jan 2016 17:36:47.5023 (UTC) X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.60.83];Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL2NAM02HT118 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Updated Zynq PCI binding documentation with Microblaze node. Signed-off-by: Bharat Kumar Gogada Signed-off-by: Ravi Kiran Gummaluri --- Changes: Adding Microblaze device tree node Documnetation. --- .../devicetree/bindings/pci/xilinx-pcie.txt | 36 ++++++++++++++++++++-- 1 file changed, 33 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/xilinx-pcie.txt b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt index 02f979a..d207bf4 100644 --- a/Documentation/devicetree/bindings/pci/xilinx-pcie.txt +++ b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt @@ -17,7 +17,10 @@ Required properties: Please refer to the standard PCI bus binding document for a more detailed explanation -Optional properties: +Optional properties for Zynq: +- bus-range: PCI bus numbers covered + +Required property for Microblaze: - bus-range: PCI bus numbers covered Interrupt controller child node @@ -38,13 +41,13 @@ the four INTx interrupts in ISR and route them to this domain. Example: ++++++++ - +Zynq: pci_express: axi-pcie@50000000 { #address-cells = <3>; #size-cells = <2>; #interrupt-cells = <1>; compatible = "xlnx,axi-pcie-host-1.00.a"; - reg = < 0x50000000 0x10000000 >; + reg = < 0x50000000 0x1000000 >; device_type = "pci"; interrupts = < 0 52 4 >; interrupt-map-mask = <0 0 0 7>; @@ -60,3 +63,30 @@ Example: #interrupt-cells = <1>; }; }; + + +Microblaze: + pci_express: axi-pcie@10000000 { + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + compatible = "xlnx,axi-pcie-host-1.00.a"; + reg = <0x10000000 0x4000000>; + device_type = "pci"; + interrupt-parent = <µbalze_0_intc>; + interrupts = <1 2>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc 1>, + <0 0 0 2 &pcie_intc 2>, + <0 0 0 3 &pcie_intc 3>, + <0 0 0 4 &pcie_intc 4>; + ranges = <0x02000000 0x00000000 0x80000000 0x80000000 0x00000000 0x10000000>; + bus-range = <0x00 0xff>; + + pcie_intc: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + + }; -- 2.1.1 From mboxrd@z Thu Jan 1 00:00:00 1970 From: Bharat Kumar Gogada Subject: [PATCH V2 4/5] PCI: xilinx: Updating Zynq PCI binding documentation with Microblaze node. Date: Tue, 12 Jan 2016 23:06:12 +0530 Message-ID: <1452620173-4905-5-git-send-email-bharatku@xilinx.com> References: <1452620173-4905-1-git-send-email-bharatku@xilinx.com> Mime-Version: 1.0 Content-Type: text/plain Return-path: In-Reply-To: <1452620173-4905-1-git-send-email-bharatku@xilinx.com> Sender: linux-kernel-owner@vger.kernel.org To: bhelgaas@google.com, michals@xilinx.com, lorenzo.pieralisi@arm.com, paul.burton@imgtec.com, yinghai@kernel.org, wangyijing@huawei.com, robh@kernel.org, russell.joyce@york.ac.uk, sorenb@xilinx.com, jiang.liu@linux.intel.com, arnd@arndb.de, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, Bharat Kumar Gogada , Ravi Kiran Gummaluri List-Id: devicetree@vger.kernel.org Updated Zynq PCI binding documentation with Microblaze node. Signed-off-by: Bharat Kumar Gogada Signed-off-by: Ravi Kiran Gummaluri --- Changes: Adding Microblaze device tree node Documnetation. --- .../devicetree/bindings/pci/xilinx-pcie.txt | 36 ++++++++++++++++++++-- 1 file changed, 33 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/xilinx-pcie.txt b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt index 02f979a..d207bf4 100644 --- a/Documentation/devicetree/bindings/pci/xilinx-pcie.txt +++ b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt @@ -17,7 +17,10 @@ Required properties: Please refer to the standard PCI bus binding document for a more detailed explanation -Optional properties: +Optional properties for Zynq: +- bus-range: PCI bus numbers covered + +Required property for Microblaze: - bus-range: PCI bus numbers covered Interrupt controller child node @@ -38,13 +41,13 @@ the four INTx interrupts in ISR and route them to this domain. Example: ++++++++ - +Zynq: pci_express: axi-pcie@50000000 { #address-cells = <3>; #size-cells = <2>; #interrupt-cells = <1>; compatible = "xlnx,axi-pcie-host-1.00.a"; - reg = < 0x50000000 0x10000000 >; + reg = < 0x50000000 0x1000000 >; device_type = "pci"; interrupts = < 0 52 4 >; interrupt-map-mask = <0 0 0 7>; @@ -60,3 +63,30 @@ Example: #interrupt-cells = <1>; }; }; + + +Microblaze: + pci_express: axi-pcie@10000000 { + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + compatible = "xlnx,axi-pcie-host-1.00.a"; + reg = <0x10000000 0x4000000>; + device_type = "pci"; + interrupt-parent = <µbalze_0_intc>; + interrupts = <1 2>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc 1>, + <0 0 0 2 &pcie_intc 2>, + <0 0 0 3 &pcie_intc 3>, + <0 0 0 4 &pcie_intc 4>; + ranges = <0x02000000 0x00000000 0x80000000 0x80000000 0x00000000 0x10000000>; + bus-range = <0x00 0xff>; + + pcie_intc: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + + }; -- 2.1.1 From mboxrd@z Thu Jan 1 00:00:00 1970 From: bharat.kumar.gogada@xilinx.com (Bharat Kumar Gogada) Date: Tue, 12 Jan 2016 23:06:12 +0530 Subject: [PATCH V2 4/5] PCI: xilinx: Updating Zynq PCI binding documentation with Microblaze node. In-Reply-To: <1452620173-4905-1-git-send-email-bharatku@xilinx.com> References: <1452620173-4905-1-git-send-email-bharatku@xilinx.com> Message-ID: <1452620173-4905-5-git-send-email-bharatku@xilinx.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Updated Zynq PCI binding documentation with Microblaze node. Signed-off-by: Bharat Kumar Gogada Signed-off-by: Ravi Kiran Gummaluri --- Changes: Adding Microblaze device tree node Documnetation. --- .../devicetree/bindings/pci/xilinx-pcie.txt | 36 ++++++++++++++++++++-- 1 file changed, 33 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/xilinx-pcie.txt b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt index 02f979a..d207bf4 100644 --- a/Documentation/devicetree/bindings/pci/xilinx-pcie.txt +++ b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt @@ -17,7 +17,10 @@ Required properties: Please refer to the standard PCI bus binding document for a more detailed explanation -Optional properties: +Optional properties for Zynq: +- bus-range: PCI bus numbers covered + +Required property for Microblaze: - bus-range: PCI bus numbers covered Interrupt controller child node @@ -38,13 +41,13 @@ the four INTx interrupts in ISR and route them to this domain. Example: ++++++++ - +Zynq: pci_express: axi-pcie at 50000000 { #address-cells = <3>; #size-cells = <2>; #interrupt-cells = <1>; compatible = "xlnx,axi-pcie-host-1.00.a"; - reg = < 0x50000000 0x10000000 >; + reg = < 0x50000000 0x1000000 >; device_type = "pci"; interrupts = < 0 52 4 >; interrupt-map-mask = <0 0 0 7>; @@ -60,3 +63,30 @@ Example: #interrupt-cells = <1>; }; }; + + +Microblaze: + pci_express: axi-pcie at 10000000 { + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + compatible = "xlnx,axi-pcie-host-1.00.a"; + reg = <0x10000000 0x4000000>; + device_type = "pci"; + interrupt-parent = <µbalze_0_intc>; + interrupts = <1 2>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc 1>, + <0 0 0 2 &pcie_intc 2>, + <0 0 0 3 &pcie_intc 3>, + <0 0 0 4 &pcie_intc 4>; + ranges = <0x02000000 0x00000000 0x80000000 0x80000000 0x00000000 0x10000000>; + bus-range = <0x00 0xff>; + + pcie_intc: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + + }; -- 2.1.1