From mboxrd@z Thu Jan 1 00:00:00 1970 From: Romain Izard Subject: [PATCH v1 5/5] ARM: at91/dt: sama5d2: add nand0 and nfc0 nodes Date: Wed, 13 Jan 2016 17:34:17 +0100 Message-ID: <1452702857-2240-6-git-send-email-romain.izard.pro@gmail.com> References: <1452702857-2240-1-git-send-email-romain.izard.pro@gmail.com> Return-path: In-Reply-To: <1452702857-2240-1-git-send-email-romain.izard.pro-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org Cc: Yang Wenyou , Josh Wu , Nicolas Ferre , Romain Izard List-Id: devicetree@vger.kernel.org Both nodes are required to access NAND Flash memory. Additional settings will be necessary at the board level to use it. Signed-off-by: Romain Izard --- arch/arm/boot/dts/sama5d2.dtsi | 38 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi index aee571448342..80420177ec1a 100644 --- a/arch/arm/boot/dts/sama5d2.dtsi +++ b/arch/arm/boot/dts/sama5d2.dtsi @@ -265,6 +265,44 @@ cache-level = <2>; }; + nand0: nand@80000000 { + compatible = "atmel,sama5d2-nand"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + reg = < /* EBI CS3 */ + 0x80000000 0x08000000 + /* SMC PMECC regs */ + 0xf8014070 0x00000490 + /* SMC PMECC Error Location regs */ + 0xf8014500 0x00000200 + /* ROM Galois tables */ + 0x00040000 0x00018000 + >; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH 6>; + atmel,nand-addr-offset = <21>; + atmel,nand-cmd-offset = <22>; + atmel,nand-has-dma; + atmel,has-pmecc; + atmel,pmecc-lookup-table-offset = <0x0 0x8000>; + status = "disabled"; + + nfc@90000000 { + compatible = "atmel,sama5d4-nfc"; + #address-cells = <1>; + #size-cells = <1>; + reg = < /* NFC Command Registers */ + 0xC0000000 0x08000000 + /* NFC HSMC regs */ + 0xf8014000 0x00000070 + /* NFC SRAM banks */ + 0x00100000 0x00100000 + >; + clocks = <&hsmc_clk>; + atmel,write-by-sram; + }; + }; + sdmmc0: sdio-host@a0000000 { compatible = "atmel,sama5d2-sdhci"; reg = <0xa0000000 0x300>; -- 2.5.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wm0-x241.google.com ([2a00:1450:400c:c09::241]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1aJOO8-0000Iq-Sq for linux-mtd@lists.infradead.org; Wed, 13 Jan 2016 16:35:14 +0000 Received: by mail-wm0-x241.google.com with SMTP id f206so37785415wmf.2 for ; Wed, 13 Jan 2016 08:34:57 -0800 (PST) From: Romain Izard To: linux-mtd@lists.infradead.org, devicetree@vger.kernel.org Cc: Yang Wenyou , Josh Wu , Nicolas Ferre , Romain Izard Subject: [PATCH v1 5/5] ARM: at91/dt: sama5d2: add nand0 and nfc0 nodes Date: Wed, 13 Jan 2016 17:34:17 +0100 Message-Id: <1452702857-2240-6-git-send-email-romain.izard.pro@gmail.com> In-Reply-To: <1452702857-2240-1-git-send-email-romain.izard.pro@gmail.com> References: <1452702857-2240-1-git-send-email-romain.izard.pro@gmail.com> List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Both nodes are required to access NAND Flash memory. Additional settings will be necessary at the board level to use it. Signed-off-by: Romain Izard --- arch/arm/boot/dts/sama5d2.dtsi | 38 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi index aee571448342..80420177ec1a 100644 --- a/arch/arm/boot/dts/sama5d2.dtsi +++ b/arch/arm/boot/dts/sama5d2.dtsi @@ -265,6 +265,44 @@ cache-level = <2>; }; + nand0: nand@80000000 { + compatible = "atmel,sama5d2-nand"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + reg = < /* EBI CS3 */ + 0x80000000 0x08000000 + /* SMC PMECC regs */ + 0xf8014070 0x00000490 + /* SMC PMECC Error Location regs */ + 0xf8014500 0x00000200 + /* ROM Galois tables */ + 0x00040000 0x00018000 + >; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH 6>; + atmel,nand-addr-offset = <21>; + atmel,nand-cmd-offset = <22>; + atmel,nand-has-dma; + atmel,has-pmecc; + atmel,pmecc-lookup-table-offset = <0x0 0x8000>; + status = "disabled"; + + nfc@90000000 { + compatible = "atmel,sama5d4-nfc"; + #address-cells = <1>; + #size-cells = <1>; + reg = < /* NFC Command Registers */ + 0xC0000000 0x08000000 + /* NFC HSMC regs */ + 0xf8014000 0x00000070 + /* NFC SRAM banks */ + 0x00100000 0x00100000 + >; + clocks = <&hsmc_clk>; + atmel,write-by-sram; + }; + }; + sdmmc0: sdio-host@a0000000 { compatible = "atmel,sama5d2-sdhci"; reg = <0xa0000000 0x300>; -- 2.5.0