From mboxrd@z Thu Jan 1 00:00:00 1970 From: Arun Siluvery Subject: [PATCH] drm/i915/gen9: Correct max save/restore register count during gpu reset with GuC Date: Mon, 18 Jan 2016 15:59:36 +0000 Message-ID: <1453132776-22229-1-git-send-email-arun.siluvery@linux.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTP id 8CCE96E5C5 for ; Mon, 18 Jan 2016 07:59:44 -0800 (PST) List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org SW4gR3VDIHN1Ym1pc3Npb24gbW9kZSwgZHJpdmVyIGhhcyB0byBwcm92aWRlIGEgbGlzdCBvZiBy ZWdpc3RlcnMgdG8gYmUKc2F2ZS9yZXN0b3JlZCBkdXJpbmcgZ3B1IHJlc2V0LCBtYWtlIHRoZSBt YXggbm8uIG9mIHJlZ2lzdGVycyB2YWx1ZSBjb25zaXN0ZW50CndpdGggdGhhdCBvZiB0aGUgdmFs dWUgZGVmaW5lZCBpbiBGVy4gSWYgdGhleSBhcmUgbm90IGluIHN5bmMgdGhlbiByZWdpc3Rlcgpz YXZlL3Jlc3RvcmUgZHVyaW5nIGdwdSByZXNldCB3b24ndCB3b3JrIGFzIGV4cGVjdGVkLgoKQ2M6 IEFsZXggRGFpIDx5dS5kYWlAaW50ZWwuY29tPgpDYzogRGF2ZSBHb3Jkb24gPGRhdmlkLnMuZ29y ZG9uQGludGVsLmNvbT4KU2lnbmVkLW9mZi1ieTogQXJ1biBTaWx1dmVyeSA8YXJ1bi5zaWx1dmVy eUBsaW51eC5pbnRlbC5jb20+Ci0tLQogZHJpdmVycy9ncHUvZHJtL2k5MTUvaW50ZWxfZ3VjX2Z3 aWYuaCB8IDIgKy0KIDEgZmlsZSBjaGFuZ2VkLCAxIGluc2VydGlvbigrKSwgMSBkZWxldGlvbigt KQoKZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2ludGVsX2d1Y19md2lmLmggYi9k cml2ZXJzL2dwdS9kcm0vaTkxNS9pbnRlbF9ndWNfZndpZi5oCmluZGV4IDEzMGQ5NGMuLjFkODA0 OGIgMTAwNjQ0Ci0tLSBhL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2ludGVsX2d1Y19md2lmLmgKKysr IGIvZHJpdmVycy9ncHUvZHJtL2k5MTUvaW50ZWxfZ3VjX2Z3aWYuaApAQCAtMzcwLDcgKzM3MCw3 IEBAIHN0cnVjdCBndWNfcG9saWNpZXMgewogI2RlZmluZSBHVUNfUkVHU0VUX1NBVkVfREVGQVVM VF9WQUxVRQkweDgKICNkZWZpbmUgR1VDX1JFR1NFVF9TQVZFX0NVUlJFTlRfVkFMVUUJMHgxMAog Ci0jZGVmaW5lIEdVQ19SRUdTRVRfTUFYX1JFR0lTVEVSUwkyMAorI2RlZmluZSBHVUNfUkVHU0VU X01BWF9SRUdJU1RFUlMJMjUKICNkZWZpbmUgR1VDX01NSU9fV0hJVEVfTElTVF9TVEFSVAkweDI0 ZDAKICNkZWZpbmUgR1VDX01NSU9fV0hJVEVfTElTVF9NQVgJCTEyCiAjZGVmaW5lIEdVQ19TM19T QVZFX1NQQUNFX1BBR0VTCQkxMAotLSAKMS45LjEKCl9fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fCkludGVsLWdmeCBtYWlsaW5nIGxpc3QKSW50ZWwtZ2Z4QGxp c3RzLmZyZWVkZXNrdG9wLm9yZwpodHRwOi8vbGlzdHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4v bGlzdGluZm8vaW50ZWwtZ2Z4Cg==