* [U-Boot] [PATCH 1/2] mx6: soc: Add ENET2 mac address support
@ 2016-01-19 13:16 Ye Li
2016-01-19 13:16 ` [U-Boot] [PATCH 2/2] imx: mx6sxsabreauto: Add support for mx6sx SABREAUTO board Ye Li
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Ye Li @ 2016-01-19 13:16 UTC (permalink / raw)
To: u-boot
The i.MX6SX and i.MX6UL has two ENET controllers, add support for reading
MAC address from fuse for ENET2.
Signed-off-by: Ye Li <ye.li@nxp.com>
---
arch/arm/cpu/armv7/mx6/soc.c | 32 +++++++++++++++++++++--------
arch/arm/include/asm/arch-mx6/imx-regs.h | 19 +----------------
2 files changed, 24 insertions(+), 27 deletions(-)
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index bf5ae8c..e521bf2 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -364,15 +364,29 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
struct fuse_bank4_regs *fuse =
(struct fuse_bank4_regs *)bank->fuse_regs;
- u32 value = readl(&fuse->mac_addr_high);
- mac[0] = (value >> 8);
- mac[1] = value ;
-
- value = readl(&fuse->mac_addr_low);
- mac[2] = value >> 24 ;
- mac[3] = value >> 16 ;
- mac[4] = value >> 8 ;
- mac[5] = value ;
+ if ((is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) &&
+ 1 == dev_id) {
+ u32 value = readl(&fuse->mac_addr2);
+ mac[0] = value >> 24 ;
+ mac[1] = value >> 16 ;
+ mac[2] = value >> 8 ;
+ mac[3] = value ;
+
+ value = readl(&fuse->mac_addr_high);
+ mac[4] = value >> 24 ;
+ mac[5] = value >> 16 ;
+
+ } else {
+ u32 value = readl(&fuse->mac_addr_high);
+ mac[0] = (value >> 8);
+ mac[1] = value ;
+
+ value = readl(&fuse->mac_addr_low);
+ mac[2] = value >> 24 ;
+ mac[3] = value >> 16 ;
+ mac[4] = value >> 8 ;
+ mac[5] = value ;
+ }
}
#endif
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index f24525e..d0324a0 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -715,7 +715,6 @@ struct fuse_bank1_regs {
u32 rsvd7[3];
};
-#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
struct fuse_bank4_regs {
u32 sjc_resp_low;
u32 rsvd0[3];
@@ -725,29 +724,13 @@ struct fuse_bank4_regs {
u32 rsvd2[3];
u32 mac_addr_high;
u32 rsvd3[3];
- u32 mac_addr2;
+ u32 mac_addr2; /*For i.MX6SX and i.MX6UL*/
u32 rsvd4[7];
u32 gp1;
u32 rsvd5[3];
u32 gp2;
u32 rsvd6[3];
};
-#else
-struct fuse_bank4_regs {
- u32 sjc_resp_low;
- u32 rsvd0[3];
- u32 sjc_resp_high;
- u32 rsvd1[3];
- u32 mac_addr_low;
- u32 rsvd2[3];
- u32 mac_addr_high;
- u32 rsvd3[0xb];
- u32 gp1;
- u32 rsvd4[3];
- u32 gp2;
- u32 rsvd5[3];
-};
-#endif
struct aipstz_regs {
u32 mprot0;
--
1.7.4.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH 2/2] imx: mx6sxsabreauto: Add support for mx6sx SABREAUTO board
2016-01-19 13:16 [U-Boot] [PATCH 1/2] mx6: soc: Add ENET2 mac address support Ye Li
@ 2016-01-19 13:16 ` Ye Li
2016-01-20 1:34 ` Peng Fan
2016-01-20 1:17 ` [U-Boot] [PATCH 1/2] mx6: soc: Add ENET2 mac address support Peng Fan
2016-01-24 10:35 ` Stefano Babic
2 siblings, 1 reply; 6+ messages in thread
From: Ye Li @ 2016-01-19 13:16 UTC (permalink / raw)
To: u-boot
Initial version for mx6sx SABREAUTO board support with features:
PMIC, QSPI, NAND flash, SD/MMC, USB, Ethernet, I2C, IO Expander.
Signed-off-by: Ye Li <ye.li@nxp.com>
---
arch/arm/cpu/armv7/mx6/Kconfig | 6 +
board/freescale/mx6sxsabreauto/Kconfig | 12 +
board/freescale/mx6sxsabreauto/MAINTAINERS | 6 +
board/freescale/mx6sxsabreauto/Makefile | 6 +
board/freescale/mx6sxsabreauto/imximage.cfg | 136 ++++++
board/freescale/mx6sxsabreauto/mx6sxsabreauto.c | 508 +++++++++++++++++++++++
configs/mx6sxsabreauto_defconfig | 11 +
include/configs/mx6sxsabreauto.h | 212 ++++++++++
8 files changed, 897 insertions(+), 0 deletions(-)
create mode 100644 board/freescale/mx6sxsabreauto/Kconfig
create mode 100644 board/freescale/mx6sxsabreauto/MAINTAINERS
create mode 100644 board/freescale/mx6sxsabreauto/Makefile
create mode 100644 board/freescale/mx6sxsabreauto/imximage.cfg
create mode 100644 board/freescale/mx6sxsabreauto/mx6sxsabreauto.c
create mode 100644 configs/mx6sxsabreauto_defconfig
create mode 100644 include/configs/mx6sxsabreauto.h
diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig
index 8489182..c72a150 100644
--- a/arch/arm/cpu/armv7/mx6/Kconfig
+++ b/arch/arm/cpu/armv7/mx6/Kconfig
@@ -96,6 +96,11 @@ config TARGET_MX6SXSABRESD
select DM
select DM_THERMAL
+config TARGET_MX6SXSABREAUTO
+ bool "mx6sxsabreauto"
+ select DM
+ select DM_THERMAL
+
config TARGET_MX6UL_9X9_EVK
bool "mx6ul_9x9_evk"
select MX6UL
@@ -166,6 +171,7 @@ source "board/freescale/mx6qsabreauto/Kconfig"
source "board/freescale/mx6sabresd/Kconfig"
source "board/freescale/mx6slevk/Kconfig"
source "board/freescale/mx6sxsabresd/Kconfig"
+source "board/freescale/mx6sxsabreauto/Kconfig"
source "board/freescale/mx6ul_14x14_evk/Kconfig"
source "board/gateworks/gw_ventana/Kconfig"
source "board/kosagi/novena/Kconfig"
diff --git a/board/freescale/mx6sxsabreauto/Kconfig b/board/freescale/mx6sxsabreauto/Kconfig
new file mode 100644
index 0000000..ae2ea02
--- /dev/null
+++ b/board/freescale/mx6sxsabreauto/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MX6SXSABREAUTO
+
+config SYS_BOARD
+ default "mx6sxsabreauto"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "mx6sxsabreauto"
+
+endif
diff --git a/board/freescale/mx6sxsabreauto/MAINTAINERS b/board/freescale/mx6sxsabreauto/MAINTAINERS
new file mode 100644
index 0000000..6f2ff44
--- /dev/null
+++ b/board/freescale/mx6sxsabreauto/MAINTAINERS
@@ -0,0 +1,6 @@
+MX6SXSABREAUTO BOARD
+M: Fabio Estevam <fabio.estevam@nxp.com>
+S: Maintained
+F: board/freescale/mx6sxsabreauto/
+F: include/configs/mx6sxsabreauto.h
+F: configs/mx6sxsabreauto_defconfig
diff --git a/board/freescale/mx6sxsabreauto/Makefile b/board/freescale/mx6sxsabreauto/Makefile
new file mode 100644
index 0000000..f0cd1ce
--- /dev/null
+++ b/board/freescale/mx6sxsabreauto/Makefile
@@ -0,0 +1,6 @@
+# (C) Copyright 2014 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := mx6sxsabreauto.o
diff --git a/board/freescale/mx6sxsabreauto/imximage.cfg b/board/freescale/mx6sxsabreauto/imximage.cfg
new file mode 100644
index 0000000..529e555
--- /dev/null
+++ b/board/freescale/mx6sxsabreauto/imximage.cfg
@@ -0,0 +1,136 @@
+/*
+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi/sd/nand/onenand, qspi/nor
+ */
+
+BOOT_FROM sd
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+
+/* Enable all clocks */
+DATA 4 0x020c4068 0xffffffff
+DATA 4 0x020c406c 0xffffffff
+DATA 4 0x020c4070 0xffffffff
+DATA 4 0x020c4074 0xffffffff
+DATA 4 0x020c4078 0xffffffff
+DATA 4 0x020c407c 0xffffffff
+DATA 4 0x020c4080 0xffffffff
+DATA 4 0x020c4084 0xffffffff
+
+/* IOMUX - DDR IO Type */
+DATA 4 0x020e0618 0x000c0000
+DATA 4 0x020e05fc 0x00000000
+
+/* Clock */
+DATA 4 0x020e032c 0x00000030
+
+/* Address */
+DATA 4 0x020e0300 0x00000030
+DATA 4 0x020e02fc 0x00000030
+DATA 4 0x020e05f4 0x00000030
+
+/* Control */
+DATA 4 0x020e0340 0x00000030
+
+DATA 4 0x020e0320 0x00000000
+DATA 4 0x020e0310 0x00000030
+DATA 4 0x020e0314 0x00000030
+DATA 4 0x020e0614 0x00000030
+
+/* Data Strobe */
+DATA 4 0x020e05f8 0x00020000
+DATA 4 0x020e0330 0x00000030
+DATA 4 0x020e0334 0x00000030
+DATA 4 0x020e0338 0x00000030
+DATA 4 0x020e033c 0x00000030
+
+/* Data */
+DATA 4 0x020e0608 0x00020000
+DATA 4 0x020e060c 0x00000030
+DATA 4 0x020e0610 0x00000030
+DATA 4 0x020e061c 0x00000030
+DATA 4 0x020e0620 0x00000030
+DATA 4 0x020e02ec 0x00000030
+DATA 4 0x020e02f0 0x00000030
+DATA 4 0x020e02f4 0x00000030
+DATA 4 0x020e02f8 0x00000030
+
+/* Calibrations - ZQ */
+DATA 4 0x021b0800 0xa1390003
+
+/* Write leveling */
+DATA 4 0x021b080c 0x002C003D
+DATA 4 0x021b0810 0x00110046
+
+/* DQS Read Gate */
+DATA 4 0x021b083c 0x4160016C
+DATA 4 0x021b0840 0x013C016C
+
+/* Read/Write Delay */
+DATA 4 0x021b0848 0x46424446
+DATA 4 0x021b0850 0x3A3C3C3A
+
+DATA 4 0x021b08c0 0x2492244A
+
+/* read data bit delay */
+DATA 4 0x021b081c 0x33333333
+DATA 4 0x021b0820 0x33333333
+DATA 4 0x021b0824 0x33333333
+DATA 4 0x021b0828 0x33333333
+
+/* Complete calibration by forced measurement */
+DATA 4 0x021b08b8 0x00000800
+
+/* MMDC init - DDR3, 64-bit mode, only MMDC0 is initiated */
+DATA 4 0x021b0004 0x0002002d
+DATA 4 0x021b0008 0x00333030
+DATA 4 0x021b000c 0x676b52f3
+DATA 4 0x021b0010 0xb66d8b63
+DATA 4 0x021b0014 0x01ff00db
+DATA 4 0x021b0018 0x00011740
+DATA 4 0x021b001c 0x00008000
+DATA 4 0x021b002c 0x000026d2
+DATA 4 0x021b0030 0x006b1023
+DATA 4 0x021b0040 0x0000007f
+DATA 4 0x021b0000 0x85190000
+
+/* Initialize MT41K256M16HA-125 - MR2 */
+DATA 4 0x021b001c 0x04008032
+/* MR3 */
+DATA 4 0x021b001c 0x00008033
+/* MR1 */
+DATA 4 0x021b001c 0x00068031
+/* MR0 */
+DATA 4 0x021b001c 0x05208030
+/* DDR device ZQ calibration */
+DATA 4 0x021b001c 0x04008040
+
+/* Final DDR setup, before operation start */
+DATA 4 0x021b0020 0x00000800
+DATA 4 0x021b0818 0x00022227
+DATA 4 0x021b0004 0x0002556d
+DATA 4 0x021b0404 0x00011006
+DATA 4 0x021b001c 0x00000000
diff --git a/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c b/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c
new file mode 100644
index 0000000..c9631d2
--- /dev/null
+++ b/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c
@@ -0,0 +1,508 @@
+/*
+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ *
+ * Author: Ye Li <ye.li@nxp.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/boot_mode.h>
+#include <asm/io.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <linux/sizes.h>
+#include <common.h>
+#include <fsl_esdhc.h>
+#include <mmc.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
+#include "../common/pfuze.h"
+#include <usb.h>
+#include <usb/ehci-fsl.h>
+#include <pca953x.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+ PAD_CTL_ODE)
+
+#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
+ PAD_CTL_SPEED_HIGH | \
+ PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
+
+#define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
+
+#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
+
+#define I2C_PMIC 1
+
+#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
+#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
+ PAD_CTL_SRE_FAST)
+#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
+
+/*Define for building port exp gpio, pin starts from 0*/
+#define PORTEXP_IO_NR(chip, pin) \
+ ((chip << 5) + pin)
+
+/*Get the chip addr from a ioexp gpio*/
+#define PORTEXP_IO_TO_CHIP(gpio_nr) \
+ (gpio_nr >> 5)
+
+/*Get the pin number from a ioexp gpio*/
+#define PORTEXP_IO_TO_PIN(gpio_nr) \
+ (gpio_nr & 0x1f)
+
+#define CPU_PER_RST_B PORTEXP_IO_NR(0x30, 4)
+#define STEER_ENET PORTEXP_IO_NR(0x32, 2)
+
+static int port_exp_direction_output(unsigned gpio, int value)
+{
+ int ret;
+
+ i2c_set_bus_num(2);
+ ret = i2c_probe(PORTEXP_IO_TO_CHIP(gpio));
+ if (ret)
+ return ret;
+
+ ret = pca953x_set_dir(PORTEXP_IO_TO_CHIP(gpio),
+ (1 << PORTEXP_IO_TO_PIN(gpio)),
+ (PCA953X_DIR_OUT << PORTEXP_IO_TO_PIN(gpio)));
+
+ if (ret)
+ return ret;
+
+ ret = pca953x_set_val(PORTEXP_IO_TO_CHIP(gpio),
+ (1 << PORTEXP_IO_TO_PIN(gpio)),
+ (value << PORTEXP_IO_TO_PIN(gpio)));
+
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_SIZE;
+
+ return 0;
+}
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+ MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+ MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DATA0__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DATA1__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DATA2__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DATA3__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DATA4__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DATA5__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DATA6__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DATA7__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+ /* CD pin */
+ MX6_PAD_USB_H_DATA__GPIO7_IO_10 | MUX_PAD_CTRL(NO_PAD_CTRL),
+
+ /* RST_B, used for power reset cycle */
+ MX6_PAD_KEY_COL1__GPIO2_IO_11 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc4_pads[] = {
+ MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DATA4__USDHC4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DATA5__USDHC4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DATA6__USDHC4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DATA7__USDHC4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+ /* CD pin */
+ MX6_PAD_USB_H_STROBE__GPIO7_IO_11 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const fec2_pads[] = {
+ MX6_PAD_ENET1_MDC__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET1_MDIO__ENET2_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII2_RX_CTL__ENET2_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+ MX6_PAD_RGMII2_RD0__ENET2_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+ MX6_PAD_RGMII2_RD1__ENET2_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+ MX6_PAD_RGMII2_RD2__ENET2_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+ MX6_PAD_RGMII2_RD3__ENET2_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+ MX6_PAD_RGMII2_RXC__ENET2_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+ MX6_PAD_RGMII2_TX_CTL__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII2_TD0__ENET2_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII2_TD1__ENET2_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII2_TD2__ENET2_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII2_TD3__ENET2_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII2_TXC__ENET2_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+ imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+static int setup_fec(void)
+{
+ struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+ /* Use 125MHz anatop loopback REF_CLK1 for ENET2 */
+ clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, 0);
+
+ return enable_fec_anatop_clock(1, ENET_125MHZ);
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int ret;
+
+ imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads));
+ setup_fec();
+
+ ret = fecmxc_initialize_multi(bis, 1,
+ CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
+ if (ret)
+ printf("FEC%d MXC: %s:failed\n", 1, __func__);
+
+ return ret;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+ /*
+ * Enable 1.8V(SEL_1P5_1P8_POS_REG) on
+ * Phy control debug reg 0
+ */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
+
+ /* rgmii tx clock delay enable */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
+
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+
+ return 0;
+}
+
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+/* I2C2 for PMIC */
+struct i2c_pads_info i2c_pad_info2 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_GPIO1_IO02__I2C2_SCL | PC,
+ .gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO_2 | PC,
+ .gp = IMX_GPIO_NR(1, 2),
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_GPIO1_IO03__I2C2_SDA | PC,
+ .gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO_3 | PC,
+ .gp = IMX_GPIO_NR(1, 3),
+ },
+};
+
+/* I2C3 for IO Expander */
+struct i2c_pads_info i2c_pad_info3 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_KEY_COL4__I2C3_SCL | PC,
+ .gpio_mode = MX6_PAD_KEY_COL4__GPIO2_IO_14 | PC,
+ .gp = IMX_GPIO_NR(2, 14),
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_KEY_ROW4__I2C3_SDA | PC,
+ .gpio_mode = MX6_PAD_KEY_ROW4__GPIO2_IO_19 | PC,
+ .gp = IMX_GPIO_NR(2, 19),
+ },
+};
+
+int power_init_board(void)
+{
+ struct pmic *p;
+
+ p = pfuze_common_init(I2C_PMIC);
+ if (!p)
+ return -ENODEV;
+
+ return 0;
+}
+
+#ifdef CONFIG_USB_EHCI_MX6
+#define USB_OTHERREGS_OFFSET 0x800
+#define UCTRL_PWR_POL (1 << 9)
+
+static iomux_v3_cfg_t const usb_otg_pads[] = {
+ /* OGT1 */
+ MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* OTG2 */
+ MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
+};
+
+static void setup_usb(void)
+{
+ imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
+ ARRAY_SIZE(usb_otg_pads));
+}
+
+int board_usb_phy_mode(int port)
+{
+ if (port == 1)
+ return USB_INIT_HOST;
+ else
+ return usb_phy_mode(port);
+}
+
+int board_ehci_hcd_init(int port)
+{
+ u32 *usbnc_usb_ctrl;
+
+ if (port > 1)
+ return -EINVAL;
+
+ usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
+ port * 4);
+
+ /* Set Power polarity */
+ setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
+
+ return 0;
+}
+#endif
+
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+
+ return 0;
+}
+
+static struct fsl_esdhc_cfg usdhc_cfg[3] = {
+ {USDHC3_BASE_ADDR},
+ {USDHC4_BASE_ADDR},
+};
+
+#define USDHC3_CD_GPIO IMX_GPIO_NR(7, 10)
+#define USDHC3_RST_GPIO IMX_GPIO_NR(2, 11)
+#define USDHC4_CD_GPIO IMX_GPIO_NR(7, 11)
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret = 0;
+
+ switch (cfg->esdhc_base) {
+ case USDHC3_BASE_ADDR:
+ ret = !gpio_get_value(USDHC3_CD_GPIO);
+ break;
+ case USDHC4_BASE_ADDR:
+ ret = !gpio_get_value(USDHC4_CD_GPIO);
+ break;
+ }
+
+ return ret;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ int i, ret;
+
+ /*
+ * According to the board_mmc_init() the following map is done:
+ * (U-boot device node) (Physical Port)
+ * mmc0 USDHC3
+ * mmc1 USDHC4
+ */
+ for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+ switch (i) {
+ case 0:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+ gpio_direction_input(USDHC3_CD_GPIO);
+
+ /* This starts a power cycle for UHS-I. Need to set steer to B0 to A*/
+ gpio_direction_output(USDHC3_RST_GPIO, 0);
+ udelay(1000); /* need 1ms@least */
+ gpio_direction_output(USDHC3_RST_GPIO, 1);
+
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ break;
+ case 1:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
+ gpio_direction_input(USDHC4_CD_GPIO);
+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+ break;
+ default:
+ printf("Warning: you configured more USDHC controllers"
+ "(%d) than supported by the board\n", i + 1);
+ return -EINVAL;
+ }
+
+ ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+ if (ret) {
+ printf("Warning: failed to initialize mmc dev %d\n", i);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+#ifdef CONFIG_FSL_QSPI
+
+#define QSPI_PAD_CTRL1 \
+ (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_HIGH | \
+ PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_40ohm)
+
+static iomux_v3_cfg_t const quadspi_pads[] = {
+ MX6_PAD_QSPI1A_SS0_B__QSPI1_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_QSPI1A_SCLK__QSPI1_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_QSPI1A_DATA0__QSPI1_A_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_QSPI1A_DATA1__QSPI1_A_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_QSPI1A_DATA2__QSPI1_A_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_QSPI1A_DATA3__QSPI1_A_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_QSPI1B_SS0_B__QSPI1_B_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_QSPI1B_SCLK__QSPI1_B_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_QSPI1B_DATA0__QSPI1_B_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_QSPI1B_DATA1__QSPI1_B_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_QSPI1B_DATA2__QSPI1_B_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_QSPI1B_DATA3__QSPI1_B_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+};
+
+int board_qspi_init(void)
+{
+ /* Set the iomux */
+ imx_iomux_v3_setup_multiple_pads(quadspi_pads,
+ ARRAY_SIZE(quadspi_pads));
+
+ /* Set the clock */
+ enable_qspi_clk(0);
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_NAND_MXS
+iomux_v3_cfg_t gpmi_pads[] = {
+ MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0),
+ MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+};
+
+static void setup_gpmi_nand(void)
+{
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ /* config gpmi nand iomux */
+ imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
+
+ setup_gpmi_io_clk((MXC_CCM_CS2CDR_QSPI2_CLK_PODF(0) |
+ MXC_CCM_CS2CDR_QSPI2_CLK_PRED(3) |
+ MXC_CCM_CS2CDR_QSPI2_CLK_SEL(3)));
+
+ /* enable apbh clock gating */
+ setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
+}
+#endif
+
+int board_init(void)
+{
+ /* Address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#ifdef CONFIG_SYS_I2C_MXC
+ setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
+ setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
+#endif
+
+ /* Reset CPU_PER_RST_B signal for enet phy and PCIE */
+ port_exp_direction_output(CPU_PER_RST_B, 0);
+ udelay(500);
+ port_exp_direction_output(CPU_PER_RST_B, 1);
+
+ /* Set steering signal to L for selecting B0 */
+ port_exp_direction_output(STEER_ENET, 0);
+
+#ifdef CONFIG_USB_EHCI_MX6
+ setup_usb();
+#endif
+
+#ifdef CONFIG_FSL_QSPI
+ board_qspi_init();
+#endif
+
+#ifdef CONFIG_NAND_MXS
+ setup_gpmi_nand();
+#endif
+
+ return 0;
+}
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+ {"sda", MAKE_CFGVAL(0x42, 0x30, 0x00, 0x00)},
+ {"sdb", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
+ {"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
+ {"nand", MAKE_CFGVAL(0x82, 0x00, 0x00, 0x00)},
+ {NULL, 0},
+};
+#endif
+
+int board_late_init(void)
+{
+#ifdef CONFIG_CMD_BMODE
+ add_board_boot_modes(board_boot_modes);
+#endif
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: MX6SX SABRE AUTO\n");
+
+ return 0;
+}
diff --git a/configs/mx6sxsabreauto_defconfig b/configs/mx6sxsabreauto_defconfig
new file mode 100644
index 0000000..d9e35df
--- /dev/null
+++ b/configs/mx6sxsabreauto_defconfig
@@ -0,0 +1,11 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_TARGET_MX6SXSABREAUTO=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabreauto/imximage.cfg,MX6SX"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_STMICRO=y
diff --git a/include/configs/mx6sxsabreauto.h b/include/configs/mx6sxsabreauto.h
new file mode 100644
index 0000000..2e739f9
--- /dev/null
+++ b/include/configs/mx6sxsabreauto.h
@@ -0,0 +1,212 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Freescale i.MX6SX Sabreauto board.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "mx6_common.h"
+
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE UART1_BASE
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "script=boot.scr\0" \
+ "image=zImage\0" \
+ "console=ttymxc0\0" \
+ "fdt_high=0xffffffff\0" \
+ "initrd_high=0xffffffff\0" \
+ "fdt_file=imx6sx-sabreauto.dtb\0" \
+ "fdt_addr=0x88000000\0" \
+ "boot_fdt=try\0" \
+ "ip_dyn=yes\0" \
+ "mmcdev=0\0" \
+ "mmcpart=1\0" \
+ "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
+ "mmcargs=setenv bootargs console=${console},${baudrate} " \
+ "root=${mmcroot}\0" \
+ "loadbootscript=" \
+ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+ "bootscript=echo Running bootscript from mmc ...; " \
+ "source\0" \
+ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+ "mmcboot=echo Booting from mmc ...; " \
+ "run mmcargs; " \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if run loadfdt; then " \
+ "bootz ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "if test ${boot_fdt} = try; then " \
+ "bootz; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "fi; " \
+ "else " \
+ "bootz; " \
+ "fi;\0" \
+ "netargs=setenv bootargs console=${console},${baudrate} " \
+ "root=/dev/nfs " \
+ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+ "netboot=echo Booting from net ...; " \
+ "run netargs; " \
+ "if test ${ip_dyn} = yes; then " \
+ "setenv get_cmd dhcp; " \
+ "else " \
+ "setenv get_cmd tftp; " \
+ "fi; " \
+ "${get_cmd} ${image}; " \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+ "bootz ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "if test ${boot_fdt} = try; then " \
+ "bootz; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "fi; " \
+ "else " \
+ "bootz; " \
+ "fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+ "mmc dev ${mmcdev};" \
+ "mmc dev ${mmcdev}; if mmc rescan; then " \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "else " \
+ "if run loadimage; then " \
+ "run mmcboot; " \
+ "else run netboot; " \
+ "fi; " \
+ "fi; " \
+ "else run netboot; fi"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_MEMTEST_START 0x80000000
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000)
+
+#define CONFIG_STACKSIZE SZ_128K
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
+#define PHYS_SDRAM_SIZE SZ_2G
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* MMC Configuration */
+#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR
+
+/* I2C Configs */
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
+#define CONFIG_SYS_I2C_SPEED 100000
+
+/* PMIC */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_PFUZE100
+#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
+
+/* NAND flash command */
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NAND_TRIMFFS
+
+/* NAND stuff */
+#define CONFIG_NAND_MXS
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE 0x40000000
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* DMA stuff, needed for GPMI/MXS NAND support */
+#define CONFIG_APBH_DMA
+#define CONFIG_APBH_DMA_BURST
+#define CONFIG_APBH_DMA_BURST8
+
+/* Network */
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+
+#define IMX_FEC_BASE ENET2_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR 0x0
+
+#define CONFIG_FEC_XCV_TYPE RGMII
+#define CONFIG_ETHPRIME "FEC"
+
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_ATHEROS
+
+
+#define CONFIG_CMD_USB
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX6
+#define CONFIG_USB_STORAGE
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS 0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#endif
+
+#define CONFIG_IMX_THERMAL
+
+#define CONFIG_CMD_TIME
+
+#define CONFIG_FSL_QSPI
+#ifdef CONFIG_FSL_QSPI
+#define CONFIG_CMD_SF
+#define CONFIG_SYS_FSL_QSPI_AHB
+#define CONFIG_SF_DEFAULT_BUS 0
+#define CONFIG_SF_DEFAULT_CS 0
+#define CONFIG_SF_DEFAULT_SPEED 40000000
+#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
+#define FSL_QSPI_FLASH_SIZE SZ_32M
+#define FSL_QSPI_FLASH_NUM 2
+#endif
+
+#define CONFIG_ENV_OFFSET (8 * SZ_64K)
+#define CONFIG_ENV_SIZE SZ_8K
+#define CONFIG_ENV_IS_IN_MMC
+
+#define CONFIG_SYS_FSL_USDHC_NUM 2
+#if defined(CONFIG_ENV_IS_IN_MMC)
+#define CONFIG_SYS_MMC_ENV_DEV 0 /*USDHC3*/
+#endif
+
+#define CONFIG_PCA953X
+#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x30, 8}, {0x32, 8}, {0x34, 8} }
+
+#endif /* __CONFIG_H */
--
1.7.4.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH 1/2] mx6: soc: Add ENET2 mac address support
2016-01-19 13:16 [U-Boot] [PATCH 1/2] mx6: soc: Add ENET2 mac address support Ye Li
2016-01-19 13:16 ` [U-Boot] [PATCH 2/2] imx: mx6sxsabreauto: Add support for mx6sx SABREAUTO board Ye Li
@ 2016-01-20 1:17 ` Peng Fan
2016-01-24 10:35 ` Stefano Babic
2 siblings, 0 replies; 6+ messages in thread
From: Peng Fan @ 2016-01-20 1:17 UTC (permalink / raw)
To: u-boot
On Tue, Jan 19, 2016 at 09:16:35PM +0800, Ye Li wrote:
>The i.MX6SX and i.MX6UL has two ENET controllers, add support for reading
>MAC address from fuse for ENET2.
>
>Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
>---
> arch/arm/cpu/armv7/mx6/soc.c | 32 +++++++++++++++++++++--------
> arch/arm/include/asm/arch-mx6/imx-regs.h | 19 +----------------
> 2 files changed, 24 insertions(+), 27 deletions(-)
>
>diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
>index bf5ae8c..e521bf2 100644
>--- a/arch/arm/cpu/armv7/mx6/soc.c
>+++ b/arch/arm/cpu/armv7/mx6/soc.c
>@@ -364,15 +364,29 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
> struct fuse_bank4_regs *fuse =
> (struct fuse_bank4_regs *)bank->fuse_regs;
>
>- u32 value = readl(&fuse->mac_addr_high);
>- mac[0] = (value >> 8);
>- mac[1] = value ;
>-
>- value = readl(&fuse->mac_addr_low);
>- mac[2] = value >> 24 ;
>- mac[3] = value >> 16 ;
>- mac[4] = value >> 8 ;
>- mac[5] = value ;
>+ if ((is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) &&
>+ 1 == dev_id) {
>+ u32 value = readl(&fuse->mac_addr2);
>+ mac[0] = value >> 24 ;
>+ mac[1] = value >> 16 ;
>+ mac[2] = value >> 8 ;
>+ mac[3] = value ;
>+
>+ value = readl(&fuse->mac_addr_high);
>+ mac[4] = value >> 24 ;
>+ mac[5] = value >> 16 ;
>+
>+ } else {
>+ u32 value = readl(&fuse->mac_addr_high);
>+ mac[0] = (value >> 8);
>+ mac[1] = value ;
>+
>+ value = readl(&fuse->mac_addr_low);
>+ mac[2] = value >> 24 ;
>+ mac[3] = value >> 16 ;
>+ mac[4] = value >> 8 ;
>+ mac[5] = value ;
>+ }
>
> }
> #endif
>diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
>index f24525e..d0324a0 100644
>--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
>+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
>@@ -715,7 +715,6 @@ struct fuse_bank1_regs {
> u32 rsvd7[3];
> };
>
>-#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
> struct fuse_bank4_regs {
> u32 sjc_resp_low;
> u32 rsvd0[3];
>@@ -725,29 +724,13 @@ struct fuse_bank4_regs {
> u32 rsvd2[3];
> u32 mac_addr_high;
> u32 rsvd3[3];
>- u32 mac_addr2;
>+ u32 mac_addr2; /*For i.MX6SX and i.MX6UL*/
> u32 rsvd4[7];
> u32 gp1;
> u32 rsvd5[3];
> u32 gp2;
> u32 rsvd6[3];
> };
>-#else
>-struct fuse_bank4_regs {
>- u32 sjc_resp_low;
>- u32 rsvd0[3];
>- u32 sjc_resp_high;
>- u32 rsvd1[3];
>- u32 mac_addr_low;
>- u32 rsvd2[3];
>- u32 mac_addr_high;
>- u32 rsvd3[0xb];
>- u32 gp1;
>- u32 rsvd4[3];
>- u32 gp2;
>- u32 rsvd5[3];
>-};
>-#endif
>
> struct aipstz_regs {
> u32 mprot0;
>--
>1.7.4.1
>
>_______________________________________________
>U-Boot mailing list
>U-Boot at lists.denx.de
>http://lists.denx.de/mailman/listinfo/u-boot
^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH 2/2] imx: mx6sxsabreauto: Add support for mx6sx SABREAUTO board
2016-01-19 13:16 ` [U-Boot] [PATCH 2/2] imx: mx6sxsabreauto: Add support for mx6sx SABREAUTO board Ye Li
@ 2016-01-20 1:34 ` Peng Fan
0 siblings, 0 replies; 6+ messages in thread
From: Peng Fan @ 2016-01-20 1:34 UTC (permalink / raw)
To: u-boot
On Tue, Jan 19, 2016 at 09:16:36PM +0800, Ye Li wrote:
>Initial version for mx6sx SABREAUTO board support with features:
>PMIC, QSPI, NAND flash, SD/MMC, USB, Ethernet, I2C, IO Expander.
>
>Signed-off-by: Ye Li <ye.li@nxp.com>
Tested-by: Peng Fan <peng.fan@nxp.com>
>---
> arch/arm/cpu/armv7/mx6/Kconfig | 6 +
> board/freescale/mx6sxsabreauto/Kconfig | 12 +
> board/freescale/mx6sxsabreauto/MAINTAINERS | 6 +
> board/freescale/mx6sxsabreauto/Makefile | 6 +
> board/freescale/mx6sxsabreauto/imximage.cfg | 136 ++++++
> board/freescale/mx6sxsabreauto/mx6sxsabreauto.c | 508 +++++++++++++++++++++++
> configs/mx6sxsabreauto_defconfig | 11 +
> include/configs/mx6sxsabreauto.h | 212 ++++++++++
> 8 files changed, 897 insertions(+), 0 deletions(-)
> create mode 100644 board/freescale/mx6sxsabreauto/Kconfig
> create mode 100644 board/freescale/mx6sxsabreauto/MAINTAINERS
> create mode 100644 board/freescale/mx6sxsabreauto/Makefile
> create mode 100644 board/freescale/mx6sxsabreauto/imximage.cfg
> create mode 100644 board/freescale/mx6sxsabreauto/mx6sxsabreauto.c
> create mode 100644 configs/mx6sxsabreauto_defconfig
> create mode 100644 include/configs/mx6sxsabreauto.h
>
>diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig
>index 8489182..c72a150 100644
>--- a/arch/arm/cpu/armv7/mx6/Kconfig
>+++ b/arch/arm/cpu/armv7/mx6/Kconfig
>@@ -96,6 +96,11 @@ config TARGET_MX6SXSABRESD
> select DM
> select DM_THERMAL
>
>+config TARGET_MX6SXSABREAUTO
>+ bool "mx6sxsabreauto"
>+ select DM
>+ select DM_THERMAL
>+
> config TARGET_MX6UL_9X9_EVK
> bool "mx6ul_9x9_evk"
> select MX6UL
>@@ -166,6 +171,7 @@ source "board/freescale/mx6qsabreauto/Kconfig"
> source "board/freescale/mx6sabresd/Kconfig"
> source "board/freescale/mx6slevk/Kconfig"
> source "board/freescale/mx6sxsabresd/Kconfig"
>+source "board/freescale/mx6sxsabreauto/Kconfig"
> source "board/freescale/mx6ul_14x14_evk/Kconfig"
> source "board/gateworks/gw_ventana/Kconfig"
> source "board/kosagi/novena/Kconfig"
>diff --git a/board/freescale/mx6sxsabreauto/Kconfig b/board/freescale/mx6sxsabreauto/Kconfig
>new file mode 100644
>index 0000000..ae2ea02
>--- /dev/null
>+++ b/board/freescale/mx6sxsabreauto/Kconfig
>@@ -0,0 +1,12 @@
>+if TARGET_MX6SXSABREAUTO
>+
>+config SYS_BOARD
>+ default "mx6sxsabreauto"
>+
>+config SYS_VENDOR
>+ default "freescale"
>+
>+config SYS_CONFIG_NAME
>+ default "mx6sxsabreauto"
>+
>+endif
>diff --git a/board/freescale/mx6sxsabreauto/MAINTAINERS b/board/freescale/mx6sxsabreauto/MAINTAINERS
>new file mode 100644
>index 0000000..6f2ff44
>--- /dev/null
>+++ b/board/freescale/mx6sxsabreauto/MAINTAINERS
>@@ -0,0 +1,6 @@
>+MX6SXSABREAUTO BOARD
>+M: Fabio Estevam <fabio.estevam@nxp.com>
>+S: Maintained
>+F: board/freescale/mx6sxsabreauto/
>+F: include/configs/mx6sxsabreauto.h
>+F: configs/mx6sxsabreauto_defconfig
>diff --git a/board/freescale/mx6sxsabreauto/Makefile b/board/freescale/mx6sxsabreauto/Makefile
>new file mode 100644
>index 0000000..f0cd1ce
>--- /dev/null
>+++ b/board/freescale/mx6sxsabreauto/Makefile
>@@ -0,0 +1,6 @@
>+# (C) Copyright 2014 Freescale Semiconductor, Inc.
>+#
>+# SPDX-License-Identifier: GPL-2.0+
>+#
>+
>+obj-y := mx6sxsabreauto.o
>diff --git a/board/freescale/mx6sxsabreauto/imximage.cfg b/board/freescale/mx6sxsabreauto/imximage.cfg
>new file mode 100644
>index 0000000..529e555
>--- /dev/null
>+++ b/board/freescale/mx6sxsabreauto/imximage.cfg
>@@ -0,0 +1,136 @@
>+/*
>+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
>+ *
>+ * SPDX-License-Identifier: GPL-2.0+
>+ */
>+
>+#define __ASSEMBLY__
>+#include <config.h>
>+
>+/* image version */
>+
>+IMAGE_VERSION 2
>+
>+/*
>+ * Boot Device : one of
>+ * spi/sd/nand/onenand, qspi/nor
>+ */
>+
>+BOOT_FROM sd
>+
>+/*
>+ * Device Configuration Data (DCD)
>+ *
>+ * Each entry must have the format:
>+ * Addr-type Address Value
>+ *
>+ * where:
>+ * Addr-type register length (1,2 or 4 bytes)
>+ * Address absolute address of the register
>+ * value value to be stored in the register
>+ */
>+
>+/* Enable all clocks */
>+DATA 4 0x020c4068 0xffffffff
>+DATA 4 0x020c406c 0xffffffff
>+DATA 4 0x020c4070 0xffffffff
>+DATA 4 0x020c4074 0xffffffff
>+DATA 4 0x020c4078 0xffffffff
>+DATA 4 0x020c407c 0xffffffff
>+DATA 4 0x020c4080 0xffffffff
>+DATA 4 0x020c4084 0xffffffff
>+
>+/* IOMUX - DDR IO Type */
>+DATA 4 0x020e0618 0x000c0000
>+DATA 4 0x020e05fc 0x00000000
>+
>+/* Clock */
>+DATA 4 0x020e032c 0x00000030
>+
>+/* Address */
>+DATA 4 0x020e0300 0x00000030
>+DATA 4 0x020e02fc 0x00000030
>+DATA 4 0x020e05f4 0x00000030
>+
>+/* Control */
>+DATA 4 0x020e0340 0x00000030
>+
>+DATA 4 0x020e0320 0x00000000
>+DATA 4 0x020e0310 0x00000030
>+DATA 4 0x020e0314 0x00000030
>+DATA 4 0x020e0614 0x00000030
>+
>+/* Data Strobe */
>+DATA 4 0x020e05f8 0x00020000
>+DATA 4 0x020e0330 0x00000030
>+DATA 4 0x020e0334 0x00000030
>+DATA 4 0x020e0338 0x00000030
>+DATA 4 0x020e033c 0x00000030
>+
>+/* Data */
>+DATA 4 0x020e0608 0x00020000
>+DATA 4 0x020e060c 0x00000030
>+DATA 4 0x020e0610 0x00000030
>+DATA 4 0x020e061c 0x00000030
>+DATA 4 0x020e0620 0x00000030
>+DATA 4 0x020e02ec 0x00000030
>+DATA 4 0x020e02f0 0x00000030
>+DATA 4 0x020e02f4 0x00000030
>+DATA 4 0x020e02f8 0x00000030
>+
>+/* Calibrations - ZQ */
>+DATA 4 0x021b0800 0xa1390003
>+
>+/* Write leveling */
>+DATA 4 0x021b080c 0x002C003D
>+DATA 4 0x021b0810 0x00110046
>+
>+/* DQS Read Gate */
>+DATA 4 0x021b083c 0x4160016C
>+DATA 4 0x021b0840 0x013C016C
>+
>+/* Read/Write Delay */
>+DATA 4 0x021b0848 0x46424446
>+DATA 4 0x021b0850 0x3A3C3C3A
>+
>+DATA 4 0x021b08c0 0x2492244A
>+
>+/* read data bit delay */
>+DATA 4 0x021b081c 0x33333333
>+DATA 4 0x021b0820 0x33333333
>+DATA 4 0x021b0824 0x33333333
>+DATA 4 0x021b0828 0x33333333
>+
>+/* Complete calibration by forced measurement */
>+DATA 4 0x021b08b8 0x00000800
>+
>+/* MMDC init - DDR3, 64-bit mode, only MMDC0 is initiated */
>+DATA 4 0x021b0004 0x0002002d
>+DATA 4 0x021b0008 0x00333030
>+DATA 4 0x021b000c 0x676b52f3
>+DATA 4 0x021b0010 0xb66d8b63
>+DATA 4 0x021b0014 0x01ff00db
>+DATA 4 0x021b0018 0x00011740
>+DATA 4 0x021b001c 0x00008000
>+DATA 4 0x021b002c 0x000026d2
>+DATA 4 0x021b0030 0x006b1023
>+DATA 4 0x021b0040 0x0000007f
>+DATA 4 0x021b0000 0x85190000
>+
>+/* Initialize MT41K256M16HA-125 - MR2 */
>+DATA 4 0x021b001c 0x04008032
>+/* MR3 */
>+DATA 4 0x021b001c 0x00008033
>+/* MR1 */
>+DATA 4 0x021b001c 0x00068031
>+/* MR0 */
>+DATA 4 0x021b001c 0x05208030
>+/* DDR device ZQ calibration */
>+DATA 4 0x021b001c 0x04008040
>+
>+/* Final DDR setup, before operation start */
>+DATA 4 0x021b0020 0x00000800
>+DATA 4 0x021b0818 0x00022227
>+DATA 4 0x021b0004 0x0002556d
>+DATA 4 0x021b0404 0x00011006
>+DATA 4 0x021b001c 0x00000000
>diff --git a/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c b/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c
>new file mode 100644
>index 0000000..c9631d2
>--- /dev/null
>+++ b/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c
>@@ -0,0 +1,508 @@
>+/*
>+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
>+ *
>+ * Author: Ye Li <ye.li@nxp.com>
>+ *
>+ * SPDX-License-Identifier: GPL-2.0+
>+ */
>+
>+#include <asm/arch/clock.h>
>+#include <asm/arch/crm_regs.h>
>+#include <asm/arch/iomux.h>
>+#include <asm/arch/imx-regs.h>
>+#include <asm/arch/mx6-pins.h>
>+#include <asm/arch/sys_proto.h>
>+#include <asm/gpio.h>
>+#include <asm/imx-common/iomux-v3.h>
>+#include <asm/imx-common/boot_mode.h>
>+#include <asm/io.h>
>+#include <asm/imx-common/mxc_i2c.h>
>+#include <linux/sizes.h>
>+#include <common.h>
>+#include <fsl_esdhc.h>
>+#include <mmc.h>
>+#include <i2c.h>
>+#include <miiphy.h>
>+#include <netdev.h>
>+#include <power/pmic.h>
>+#include <power/pfuze100_pmic.h>
>+#include "../common/pfuze.h"
>+#include <usb.h>
>+#include <usb/ehci-fsl.h>
>+#include <pca953x.h>
>+
>+DECLARE_GLOBAL_DATA_PTR;
>+
>+#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
>+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
>+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
>+
>+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
>+ PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
>+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
>+
>+#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
>+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
>+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
>+ PAD_CTL_ODE)
>+
>+#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
>+ PAD_CTL_SPEED_HIGH | \
>+ PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
>+
>+#define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
>+ PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
>+
>+#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
>+ PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
>+
>+#define I2C_PMIC 1
>+
>+#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
>+#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
>+ PAD_CTL_SRE_FAST)
>+#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
>+
>+/*Define for building port exp gpio, pin starts from 0*/
>+#define PORTEXP_IO_NR(chip, pin) \
>+ ((chip << 5) + pin)
>+
>+/*Get the chip addr from a ioexp gpio*/
>+#define PORTEXP_IO_TO_CHIP(gpio_nr) \
>+ (gpio_nr >> 5)
>+
>+/*Get the pin number from a ioexp gpio*/
>+#define PORTEXP_IO_TO_PIN(gpio_nr) \
>+ (gpio_nr & 0x1f)
>+
>+#define CPU_PER_RST_B PORTEXP_IO_NR(0x30, 4)
>+#define STEER_ENET PORTEXP_IO_NR(0x32, 2)
>+
>+static int port_exp_direction_output(unsigned gpio, int value)
>+{
>+ int ret;
>+
>+ i2c_set_bus_num(2);
>+ ret = i2c_probe(PORTEXP_IO_TO_CHIP(gpio));
>+ if (ret)
>+ return ret;
>+
>+ ret = pca953x_set_dir(PORTEXP_IO_TO_CHIP(gpio),
>+ (1 << PORTEXP_IO_TO_PIN(gpio)),
>+ (PCA953X_DIR_OUT << PORTEXP_IO_TO_PIN(gpio)));
>+
>+ if (ret)
>+ return ret;
>+
>+ ret = pca953x_set_val(PORTEXP_IO_TO_CHIP(gpio),
>+ (1 << PORTEXP_IO_TO_PIN(gpio)),
>+ (value << PORTEXP_IO_TO_PIN(gpio)));
>+
>+ if (ret)
>+ return ret;
>+
>+ return 0;
>+}
>+
>+int dram_init(void)
>+{
>+ gd->ram_size = PHYS_SDRAM_SIZE;
>+
>+ return 0;
>+}
>+
>+static iomux_v3_cfg_t const uart1_pads[] = {
>+ MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
>+ MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
>+};
>+
>+static iomux_v3_cfg_t const usdhc3_pads[] = {
>+ MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>+ MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>+ MX6_PAD_SD3_DATA0__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>+ MX6_PAD_SD3_DATA1__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>+ MX6_PAD_SD3_DATA2__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>+ MX6_PAD_SD3_DATA3__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>+ MX6_PAD_SD3_DATA4__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>+ MX6_PAD_SD3_DATA5__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>+ MX6_PAD_SD3_DATA6__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>+ MX6_PAD_SD3_DATA7__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>+
>+ /* CD pin */
>+ MX6_PAD_USB_H_DATA__GPIO7_IO_10 | MUX_PAD_CTRL(NO_PAD_CTRL),
>+
>+ /* RST_B, used for power reset cycle */
>+ MX6_PAD_KEY_COL1__GPIO2_IO_11 | MUX_PAD_CTRL(NO_PAD_CTRL),
>+};
>+
>+static iomux_v3_cfg_t const usdhc4_pads[] = {
>+ MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>+ MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>+ MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>+ MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>+ MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>+ MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>+ MX6_PAD_SD4_DATA4__USDHC4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>+ MX6_PAD_SD4_DATA5__USDHC4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>+ MX6_PAD_SD4_DATA6__USDHC4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>+ MX6_PAD_SD4_DATA7__USDHC4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>+
>+ /* CD pin */
>+ MX6_PAD_USB_H_STROBE__GPIO7_IO_11 | MUX_PAD_CTRL(NO_PAD_CTRL),
>+};
>+
>+static iomux_v3_cfg_t const fec2_pads[] = {
>+ MX6_PAD_ENET1_MDC__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
>+ MX6_PAD_ENET1_MDIO__ENET2_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
>+ MX6_PAD_RGMII2_RX_CTL__ENET2_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
>+ MX6_PAD_RGMII2_RD0__ENET2_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
>+ MX6_PAD_RGMII2_RD1__ENET2_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
>+ MX6_PAD_RGMII2_RD2__ENET2_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
>+ MX6_PAD_RGMII2_RD3__ENET2_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
>+ MX6_PAD_RGMII2_RXC__ENET2_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
>+ MX6_PAD_RGMII2_TX_CTL__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
>+ MX6_PAD_RGMII2_TD0__ENET2_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
>+ MX6_PAD_RGMII2_TD1__ENET2_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
>+ MX6_PAD_RGMII2_TD2__ENET2_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
>+ MX6_PAD_RGMII2_TD3__ENET2_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
>+ MX6_PAD_RGMII2_TXC__ENET2_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
>+};
>+
>+static void setup_iomux_uart(void)
>+{
>+ imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
>+}
>+
>+static int setup_fec(void)
>+{
>+ struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
>+
>+ /* Use 125MHz anatop loopback REF_CLK1 for ENET2 */
>+ clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, 0);
>+
>+ return enable_fec_anatop_clock(1, ENET_125MHZ);
>+}
>+
>+int board_eth_init(bd_t *bis)
>+{
>+ int ret;
>+
>+ imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads));
>+ setup_fec();
>+
>+ ret = fecmxc_initialize_multi(bis, 1,
>+ CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
>+ if (ret)
>+ printf("FEC%d MXC: %s:failed\n", 1, __func__);
>+
>+ return ret;
>+}
>+
>+int board_phy_config(struct phy_device *phydev)
>+{
>+ /*
>+ * Enable 1.8V(SEL_1P5_1P8_POS_REG) on
>+ * Phy control debug reg 0
>+ */
>+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
>+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
>+
>+ /* rgmii tx clock delay enable */
>+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
>+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
>+
>+ if (phydev->drv->config)
>+ phydev->drv->config(phydev);
>+
>+ return 0;
>+}
>+
>+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
>+/* I2C2 for PMIC */
>+struct i2c_pads_info i2c_pad_info2 = {
>+ .scl = {
>+ .i2c_mode = MX6_PAD_GPIO1_IO02__I2C2_SCL | PC,
>+ .gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO_2 | PC,
>+ .gp = IMX_GPIO_NR(1, 2),
>+ },
>+ .sda = {
>+ .i2c_mode = MX6_PAD_GPIO1_IO03__I2C2_SDA | PC,
>+ .gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO_3 | PC,
>+ .gp = IMX_GPIO_NR(1, 3),
>+ },
>+};
>+
>+/* I2C3 for IO Expander */
>+struct i2c_pads_info i2c_pad_info3 = {
>+ .scl = {
>+ .i2c_mode = MX6_PAD_KEY_COL4__I2C3_SCL | PC,
>+ .gpio_mode = MX6_PAD_KEY_COL4__GPIO2_IO_14 | PC,
>+ .gp = IMX_GPIO_NR(2, 14),
>+ },
>+ .sda = {
>+ .i2c_mode = MX6_PAD_KEY_ROW4__I2C3_SDA | PC,
>+ .gpio_mode = MX6_PAD_KEY_ROW4__GPIO2_IO_19 | PC,
>+ .gp = IMX_GPIO_NR(2, 19),
>+ },
>+};
>+
>+int power_init_board(void)
>+{
>+ struct pmic *p;
>+
>+ p = pfuze_common_init(I2C_PMIC);
>+ if (!p)
>+ return -ENODEV;
>+
>+ return 0;
>+}
>+
>+#ifdef CONFIG_USB_EHCI_MX6
>+#define USB_OTHERREGS_OFFSET 0x800
>+#define UCTRL_PWR_POL (1 << 9)
>+
>+static iomux_v3_cfg_t const usb_otg_pads[] = {
>+ /* OGT1 */
>+ MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
>+ MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
>+ /* OTG2 */
>+ MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
>+};
>+
>+static void setup_usb(void)
>+{
>+ imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
>+ ARRAY_SIZE(usb_otg_pads));
>+}
>+
>+int board_usb_phy_mode(int port)
>+{
>+ if (port == 1)
>+ return USB_INIT_HOST;
>+ else
>+ return usb_phy_mode(port);
>+}
>+
>+int board_ehci_hcd_init(int port)
>+{
>+ u32 *usbnc_usb_ctrl;
>+
>+ if (port > 1)
>+ return -EINVAL;
>+
>+ usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
>+ port * 4);
>+
>+ /* Set Power polarity */
>+ setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
>+
>+ return 0;
>+}
>+#endif
>+
>+int board_early_init_f(void)
>+{
>+ setup_iomux_uart();
>+
>+ return 0;
>+}
>+
>+static struct fsl_esdhc_cfg usdhc_cfg[3] = {
>+ {USDHC3_BASE_ADDR},
>+ {USDHC4_BASE_ADDR},
>+};
>+
>+#define USDHC3_CD_GPIO IMX_GPIO_NR(7, 10)
>+#define USDHC3_RST_GPIO IMX_GPIO_NR(2, 11)
>+#define USDHC4_CD_GPIO IMX_GPIO_NR(7, 11)
>+
>+int board_mmc_getcd(struct mmc *mmc)
>+{
>+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
>+ int ret = 0;
>+
>+ switch (cfg->esdhc_base) {
>+ case USDHC3_BASE_ADDR:
>+ ret = !gpio_get_value(USDHC3_CD_GPIO);
>+ break;
>+ case USDHC4_BASE_ADDR:
>+ ret = !gpio_get_value(USDHC4_CD_GPIO);
>+ break;
>+ }
>+
>+ return ret;
>+}
>+
>+int board_mmc_init(bd_t *bis)
>+{
>+ int i, ret;
>+
>+ /*
>+ * According to the board_mmc_init() the following map is done:
>+ * (U-boot device node) (Physical Port)
>+ * mmc0 USDHC3
>+ * mmc1 USDHC4
>+ */
>+ for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
>+ switch (i) {
>+ case 0:
>+ imx_iomux_v3_setup_multiple_pads(
>+ usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
>+ gpio_direction_input(USDHC3_CD_GPIO);
>+
>+ /* This starts a power cycle for UHS-I. Need to set steer to B0 to A*/
>+ gpio_direction_output(USDHC3_RST_GPIO, 0);
>+ udelay(1000); /* need 1ms at least */
>+ gpio_direction_output(USDHC3_RST_GPIO, 1);
>+
>+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
>+ break;
>+ case 1:
>+ imx_iomux_v3_setup_multiple_pads(
>+ usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
>+ gpio_direction_input(USDHC4_CD_GPIO);
>+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
>+ break;
>+ default:
>+ printf("Warning: you configured more USDHC controllers"
>+ "(%d) than supported by the board\n", i + 1);
>+ return -EINVAL;
>+ }
>+
>+ ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
>+ if (ret) {
>+ printf("Warning: failed to initialize mmc dev %d\n", i);
>+ return ret;
>+ }
>+ }
>+
>+ return 0;
>+}
>+
>+#ifdef CONFIG_FSL_QSPI
>+
>+#define QSPI_PAD_CTRL1 \
>+ (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_HIGH | \
>+ PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_40ohm)
>+
>+static iomux_v3_cfg_t const quadspi_pads[] = {
>+ MX6_PAD_QSPI1A_SS0_B__QSPI1_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
>+ MX6_PAD_QSPI1A_SCLK__QSPI1_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
>+ MX6_PAD_QSPI1A_DATA0__QSPI1_A_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
>+ MX6_PAD_QSPI1A_DATA1__QSPI1_A_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
>+ MX6_PAD_QSPI1A_DATA2__QSPI1_A_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
>+ MX6_PAD_QSPI1A_DATA3__QSPI1_A_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
>+ MX6_PAD_QSPI1B_SS0_B__QSPI1_B_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
>+ MX6_PAD_QSPI1B_SCLK__QSPI1_B_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
>+ MX6_PAD_QSPI1B_DATA0__QSPI1_B_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
>+ MX6_PAD_QSPI1B_DATA1__QSPI1_B_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
>+ MX6_PAD_QSPI1B_DATA2__QSPI1_B_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
>+ MX6_PAD_QSPI1B_DATA3__QSPI1_B_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
>+};
>+
>+int board_qspi_init(void)
>+{
>+ /* Set the iomux */
>+ imx_iomux_v3_setup_multiple_pads(quadspi_pads,
>+ ARRAY_SIZE(quadspi_pads));
>+
>+ /* Set the clock */
>+ enable_qspi_clk(0);
>+
>+ return 0;
>+}
>+#endif
>+
>+#ifdef CONFIG_NAND_MXS
>+iomux_v3_cfg_t gpmi_pads[] = {
>+ MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
>+ MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
>+ MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
>+ MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0),
>+ MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
>+ MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
>+ MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
>+ MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
>+ MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
>+ MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
>+ MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
>+ MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
>+ MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
>+ MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
>+ MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
>+};
>+
>+static void setup_gpmi_nand(void)
>+{
>+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
>+
>+ /* config gpmi nand iomux */
>+ imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
>+
>+ setup_gpmi_io_clk((MXC_CCM_CS2CDR_QSPI2_CLK_PODF(0) |
>+ MXC_CCM_CS2CDR_QSPI2_CLK_PRED(3) |
>+ MXC_CCM_CS2CDR_QSPI2_CLK_SEL(3)));
>+
>+ /* enable apbh clock gating */
>+ setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
>+}
>+#endif
>+
>+int board_init(void)
>+{
>+ /* Address of boot parameters */
>+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
>+
>+#ifdef CONFIG_SYS_I2C_MXC
>+ setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
>+ setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
>+#endif
>+
>+ /* Reset CPU_PER_RST_B signal for enet phy and PCIE */
>+ port_exp_direction_output(CPU_PER_RST_B, 0);
>+ udelay(500);
>+ port_exp_direction_output(CPU_PER_RST_B, 1);
>+
>+ /* Set steering signal to L for selecting B0 */
>+ port_exp_direction_output(STEER_ENET, 0);
>+
>+#ifdef CONFIG_USB_EHCI_MX6
>+ setup_usb();
>+#endif
>+
>+#ifdef CONFIG_FSL_QSPI
>+ board_qspi_init();
>+#endif
>+
>+#ifdef CONFIG_NAND_MXS
>+ setup_gpmi_nand();
>+#endif
>+
>+ return 0;
>+}
>+
>+#ifdef CONFIG_CMD_BMODE
>+static const struct boot_mode board_boot_modes[] = {
>+ {"sda", MAKE_CFGVAL(0x42, 0x30, 0x00, 0x00)},
>+ {"sdb", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
>+ {"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
>+ {"nand", MAKE_CFGVAL(0x82, 0x00, 0x00, 0x00)},
>+ {NULL, 0},
>+};
>+#endif
>+
>+int board_late_init(void)
>+{
>+#ifdef CONFIG_CMD_BMODE
>+ add_board_boot_modes(board_boot_modes);
>+#endif
>+
>+ return 0;
>+}
>+
>+int checkboard(void)
>+{
>+ puts("Board: MX6SX SABRE AUTO\n");
>+
>+ return 0;
>+}
>diff --git a/configs/mx6sxsabreauto_defconfig b/configs/mx6sxsabreauto_defconfig
>new file mode 100644
>index 0000000..d9e35df
>--- /dev/null
>+++ b/configs/mx6sxsabreauto_defconfig
>@@ -0,0 +1,11 @@
>+CONFIG_ARM=y
>+CONFIG_ARCH_MX6=y
>+CONFIG_TARGET_MX6SXSABREAUTO=y
>+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabreauto/imximage.cfg,MX6SX"
>+# CONFIG_CMD_IMLS is not set
>+# CONFIG_CMD_FLASH is not set
>+CONFIG_CMD_GPIO=y
>+# CONFIG_CMD_SETEXPR is not set
>+CONFIG_SPI_FLASH=y
>+CONFIG_SPI_FLASH_BAR=y
>+CONFIG_SPI_FLASH_STMICRO=y
>diff --git a/include/configs/mx6sxsabreauto.h b/include/configs/mx6sxsabreauto.h
>new file mode 100644
>index 0000000..2e739f9
>--- /dev/null
>+++ b/include/configs/mx6sxsabreauto.h
>@@ -0,0 +1,212 @@
>+/*
>+ * Copyright 2014 Freescale Semiconductor, Inc.
>+ *
>+ * Configuration settings for the Freescale i.MX6SX Sabreauto board.
>+ *
>+ * SPDX-License-Identifier: GPL-2.0+
>+ */
>+
>+
>+#ifndef __CONFIG_H
>+#define __CONFIG_H
>+
>+#include "mx6_common.h"
>+
>+
>+/* Size of malloc() pool */
>+#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M)
>+
>+#define CONFIG_BOARD_EARLY_INIT_F
>+#define CONFIG_BOARD_LATE_INIT
>+
>+#define CONFIG_MXC_UART
>+#define CONFIG_MXC_UART_BASE UART1_BASE
>+
>+#define CONFIG_EXTRA_ENV_SETTINGS \
>+ "script=boot.scr\0" \
>+ "image=zImage\0" \
>+ "console=ttymxc0\0" \
>+ "fdt_high=0xffffffff\0" \
>+ "initrd_high=0xffffffff\0" \
>+ "fdt_file=imx6sx-sabreauto.dtb\0" \
>+ "fdt_addr=0x88000000\0" \
>+ "boot_fdt=try\0" \
>+ "ip_dyn=yes\0" \
>+ "mmcdev=0\0" \
>+ "mmcpart=1\0" \
>+ "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
>+ "mmcargs=setenv bootargs console=${console},${baudrate} " \
>+ "root=${mmcroot}\0" \
>+ "loadbootscript=" \
>+ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
>+ "bootscript=echo Running bootscript from mmc ...; " \
>+ "source\0" \
>+ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
>+ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
>+ "mmcboot=echo Booting from mmc ...; " \
>+ "run mmcargs; " \
>+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
>+ "if run loadfdt; then " \
>+ "bootz ${loadaddr} - ${fdt_addr}; " \
>+ "else " \
>+ "if test ${boot_fdt} = try; then " \
>+ "bootz; " \
>+ "else " \
>+ "echo WARN: Cannot load the DT; " \
>+ "fi; " \
>+ "fi; " \
>+ "else " \
>+ "bootz; " \
>+ "fi;\0" \
>+ "netargs=setenv bootargs console=${console},${baudrate} " \
>+ "root=/dev/nfs " \
>+ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
>+ "netboot=echo Booting from net ...; " \
>+ "run netargs; " \
>+ "if test ${ip_dyn} = yes; then " \
>+ "setenv get_cmd dhcp; " \
>+ "else " \
>+ "setenv get_cmd tftp; " \
>+ "fi; " \
>+ "${get_cmd} ${image}; " \
>+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
>+ "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
>+ "bootz ${loadaddr} - ${fdt_addr}; " \
>+ "else " \
>+ "if test ${boot_fdt} = try; then " \
>+ "bootz; " \
>+ "else " \
>+ "echo WARN: Cannot load the DT; " \
>+ "fi; " \
>+ "fi; " \
>+ "else " \
>+ "bootz; " \
>+ "fi;\0"
>+
>+#define CONFIG_BOOTCOMMAND \
>+ "mmc dev ${mmcdev};" \
>+ "mmc dev ${mmcdev}; if mmc rescan; then " \
>+ "if run loadbootscript; then " \
>+ "run bootscript; " \
>+ "else " \
>+ "if run loadimage; then " \
>+ "run mmcboot; " \
>+ "else run netboot; " \
>+ "fi; " \
>+ "fi; " \
>+ "else run netboot; fi"
>+
>+/* Miscellaneous configurable options */
>+#define CONFIG_SYS_MEMTEST_START 0x80000000
>+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000)
>+
>+#define CONFIG_STACKSIZE SZ_128K
>+
>+/* Physical Memory Map */
>+#define CONFIG_NR_DRAM_BANKS 1
>+#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
>+#define PHYS_SDRAM_SIZE SZ_2G
>+
>+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
>+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
>+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
>+
>+#define CONFIG_SYS_INIT_SP_OFFSET \
>+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
>+#define CONFIG_SYS_INIT_SP_ADDR \
>+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
>+
>+/* MMC Configuration */
>+#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR
>+
>+/* I2C Configs */
>+#define CONFIG_CMD_I2C
>+#define CONFIG_SYS_I2C
>+#define CONFIG_SYS_I2C_MXC
>+#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
>+#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
>+#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
>+#define CONFIG_SYS_I2C_SPEED 100000
>+
>+/* PMIC */
>+#define CONFIG_POWER
>+#define CONFIG_POWER_I2C
>+#define CONFIG_POWER_PFUZE100
>+#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
>+
>+/* NAND flash command */
>+#define CONFIG_CMD_NAND
>+#define CONFIG_CMD_NAND_TRIMFFS
>+
>+/* NAND stuff */
>+#define CONFIG_NAND_MXS
>+#define CONFIG_SYS_MAX_NAND_DEVICE 1
>+#define CONFIG_SYS_NAND_BASE 0x40000000
>+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
>+#define CONFIG_SYS_NAND_ONFI_DETECTION
>+
>+/* DMA stuff, needed for GPMI/MXS NAND support */
>+#define CONFIG_APBH_DMA
>+#define CONFIG_APBH_DMA_BURST
>+#define CONFIG_APBH_DMA_BURST8
>+
>+/* Network */
>+#define CONFIG_CMD_PING
>+#define CONFIG_CMD_DHCP
>+#define CONFIG_CMD_MII
>+
>+#define CONFIG_FEC_MXC
>+#define CONFIG_MII
>+
>+#define IMX_FEC_BASE ENET2_BASE_ADDR
>+#define CONFIG_FEC_MXC_PHYADDR 0x0
>+
>+#define CONFIG_FEC_XCV_TYPE RGMII
>+#define CONFIG_ETHPRIME "FEC"
>+
>+#define CONFIG_PHYLIB
>+#define CONFIG_PHY_ATHEROS
>+
>+
>+#define CONFIG_CMD_USB
>+#ifdef CONFIG_CMD_USB
>+#define CONFIG_USB_EHCI
>+#define CONFIG_USB_EHCI_MX6
>+#define CONFIG_USB_STORAGE
>+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
>+#define CONFIG_USB_HOST_ETHER
>+#define CONFIG_USB_ETHER_ASIX
>+#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
>+#define CONFIG_MXC_USB_FLAGS 0
>+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
>+#endif
>+
>+#define CONFIG_IMX_THERMAL
>+
>+#define CONFIG_CMD_TIME
>+
>+#define CONFIG_FSL_QSPI
>+#ifdef CONFIG_FSL_QSPI
>+#define CONFIG_CMD_SF
>+#define CONFIG_SYS_FSL_QSPI_AHB
>+#define CONFIG_SF_DEFAULT_BUS 0
>+#define CONFIG_SF_DEFAULT_CS 0
>+#define CONFIG_SF_DEFAULT_SPEED 40000000
>+#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
>+#define FSL_QSPI_FLASH_SIZE SZ_32M
>+#define FSL_QSPI_FLASH_NUM 2
>+#endif
>+
>+#define CONFIG_ENV_OFFSET (8 * SZ_64K)
>+#define CONFIG_ENV_SIZE SZ_8K
>+#define CONFIG_ENV_IS_IN_MMC
>+
>+#define CONFIG_SYS_FSL_USDHC_NUM 2
>+#if defined(CONFIG_ENV_IS_IN_MMC)
>+#define CONFIG_SYS_MMC_ENV_DEV 0 /*USDHC3*/
>+#endif
>+
>+#define CONFIG_PCA953X
>+#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x30, 8}, {0x32, 8}, {0x34, 8} }
>+
>+#endif /* __CONFIG_H */
>--
>1.7.4.1
>
>_______________________________________________
>U-Boot mailing list
>U-Boot at lists.denx.de
>http://lists.denx.de/mailman/listinfo/u-boot
^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH 1/2] mx6: soc: Add ENET2 mac address support
2016-01-19 13:16 [U-Boot] [PATCH 1/2] mx6: soc: Add ENET2 mac address support Ye Li
2016-01-19 13:16 ` [U-Boot] [PATCH 2/2] imx: mx6sxsabreauto: Add support for mx6sx SABREAUTO board Ye Li
2016-01-20 1:17 ` [U-Boot] [PATCH 1/2] mx6: soc: Add ENET2 mac address support Peng Fan
@ 2016-01-24 10:35 ` Stefano Babic
2016-01-25 3:24 ` Ye Li
2 siblings, 1 reply; 6+ messages in thread
From: Stefano Babic @ 2016-01-24 10:35 UTC (permalink / raw)
To: u-boot
Hi Ye,
On 19/01/2016 14:16, Ye Li wrote:
> The i.MX6SX and i.MX6UL has two ENET controllers, add support for reading
> MAC address from fuse for ENET2.
>
> Signed-off-by: Ye Li <ye.li@nxp.com>
> ---
> arch/arm/cpu/armv7/mx6/soc.c | 32 +++++++++++++++++++++--------
> arch/arm/include/asm/arch-mx6/imx-regs.h | 19 +----------------
> 2 files changed, 24 insertions(+), 27 deletions(-)
>
> diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
> index bf5ae8c..e521bf2 100644
> --- a/arch/arm/cpu/armv7/mx6/soc.c
> +++ b/arch/arm/cpu/armv7/mx6/soc.c
> @@ -364,15 +364,29 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
> struct fuse_bank4_regs *fuse =
> (struct fuse_bank4_regs *)bank->fuse_regs;
>
> - u32 value = readl(&fuse->mac_addr_high);
> - mac[0] = (value >> 8);
> - mac[1] = value ;
> -
> - value = readl(&fuse->mac_addr_low);
> - mac[2] = value >> 24 ;
> - mac[3] = value >> 16 ;
> - mac[4] = value >> 8 ;
> - mac[5] = value ;
I beg your pardon, but I need your help to better understand it with the
manual. References are Application Processor manual for MX6Q and MX6X.
Currently, we support loading the MAC address from fuses (all other
i.MX6 with just one FEC) reading the fuses MAC_ADDRESS[31:0] and
MAC_ADDRESS[47:32] as stated, for example, in Table 5-19 for i.MX6Q.
In i.MX6SX manual, there is no an additional entry for the second MAC
address, and in my understanding GP1[31:0] is used. This is ok if we
agree on that, but it should be documented in doc/README.imx6, that
already explains the case with a single controller
> + if ((is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) &&
> + 1 == dev_id) {
> + u32 value = readl(&fuse->mac_addr2);
> + mac[0] = value >> 24 ;
> + mac[1] = value >> 16 ;
> + mac[2] = value >> 8 ;
> + mac[3] = value ;
> +
> + value = readl(&fuse->mac_addr_high);
> + mac[4] = value >> 24 ;
> + mac[5] = value >> 16 ;
> +
I admit I have not understood why the order is exchanged. Should be
mac_addr_high not be identical to the two controllers, and just the
lower part different ? Here mac_addr_high goes into mac[4,5], while for
id = 0 it goes into mac[0,1]. Do I miss something ? Or is the manual not
updated ?
> + } else {
> + u32 value = readl(&fuse->mac_addr_high);
> + mac[0] = (value >> 8);
> + mac[1] = value ;
> +
> + value = readl(&fuse->mac_addr_low);
> + mac[2] = value >> 24 ;
> + mac[3] = value >> 16 ;
> + mac[4] = value >> 8 ;
> + mac[5] = value ;
> + }
>
> }
> #endif
> diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
> index f24525e..d0324a0 100644
> --- a/arch/arm/include/asm/arch-mx6/imx-regs.h
> +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
> @@ -715,7 +715,6 @@ struct fuse_bank1_regs {
> u32 rsvd7[3];
> };
>
> -#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
> struct fuse_bank4_regs {
> u32 sjc_resp_low;
> u32 rsvd0[3];
> @@ -725,29 +724,13 @@ struct fuse_bank4_regs {
> u32 rsvd2[3];
> u32 mac_addr_high;
> u32 rsvd3[3];
> - u32 mac_addr2;
> + u32 mac_addr2; /*For i.MX6SX and i.MX6UL*/
> u32 rsvd4[7];
> u32 gp1;
> u32 rsvd5[3];
> u32 gp2;
> u32 rsvd6[3];
> };
> -#else
> -struct fuse_bank4_regs {
> - u32 sjc_resp_low;
> - u32 rsvd0[3];
> - u32 sjc_resp_high;
> - u32 rsvd1[3];
> - u32 mac_addr_low;
> - u32 rsvd2[3];
> - u32 mac_addr_high;
> - u32 rsvd3[0xb];
> - u32 gp1;
> - u32 rsvd4[3];
> - u32 gp2;
> - u32 rsvd5[3];
> -};
> -#endif
>
> struct aipstz_regs {
> u32 mprot0;
>
Best regards,
Stefano Babic
--
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^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH 1/2] mx6: soc: Add ENET2 mac address support
2016-01-24 10:35 ` Stefano Babic
@ 2016-01-25 3:24 ` Ye Li
0 siblings, 0 replies; 6+ messages in thread
From: Ye Li @ 2016-01-25 3:24 UTC (permalink / raw)
To: u-boot
Hi Stefano,
On 1/24/2016 6:35 PM, Stefano Babic wrote:
> Hi Ye,
>
> On 19/01/2016 14:16, Ye Li wrote:
>> The i.MX6SX and i.MX6UL has two ENET controllers, add support for reading
>> MAC address from fuse for ENET2.
>>
>> Signed-off-by: Ye Li <ye.li@nxp.com>
>> ---
>> arch/arm/cpu/armv7/mx6/soc.c | 32 +++++++++++++++++++++--------
>> arch/arm/include/asm/arch-mx6/imx-regs.h | 19 +----------------
>> 2 files changed, 24 insertions(+), 27 deletions(-)
>>
>> diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
>> index bf5ae8c..e521bf2 100644
>> --- a/arch/arm/cpu/armv7/mx6/soc.c
>> +++ b/arch/arm/cpu/armv7/mx6/soc.c
>> @@ -364,15 +364,29 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
>> struct fuse_bank4_regs *fuse =
>> (struct fuse_bank4_regs *)bank->fuse_regs;
>>
>> - u32 value = readl(&fuse->mac_addr_high);
>> - mac[0] = (value >> 8);
>> - mac[1] = value ;
>> -
>> - value = readl(&fuse->mac_addr_low);
>> - mac[2] = value >> 24 ;
>> - mac[3] = value >> 16 ;
>> - mac[4] = value >> 8 ;
>> - mac[5] = value ;
> I beg your pardon, but I need your help to better understand it with the
> manual. References are Application Processor manual for MX6Q and MX6X.
>
> Currently, we support loading the MAC address from fuses (all other
> i.MX6 with just one FEC) reading the fuses MAC_ADDRESS[31:0] and
> MAC_ADDRESS[47:32] as stated, for example, in Table 5-19 for i.MX6Q.
>
> In i.MX6SX manual, there is no an additional entry for the second MAC
> address, and in my understanding GP1[31:0] is used. This is ok if we
> agree on that, but it should be documented in doc/README.imx6, that
> already explains the case with a single controller
The fuse map table seems not update that fuse in i.MX6SX manual. But in OCOTP chapter, I can find the new OCOTP_MAC2. It is at the offset 0x640, not the GP1[31:0].
I agree the README.imx6 needs updating for second controller. I will add it in patch v2.
>> + if ((is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) &&
>> + 1 == dev_id) {
>> + u32 value = readl(&fuse->mac_addr2);
>> + mac[0] = value >> 24 ;
>> + mac[1] = value >> 16 ;
>> + mac[2] = value >> 8 ;
>> + mac[3] = value ;
>> +
>> + value = readl(&fuse->mac_addr_high);
>> + mac[4] = value >> 24 ;
>> + mac[5] = value >> 16 ;
>> +
> I admit I have not understood why the order is exchanged. Should be
> mac_addr_high not be identical to the two controllers, and just the
> lower part different ? Here mac_addr_high goes into mac[4,5], while for
> id = 0 it goes into mac[0,1]. Do I miss something ? Or is the manual not
> updated ?
>
The layout for MAC2 address is low bytes 4 and 5 come from the mac_addr_high and other high bytes from the mac_addr2. The name "mac_addr_high" only means to MAC1.
>> + } else {
>> + u32 value = readl(&fuse->mac_addr_high);
>> + mac[0] = (value >> 8);
>> + mac[1] = value ;
>> +
>> + value = readl(&fuse->mac_addr_low);
>> + mac[2] = value >> 24 ;
>> + mac[3] = value >> 16 ;
>> + mac[4] = value >> 8 ;
>> + mac[5] = value ;
>> + }
>
>>
>> }
>> #endif
>> diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
>> index f24525e..d0324a0 100644
>> --- a/arch/arm/include/asm/arch-mx6/imx-regs.h
>> +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
>> @@ -715,7 +715,6 @@ struct fuse_bank1_regs {
>> u32 rsvd7[3];
>> };
>>
>> -#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
>> struct fuse_bank4_regs {
>> u32 sjc_resp_low;
>> u32 rsvd0[3];
>> @@ -725,29 +724,13 @@ struct fuse_bank4_regs {
>> u32 rsvd2[3];
>> u32 mac_addr_high;
>> u32 rsvd3[3];
>> - u32 mac_addr2;
>> + u32 mac_addr2; /*For i.MX6SX and i.MX6UL*/
>> u32 rsvd4[7];
>> u32 gp1;
>> u32 rsvd5[3];
>> u32 gp2;
>> u32 rsvd6[3];
>> };
>> -#else
>> -struct fuse_bank4_regs {
>> - u32 sjc_resp_low;
>> - u32 rsvd0[3];
>> - u32 sjc_resp_high;
>> - u32 rsvd1[3];
>> - u32 mac_addr_low;
>> - u32 rsvd2[3];
>> - u32 mac_addr_high;
>> - u32 rsvd3[0xb];
>> - u32 gp1;
>> - u32 rsvd4[3];
>> - u32 gp2;
>> - u32 rsvd5[3];
>> -};
>> -#endif
>>
>> struct aipstz_regs {
>> u32 mprot0;
>>
> Best regards,
> Stefano Babic
>
Best regards,
Ye Li
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2016-01-25 3:24 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-01-19 13:16 [U-Boot] [PATCH 1/2] mx6: soc: Add ENET2 mac address support Ye Li
2016-01-19 13:16 ` [U-Boot] [PATCH 2/2] imx: mx6sxsabreauto: Add support for mx6sx SABREAUTO board Ye Li
2016-01-20 1:34 ` Peng Fan
2016-01-20 1:17 ` [U-Boot] [PATCH 1/2] mx6: soc: Add ENET2 mac address support Peng Fan
2016-01-24 10:35 ` Stefano Babic
2016-01-25 3:24 ` Ye Li
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