From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47830) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aNVjs-0002cB-6F for qemu-devel@nongnu.org; Sun, 24 Jan 2016 20:14:44 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aNVjp-0000eb-3O for qemu-devel@nongnu.org; Sun, 24 Jan 2016 20:14:40 -0500 From: David Gibson Date: Mon, 25 Jan 2016 12:15:22 +1100 Message-Id: <1453684527-23564-24-git-send-email-david@gibson.dropbear.id.au> In-Reply-To: <1453684527-23564-1-git-send-email-david@gibson.dropbear.id.au> References: <1453684527-23564-1-git-send-email-david@gibson.dropbear.id.au> Subject: [Qemu-devel] [PULL 23/28] target-ppc: gdbstub: fix altivec registers for little-endian guests List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: peter.maydell@linaro.org Cc: lvivier@redhat.com, thuth@redhat.com, mark.cave-ayland@ilande.co.uk, agraf@suse.de, qemu-devel@nongnu.org, qemu-ppc@nongnu.org, bharata@linux.vnet.ibm.com, David Gibson , gkurz@linux.vnet.ibm.com From: Greg Kurz Altivec registers are 128-bit wide. They are stored in memory as two 64-bit values that must be byteswapped when the guest is little-endian. Let's reuse the ppc_maybe_bswap_register() helper for this. We also need to fix the ordering of the 64-bit elements according to the target endianness, for both system and user mode. Signed-off-by: Greg Kurz Signed-off-by: David Gibson --- target-ppc/translate_init.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index 54720ca..4c29912 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -8754,9 +8754,9 @@ static void dump_ppc_insns (CPUPPCState *env) static bool avr_need_swap(CPUPPCState *env) { #ifdef HOST_WORDS_BIGENDIAN - return false; + return msr_le; #else - return true; + return !msr_le; #endif } @@ -8800,14 +8800,18 @@ static int gdb_get_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n) stq_p(mem_buf, env->avr[n].u64[1]); stq_p(mem_buf+8, env->avr[n].u64[0]); } + ppc_maybe_bswap_register(env, mem_buf, 8); + ppc_maybe_bswap_register(env, mem_buf + 8, 8); return 16; } if (n == 32) { stl_p(mem_buf, env->vscr); + ppc_maybe_bswap_register(env, mem_buf, 4); return 4; } if (n == 33) { stl_p(mem_buf, (uint32_t)env->spr[SPR_VRSAVE]); + ppc_maybe_bswap_register(env, mem_buf, 4); return 4; } return 0; @@ -8816,6 +8820,8 @@ static int gdb_get_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n) static int gdb_set_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n) { if (n < 32) { + ppc_maybe_bswap_register(env, mem_buf, 8); + ppc_maybe_bswap_register(env, mem_buf + 8, 8); if (!avr_need_swap(env)) { env->avr[n].u64[0] = ldq_p(mem_buf); env->avr[n].u64[1] = ldq_p(mem_buf+8); @@ -8826,10 +8832,12 @@ static int gdb_set_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n) return 16; } if (n == 32) { + ppc_maybe_bswap_register(env, mem_buf, 4); env->vscr = ldl_p(mem_buf); return 4; } if (n == 33) { + ppc_maybe_bswap_register(env, mem_buf, 4); env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf); return 4; } -- 2.5.0