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From: Borislav Petkov <bp@alien8.de>
To: Ingo Molnar <mingo@kernel.org>
Cc: LKML <linux-kernel@vger.kernel.org>
Subject: [PATCH 4/8] x86/mce/AMD: Do not perform shared bank check for future processors
Date: Mon, 25 Jan 2016 20:41:49 +0100	[thread overview]
Message-ID: <1453750913-4781-5-git-send-email-bp@alien8.de> (raw)
In-Reply-To: <1453750913-4781-1-git-send-email-bp@alien8.de>

From: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>

Fam17h and above should not require a check to see if a bank is shared
or not. For shared banks, there will always be only one core that has
visibility over the MSRs and only that particular core will be allowed
to write to the MSRs.

Fix the code to return early if we have Scalable MCA support. No change
in functionality for earlier processors.

Boris: Fold in fix from kbuild test robot for:

  arch/x86/kernel/cpu/mcheck/mce_amd.c:93:9-10: WARNING: return of 0/1 in function 'is_shared_bank' with return type bool
  Generated by: scripts/coccinelle/misc/boolreturn.cocci

Signed-off-by: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
Cc: linux-edac <linux-edac@vger.kernel.org>
Cc: Tony Luck <tony.luck@intel.com>
Cc: x86-ml <x86@kernel.org>
Link: http://lkml.kernel.org/r/1452901836-27632-3-git-send-email-Aravind.Gopalakrishnan@amd.com
Signed-off-by: Fengguang Wu <fengguang.wu@intel.com>
[ Boris: massage text. ]
Signed-off-by: Borislav Petkov <bp@suse.de>
---
 arch/x86/kernel/cpu/mcheck/mce_amd.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c
index e99b15077e94..3068ce25dfa1 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_amd.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c
@@ -84,6 +84,13 @@ struct thresh_restart {
 
 static inline bool is_shared_bank(int bank)
 {
+	/*
+	 * Scalable MCA provides for only one core to have access to the MSRs of
+	 * a shared bank.
+	 */
+	if (mce_flags.smca)
+		return false;
+
 	/* Bank 4 is for northbridge reporting and is thus shared */
 	return (bank == 4);
 }
-- 
2.3.5

  parent reply	other threads:[~2016-01-25 19:43 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-01-25 19:41 [PATCH 0/8] tip-queue 2016-01-25 Borislav Petkov
2016-01-25 19:41 ` [PATCH 1/8] x86/traps.c: Refactor preemption and interrupt flag handling Borislav Petkov
2016-02-01 11:39   ` [tip:x86/asm] x86/entry/traps: " tip-bot for Alexander Kuleshov
2016-01-25 19:41 ` [PATCH 2/8] x86/cpufeature: Use enum cpuid_leafs instead of magic numbers Borislav Petkov
2016-02-01 11:40   ` [tip:x86/cpu] " tip-bot for Huaitong Han
2016-01-25 19:41 ` [PATCH 3/8] x86/mce: Fix order of AMD MCE init function call Borislav Petkov
2016-02-01 11:40   ` [tip:ras/core] " tip-bot for Aravind Gopalakrishnan
2016-01-25 19:41 ` Borislav Petkov [this message]
2016-02-01 11:40   ` [tip:ras/core] x86/mce/AMD: Do not perform shared bank check for future processors tip-bot for Aravind Gopalakrishnan
2016-01-25 19:41 ` [PATCH 5/8] x86/mce/AMD: Reduce number of blocks scanned per bank Borislav Petkov
2016-02-01 11:41   ` [tip:ras/core] " tip-bot for Aravind Gopalakrishnan
2016-01-25 19:41 ` [PATCH 6/8] x86/mce/AMD: Fix LVT offset configuration for thresholding Borislav Petkov
2016-02-01 11:41   ` [tip:ras/core] " tip-bot for Aravind Gopalakrishnan
2016-01-25 19:41 ` [PATCH 7/8] x86/mce/AMD: Carve out threshold block preparation Borislav Petkov
2016-02-01 11:41   ` [tip:ras/core] " tip-bot for Borislav Petkov
2016-01-25 19:41 ` [PATCH 8/8] x86/mce/AMD: Set MCAX Enable bit Borislav Petkov
2016-02-01 11:42   ` [tip:ras/core] " tip-bot for Aravind Gopalakrishnan

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