* [PATCH 1/8] x86/traps.c: Refactor preemption and interrupt flag handling
2016-01-25 19:41 [PATCH 0/8] tip-queue 2016-01-25 Borislav Petkov
@ 2016-01-25 19:41 ` Borislav Petkov
2016-02-01 11:39 ` [tip:x86/asm] x86/entry/traps: " tip-bot for Alexander Kuleshov
2016-01-25 19:41 ` [PATCH 2/8] x86/cpufeature: Use enum cpuid_leafs instead of magic numbers Borislav Petkov
` (6 subsequent siblings)
7 siblings, 1 reply; 17+ messages in thread
From: Borislav Petkov @ 2016-01-25 19:41 UTC (permalink / raw)
To: Ingo Molnar; +Cc: LKML
From: Alexander Kuleshov <kuleshovmail@gmail.com>
Make the preemption and interrupt flag handling more readable by
removing preempt_conditional_sti() and preempt_conditional_cli() helpers
and using preempt_disable() and preempt_enable_no_resched() instead.
Rename contitional_sti() and conditional_cli() to the more
understandable cond_local_irq_enable() and cond_local_irq_disable()
respectively, while at it.
Signed-off-by: Alexander Kuleshov <kuleshovmail@gmail.com>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Suggested-by: Borislav Petkov <bp@suse.de>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Dave Hansen <dave.hansen@linux.intel.com>
Cc: "H Peter Anvin" <hpa@zytor.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Wang Nan <wangnan0@huawei.com>
Cc: x86-ml <x86@kernel.org>
Link: http://lkml.kernel.org/r/1453036184-15077-1-git-send-email-kuleshovmail@gmail.com
[ Boris: massage text. ]
Signed-off-by: Borislav Petkov <bp@suse.de>
---
arch/x86/kernel/traps.c | 47 +++++++++++++++++++----------------------------
1 file changed, 19 insertions(+), 28 deletions(-)
diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c
index ade185a46b1d..410e8e2700c5 100644
--- a/arch/x86/kernel/traps.c
+++ b/arch/x86/kernel/traps.c
@@ -83,30 +83,16 @@ gate_desc idt_table[NR_VECTORS] __page_aligned_bss;
DECLARE_BITMAP(used_vectors, NR_VECTORS);
EXPORT_SYMBOL_GPL(used_vectors);
-static inline void conditional_sti(struct pt_regs *regs)
+static inline void cond_local_irq_enable(struct pt_regs *regs)
{
if (regs->flags & X86_EFLAGS_IF)
local_irq_enable();
}
-static inline void preempt_conditional_sti(struct pt_regs *regs)
-{
- preempt_count_inc();
- if (regs->flags & X86_EFLAGS_IF)
- local_irq_enable();
-}
-
-static inline void conditional_cli(struct pt_regs *regs)
-{
- if (regs->flags & X86_EFLAGS_IF)
- local_irq_disable();
-}
-
-static inline void preempt_conditional_cli(struct pt_regs *regs)
+static inline void cond_local_irq_disable(struct pt_regs *regs)
{
if (regs->flags & X86_EFLAGS_IF)
local_irq_disable();
- preempt_count_dec();
}
void ist_enter(struct pt_regs *regs)
@@ -286,7 +272,7 @@ static void do_error_trap(struct pt_regs *regs, long error_code, char *str,
if (notify_die(DIE_TRAP, str, regs, error_code, trapnr, signr) !=
NOTIFY_STOP) {
- conditional_sti(regs);
+ cond_local_irq_enable(regs);
do_trap(trapnr, signr, str, regs, error_code,
fill_trap_info(regs, signr, trapnr, &info));
}
@@ -368,7 +354,7 @@ dotraplinkage void do_bounds(struct pt_regs *regs, long error_code)
if (notify_die(DIE_TRAP, "bounds", regs, error_code,
X86_TRAP_BR, SIGSEGV) == NOTIFY_STOP)
return;
- conditional_sti(regs);
+ cond_local_irq_enable(regs);
if (!user_mode(regs))
die("bounds", regs, error_code);
@@ -443,7 +429,7 @@ do_general_protection(struct pt_regs *regs, long error_code)
struct task_struct *tsk;
RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU");
- conditional_sti(regs);
+ cond_local_irq_enable(regs);
if (v8086_mode(regs)) {
local_irq_enable();
@@ -517,9 +503,11 @@ dotraplinkage void notrace do_int3(struct pt_regs *regs, long error_code)
* as we may switch to the interrupt stack.
*/
debug_stack_usage_inc();
- preempt_conditional_sti(regs);
+ preempt_disable();
+ cond_local_irq_enable(regs);
do_trap(X86_TRAP_BP, SIGTRAP, "int3", regs, error_code, NULL);
- preempt_conditional_cli(regs);
+ cond_local_irq_disable(regs);
+ preempt_enable_no_resched();
debug_stack_usage_dec();
exit:
ist_exit(regs);
@@ -648,12 +636,14 @@ dotraplinkage void do_debug(struct pt_regs *regs, long error_code)
debug_stack_usage_inc();
/* It's safe to allow irq's after DR6 has been saved */
- preempt_conditional_sti(regs);
+ preempt_disable();
+ cond_local_irq_enable(regs);
if (v8086_mode(regs)) {
handle_vm86_trap((struct kernel_vm86_regs *) regs, error_code,
X86_TRAP_DB);
- preempt_conditional_cli(regs);
+ cond_local_irq_disable(regs);
+ preempt_enable_no_resched();
debug_stack_usage_dec();
goto exit;
}
@@ -673,7 +663,8 @@ dotraplinkage void do_debug(struct pt_regs *regs, long error_code)
si_code = get_si_code(tsk->thread.debugreg6);
if (tsk->thread.debugreg6 & (DR_STEP | DR_TRAP_BITS) || user_icebp)
send_sigtrap(tsk, regs, error_code, si_code);
- preempt_conditional_cli(regs);
+ cond_local_irq_disable(regs);
+ preempt_enable_no_resched();
debug_stack_usage_dec();
exit:
@@ -696,7 +687,7 @@ static void math_error(struct pt_regs *regs, int error_code, int trapnr)
if (notify_die(DIE_TRAP, str, regs, error_code, trapnr, SIGFPE) == NOTIFY_STOP)
return;
- conditional_sti(regs);
+ cond_local_irq_enable(regs);
if (!user_mode(regs)) {
if (!fixup_exception(regs)) {
@@ -743,7 +734,7 @@ do_simd_coprocessor_error(struct pt_regs *regs, long error_code)
dotraplinkage void
do_spurious_interrupt_bug(struct pt_regs *regs, long error_code)
{
- conditional_sti(regs);
+ cond_local_irq_enable(regs);
}
dotraplinkage void
@@ -756,7 +747,7 @@ do_device_not_available(struct pt_regs *regs, long error_code)
if (read_cr0() & X86_CR0_EM) {
struct math_emu_info info = { };
- conditional_sti(regs);
+ cond_local_irq_enable(regs);
info.regs = regs;
math_emulate(&info);
@@ -765,7 +756,7 @@ do_device_not_available(struct pt_regs *regs, long error_code)
#endif
fpu__restore(¤t->thread.fpu); /* interrupts still off */
#ifdef CONFIG_X86_32
- conditional_sti(regs);
+ cond_local_irq_enable(regs);
#endif
}
NOKPROBE_SYMBOL(do_device_not_available);
--
2.3.5
^ permalink raw reply related [flat|nested] 17+ messages in thread* [tip:x86/asm] x86/entry/traps: Refactor preemption and interrupt flag handling
2016-01-25 19:41 ` [PATCH 1/8] x86/traps.c: Refactor preemption and interrupt flag handling Borislav Petkov
@ 2016-02-01 11:39 ` tip-bot for Alexander Kuleshov
0 siblings, 0 replies; 17+ messages in thread
From: tip-bot for Alexander Kuleshov @ 2016-02-01 11:39 UTC (permalink / raw)
To: linux-tip-commits
Cc: dave.hansen, tony.luck, bp, wangnan0, bp, peterz, kuleshovmail,
torvalds, tglx, luto, hpa, mingo, linux-kernel
Commit-ID: d99e1bd175f4291ddb6e62b22bb5bdbe3976389a
Gitweb: http://git.kernel.org/tip/d99e1bd175f4291ddb6e62b22bb5bdbe3976389a
Author: Alexander Kuleshov <kuleshovmail@gmail.com>
AuthorDate: Mon, 25 Jan 2016 20:41:46 +0100
Committer: Ingo Molnar <mingo@kernel.org>
CommitDate: Mon, 1 Feb 2016 10:45:14 +0100
x86/entry/traps: Refactor preemption and interrupt flag handling
Make the preemption and interrupt flag handling more readable by
removing preempt_conditional_sti() and preempt_conditional_cli()
helpers and using preempt_disable() and
preempt_enable_no_resched() instead.
Rename contitional_sti() and conditional_cli() to the more
understandable cond_local_irq_enable() and
cond_local_irq_disable() respectively, while at it.
Suggested-by: Borislav Petkov <bp@suse.de>
Signed-off-by: Alexander Kuleshov <kuleshovmail@gmail.com>
[ Boris: massage text. ]
Signed-off-by: Borislav Petkov <bp@suse.de>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Dave Hansen <dave.hansen@linux.intel.com>
Cc: H Peter Anvin <hpa@zytor.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Tony Luck <tony.luck@intel.com>
Cc: Wang Nan <wangnan0@huawei.com>
Link: http://lkml.kernel.org/r/1453750913-4781-2-git-send-email-bp@alien8.de
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
arch/x86/kernel/traps.c | 47 +++++++++++++++++++----------------------------
1 file changed, 19 insertions(+), 28 deletions(-)
diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c
index ade185a..410e8e2 100644
--- a/arch/x86/kernel/traps.c
+++ b/arch/x86/kernel/traps.c
@@ -83,30 +83,16 @@ gate_desc idt_table[NR_VECTORS] __page_aligned_bss;
DECLARE_BITMAP(used_vectors, NR_VECTORS);
EXPORT_SYMBOL_GPL(used_vectors);
-static inline void conditional_sti(struct pt_regs *regs)
+static inline void cond_local_irq_enable(struct pt_regs *regs)
{
if (regs->flags & X86_EFLAGS_IF)
local_irq_enable();
}
-static inline void preempt_conditional_sti(struct pt_regs *regs)
-{
- preempt_count_inc();
- if (regs->flags & X86_EFLAGS_IF)
- local_irq_enable();
-}
-
-static inline void conditional_cli(struct pt_regs *regs)
-{
- if (regs->flags & X86_EFLAGS_IF)
- local_irq_disable();
-}
-
-static inline void preempt_conditional_cli(struct pt_regs *regs)
+static inline void cond_local_irq_disable(struct pt_regs *regs)
{
if (regs->flags & X86_EFLAGS_IF)
local_irq_disable();
- preempt_count_dec();
}
void ist_enter(struct pt_regs *regs)
@@ -286,7 +272,7 @@ static void do_error_trap(struct pt_regs *regs, long error_code, char *str,
if (notify_die(DIE_TRAP, str, regs, error_code, trapnr, signr) !=
NOTIFY_STOP) {
- conditional_sti(regs);
+ cond_local_irq_enable(regs);
do_trap(trapnr, signr, str, regs, error_code,
fill_trap_info(regs, signr, trapnr, &info));
}
@@ -368,7 +354,7 @@ dotraplinkage void do_bounds(struct pt_regs *regs, long error_code)
if (notify_die(DIE_TRAP, "bounds", regs, error_code,
X86_TRAP_BR, SIGSEGV) == NOTIFY_STOP)
return;
- conditional_sti(regs);
+ cond_local_irq_enable(regs);
if (!user_mode(regs))
die("bounds", regs, error_code);
@@ -443,7 +429,7 @@ do_general_protection(struct pt_regs *regs, long error_code)
struct task_struct *tsk;
RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU");
- conditional_sti(regs);
+ cond_local_irq_enable(regs);
if (v8086_mode(regs)) {
local_irq_enable();
@@ -517,9 +503,11 @@ dotraplinkage void notrace do_int3(struct pt_regs *regs, long error_code)
* as we may switch to the interrupt stack.
*/
debug_stack_usage_inc();
- preempt_conditional_sti(regs);
+ preempt_disable();
+ cond_local_irq_enable(regs);
do_trap(X86_TRAP_BP, SIGTRAP, "int3", regs, error_code, NULL);
- preempt_conditional_cli(regs);
+ cond_local_irq_disable(regs);
+ preempt_enable_no_resched();
debug_stack_usage_dec();
exit:
ist_exit(regs);
@@ -648,12 +636,14 @@ dotraplinkage void do_debug(struct pt_regs *regs, long error_code)
debug_stack_usage_inc();
/* It's safe to allow irq's after DR6 has been saved */
- preempt_conditional_sti(regs);
+ preempt_disable();
+ cond_local_irq_enable(regs);
if (v8086_mode(regs)) {
handle_vm86_trap((struct kernel_vm86_regs *) regs, error_code,
X86_TRAP_DB);
- preempt_conditional_cli(regs);
+ cond_local_irq_disable(regs);
+ preempt_enable_no_resched();
debug_stack_usage_dec();
goto exit;
}
@@ -673,7 +663,8 @@ dotraplinkage void do_debug(struct pt_regs *regs, long error_code)
si_code = get_si_code(tsk->thread.debugreg6);
if (tsk->thread.debugreg6 & (DR_STEP | DR_TRAP_BITS) || user_icebp)
send_sigtrap(tsk, regs, error_code, si_code);
- preempt_conditional_cli(regs);
+ cond_local_irq_disable(regs);
+ preempt_enable_no_resched();
debug_stack_usage_dec();
exit:
@@ -696,7 +687,7 @@ static void math_error(struct pt_regs *regs, int error_code, int trapnr)
if (notify_die(DIE_TRAP, str, regs, error_code, trapnr, SIGFPE) == NOTIFY_STOP)
return;
- conditional_sti(regs);
+ cond_local_irq_enable(regs);
if (!user_mode(regs)) {
if (!fixup_exception(regs)) {
@@ -743,7 +734,7 @@ do_simd_coprocessor_error(struct pt_regs *regs, long error_code)
dotraplinkage void
do_spurious_interrupt_bug(struct pt_regs *regs, long error_code)
{
- conditional_sti(regs);
+ cond_local_irq_enable(regs);
}
dotraplinkage void
@@ -756,7 +747,7 @@ do_device_not_available(struct pt_regs *regs, long error_code)
if (read_cr0() & X86_CR0_EM) {
struct math_emu_info info = { };
- conditional_sti(regs);
+ cond_local_irq_enable(regs);
info.regs = regs;
math_emulate(&info);
@@ -765,7 +756,7 @@ do_device_not_available(struct pt_regs *regs, long error_code)
#endif
fpu__restore(¤t->thread.fpu); /* interrupts still off */
#ifdef CONFIG_X86_32
- conditional_sti(regs);
+ cond_local_irq_enable(regs);
#endif
}
NOKPROBE_SYMBOL(do_device_not_available);
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 2/8] x86/cpufeature: Use enum cpuid_leafs instead of magic numbers
2016-01-25 19:41 [PATCH 0/8] tip-queue 2016-01-25 Borislav Petkov
2016-01-25 19:41 ` [PATCH 1/8] x86/traps.c: Refactor preemption and interrupt flag handling Borislav Petkov
@ 2016-01-25 19:41 ` Borislav Petkov
2016-02-01 11:40 ` [tip:x86/cpu] " tip-bot for Huaitong Han
2016-01-25 19:41 ` [PATCH 3/8] x86/mce: Fix order of AMD MCE init function call Borislav Petkov
` (5 subsequent siblings)
7 siblings, 1 reply; 17+ messages in thread
From: Borislav Petkov @ 2016-01-25 19:41 UTC (permalink / raw)
To: Ingo Molnar; +Cc: LKML
From: Huaitong Han <huaitong.han@intel.com>
Most of magic numbers of x86_capability have been converted to enum
cpuid_leafs, and this patch does update the remaining part.
Signed-off-by: Huaitong Han <huaitong.han@intel.com>
Cc: Alexander Kuleshov <kuleshovmail@gmail.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Cc: Brian Gerst <brgerst@gmail.com>
Cc: David Vrabel <david.vrabel@citrix.com>
Cc: Denys Vlasenko <dvlasenk@redhat.com>
Cc: Hector Marco-Gisbert <hecmargi@upv.es>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiang Liu <jiang.liu@linux.intel.com>
Cc: Kees Cook <keescook@chromium.org>
Cc: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Cc: lguest@lists.ozlabs.org
Cc: Rusty Russell <rusty@rustcorp.com.au>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Viresh Kumar <viresh.kumar@linaro.org>
Cc: x86-ml <x86@kernel.org>
Cc: xen-devel@lists.xenproject.org
Link: http://lkml.kernel.org/r/1453374160-4648-1-git-send-email-huaitong.han@intel.com
Signed-off-by: Borislav Petkov <bp@suse.de>
---
arch/x86/include/asm/elf.h | 2 +-
arch/x86/kernel/mpparse.c | 2 +-
arch/x86/lguest/boot.c | 2 +-
arch/x86/xen/enlighten.c | 2 +-
4 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/x86/include/asm/elf.h b/arch/x86/include/asm/elf.h
index 1514753fd435..15340e36ddcb 100644
--- a/arch/x86/include/asm/elf.h
+++ b/arch/x86/include/asm/elf.h
@@ -256,7 +256,7 @@ extern int force_personality32;
instruction set this CPU supports. This could be done in user space,
but it's not easy, and we've already done it here. */
-#define ELF_HWCAP (boot_cpu_data.x86_capability[0])
+#define ELF_HWCAP (boot_cpu_data.x86_capability[CPUID_1_EDX])
/* This yields a string that ld.so will use to load implementation
specific libraries for optimization. This is more specific in
diff --git a/arch/x86/kernel/mpparse.c b/arch/x86/kernel/mpparse.c
index 30ca7607cbbb..97340f2c437c 100644
--- a/arch/x86/kernel/mpparse.c
+++ b/arch/x86/kernel/mpparse.c
@@ -408,7 +408,7 @@ static inline void __init construct_default_ISA_mptable(int mpc_default_type)
processor.cpuflag = CPU_ENABLED;
processor.cpufeature = (boot_cpu_data.x86 << 8) |
(boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_mask;
- processor.featureflag = boot_cpu_data.x86_capability[0];
+ processor.featureflag = boot_cpu_data.x86_capability[CPUID_1_EDX];
processor.reserved[0] = 0;
processor.reserved[1] = 0;
for (i = 0; i < 2; i++) {
diff --git a/arch/x86/lguest/boot.c b/arch/x86/lguest/boot.c
index 4ba229ac3f4f..a9033ae13369 100644
--- a/arch/x86/lguest/boot.c
+++ b/arch/x86/lguest/boot.c
@@ -1535,7 +1535,7 @@ __init void lguest_init(void)
*/
cpu_detect(&new_cpu_data);
/* head.S usually sets up the first capability word, so do it here. */
- new_cpu_data.x86_capability[0] = cpuid_edx(1);
+ new_cpu_data.x86_capability[CPUID_1_EDX] = cpuid_edx(1);
/* Math is always hard! */
set_cpu_cap(&new_cpu_data, X86_FEATURE_FPU);
diff --git a/arch/x86/xen/enlighten.c b/arch/x86/xen/enlighten.c
index d09e4c9d7cc5..2c261082eadf 100644
--- a/arch/x86/xen/enlighten.c
+++ b/arch/x86/xen/enlighten.c
@@ -1654,7 +1654,7 @@ asmlinkage __visible void __init xen_start_kernel(void)
cpu_detect(&new_cpu_data);
set_cpu_cap(&new_cpu_data, X86_FEATURE_FPU);
new_cpu_data.wp_works_ok = 1;
- new_cpu_data.x86_capability[0] = cpuid_edx(1);
+ new_cpu_data.x86_capability[CPUID_1_EDX] = cpuid_edx(1);
#endif
if (xen_start_info->mod_start) {
--
2.3.5
^ permalink raw reply related [flat|nested] 17+ messages in thread* [tip:x86/cpu] x86/cpufeature: Use enum cpuid_leafs instead of magic numbers
2016-01-25 19:41 ` [PATCH 2/8] x86/cpufeature: Use enum cpuid_leafs instead of magic numbers Borislav Petkov
@ 2016-02-01 11:40 ` tip-bot for Huaitong Han
0 siblings, 0 replies; 17+ messages in thread
From: tip-bot for Huaitong Han @ 2016-02-01 11:40 UTC (permalink / raw)
To: linux-tip-commits
Cc: rusty, bp, konrad.wilk, torvalds, boris.ostrovsky, david.vrabel,
bp, jiang.liu, mingo, dvlasenk, akpm, hpa, keescook,
kuleshovmail, luto, linux-kernel, tony.luck, huaitong.han,
hecmargi, brgerst, viresh.kumar, tglx, peterz
Commit-ID: 16aaa53756501914a863ae7a15fcb070dc27c3d7
Gitweb: http://git.kernel.org/tip/16aaa53756501914a863ae7a15fcb070dc27c3d7
Author: Huaitong Han <huaitong.han@intel.com>
AuthorDate: Mon, 25 Jan 2016 20:41:47 +0100
Committer: Ingo Molnar <mingo@kernel.org>
CommitDate: Mon, 1 Feb 2016 10:46:48 +0100
x86/cpufeature: Use enum cpuid_leafs instead of magic numbers
Most of the magic numbers in x86_capability[] have been converted to
'enum cpuid_leafs', and this patch updates the remaining part.
Signed-off-by: Huaitong Han <huaitong.han@intel.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: Alexander Kuleshov <kuleshovmail@gmail.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Brian Gerst <brgerst@gmail.com>
Cc: David Vrabel <david.vrabel@citrix.com>
Cc: Denys Vlasenko <dvlasenk@redhat.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Hector Marco-Gisbert <hecmargi@upv.es>
Cc: Jiang Liu <jiang.liu@linux.intel.com>
Cc: Kees Cook <keescook@chromium.org>
Cc: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Rusty Russell <rusty@rustcorp.com.au>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Tony Luck <tony.luck@intel.com>
Cc: Viresh Kumar <viresh.kumar@linaro.org>
Cc: lguest@lists.ozlabs.org
Cc: xen-devel@lists.xenproject.org
Link: http://lkml.kernel.org/r/1453750913-4781-3-git-send-email-bp@alien8.de
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
arch/x86/include/asm/elf.h | 2 +-
arch/x86/kernel/mpparse.c | 2 +-
arch/x86/lguest/boot.c | 2 +-
arch/x86/xen/enlighten.c | 2 +-
4 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/x86/include/asm/elf.h b/arch/x86/include/asm/elf.h
index 1514753..15340e3 100644
--- a/arch/x86/include/asm/elf.h
+++ b/arch/x86/include/asm/elf.h
@@ -256,7 +256,7 @@ extern int force_personality32;
instruction set this CPU supports. This could be done in user space,
but it's not easy, and we've already done it here. */
-#define ELF_HWCAP (boot_cpu_data.x86_capability[0])
+#define ELF_HWCAP (boot_cpu_data.x86_capability[CPUID_1_EDX])
/* This yields a string that ld.so will use to load implementation
specific libraries for optimization. This is more specific in
diff --git a/arch/x86/kernel/mpparse.c b/arch/x86/kernel/mpparse.c
index 30ca760..97340f2 100644
--- a/arch/x86/kernel/mpparse.c
+++ b/arch/x86/kernel/mpparse.c
@@ -408,7 +408,7 @@ static inline void __init construct_default_ISA_mptable(int mpc_default_type)
processor.cpuflag = CPU_ENABLED;
processor.cpufeature = (boot_cpu_data.x86 << 8) |
(boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_mask;
- processor.featureflag = boot_cpu_data.x86_capability[0];
+ processor.featureflag = boot_cpu_data.x86_capability[CPUID_1_EDX];
processor.reserved[0] = 0;
processor.reserved[1] = 0;
for (i = 0; i < 2; i++) {
diff --git a/arch/x86/lguest/boot.c b/arch/x86/lguest/boot.c
index 4ba229a..a9033ae 100644
--- a/arch/x86/lguest/boot.c
+++ b/arch/x86/lguest/boot.c
@@ -1535,7 +1535,7 @@ __init void lguest_init(void)
*/
cpu_detect(&new_cpu_data);
/* head.S usually sets up the first capability word, so do it here. */
- new_cpu_data.x86_capability[0] = cpuid_edx(1);
+ new_cpu_data.x86_capability[CPUID_1_EDX] = cpuid_edx(1);
/* Math is always hard! */
set_cpu_cap(&new_cpu_data, X86_FEATURE_FPU);
diff --git a/arch/x86/xen/enlighten.c b/arch/x86/xen/enlighten.c
index d09e4c9..2c26108 100644
--- a/arch/x86/xen/enlighten.c
+++ b/arch/x86/xen/enlighten.c
@@ -1654,7 +1654,7 @@ asmlinkage __visible void __init xen_start_kernel(void)
cpu_detect(&new_cpu_data);
set_cpu_cap(&new_cpu_data, X86_FEATURE_FPU);
new_cpu_data.wp_works_ok = 1;
- new_cpu_data.x86_capability[0] = cpuid_edx(1);
+ new_cpu_data.x86_capability[CPUID_1_EDX] = cpuid_edx(1);
#endif
if (xen_start_info->mod_start) {
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 3/8] x86/mce: Fix order of AMD MCE init function call
2016-01-25 19:41 [PATCH 0/8] tip-queue 2016-01-25 Borislav Petkov
2016-01-25 19:41 ` [PATCH 1/8] x86/traps.c: Refactor preemption and interrupt flag handling Borislav Petkov
2016-01-25 19:41 ` [PATCH 2/8] x86/cpufeature: Use enum cpuid_leafs instead of magic numbers Borislav Petkov
@ 2016-01-25 19:41 ` Borislav Petkov
2016-02-01 11:40 ` [tip:ras/core] " tip-bot for Aravind Gopalakrishnan
2016-01-25 19:41 ` [PATCH 4/8] x86/mce/AMD: Do not perform shared bank check for future processors Borislav Petkov
` (4 subsequent siblings)
7 siblings, 1 reply; 17+ messages in thread
From: Borislav Petkov @ 2016-01-25 19:41 UTC (permalink / raw)
To: Ingo Molnar; +Cc: LKML
From: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
In mce_amd_feature_init() we take decisions based on mce_flags being set
or not. So the feature detection using CPUID should naturally be ordered
before we call mce_amd_feature_init().
Fix that here.
Signed-off-by: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
Cc: linux-edac <linux-edac@vger.kernel.org>
Cc: Tony Luck <tony.luck@intel.com>
Cc: x86-ml <x86@kernel.org>
Link: http://lkml.kernel.org/r/1452901836-27632-2-git-send-email-Aravind.Gopalakrishnan@amd.com
Signed-off-by: Borislav Petkov <bp@suse.de>
---
arch/x86/kernel/cpu/mcheck/mce.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index a006f4cd792b..b7180801ea33 100644
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -1617,10 +1617,10 @@ static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
case X86_VENDOR_AMD: {
u32 ebx = cpuid_ebx(0x80000007);
- mce_amd_feature_init(c);
mce_flags.overflow_recov = !!(ebx & BIT(0));
mce_flags.succor = !!(ebx & BIT(1));
mce_flags.smca = !!(ebx & BIT(3));
+ mce_amd_feature_init(c);
break;
}
--
2.3.5
^ permalink raw reply related [flat|nested] 17+ messages in thread* [tip:ras/core] x86/mce: Fix order of AMD MCE init function call
2016-01-25 19:41 ` [PATCH 3/8] x86/mce: Fix order of AMD MCE init function call Borislav Petkov
@ 2016-02-01 11:40 ` tip-bot for Aravind Gopalakrishnan
0 siblings, 0 replies; 17+ messages in thread
From: tip-bot for Aravind Gopalakrishnan @ 2016-02-01 11:40 UTC (permalink / raw)
To: linux-tip-commits
Cc: tglx, Aravind.Gopalakrishnan, linux-edac, bp, linux-kernel,
torvalds, hpa, bp, tony.luck, peterz, mingo
Commit-ID: bfbe0eeb769e2aff2cb1fc6845c4e4b7eac40bb3
Gitweb: http://git.kernel.org/tip/bfbe0eeb769e2aff2cb1fc6845c4e4b7eac40bb3
Author: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
AuthorDate: Mon, 25 Jan 2016 20:41:48 +0100
Committer: Ingo Molnar <mingo@kernel.org>
CommitDate: Mon, 1 Feb 2016 10:53:55 +0100
x86/mce: Fix order of AMD MCE init function call
In mce_amd_feature_init() we take decisions based on mce_flags
being set or not. So the feature detection using CPUID should
naturally be ordered before we call mce_amd_feature_init().
Fix that here.
Signed-off-by: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Tony Luck <tony.luck@intel.com>
Cc: linux-edac <linux-edac@vger.kernel.org>
Link: http://lkml.kernel.org/r/1453750913-4781-4-git-send-email-bp@alien8.de
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
arch/x86/kernel/cpu/mcheck/mce.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index a006f4c..b718080 100644
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -1617,10 +1617,10 @@ static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
case X86_VENDOR_AMD: {
u32 ebx = cpuid_ebx(0x80000007);
- mce_amd_feature_init(c);
mce_flags.overflow_recov = !!(ebx & BIT(0));
mce_flags.succor = !!(ebx & BIT(1));
mce_flags.smca = !!(ebx & BIT(3));
+ mce_amd_feature_init(c);
break;
}
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 4/8] x86/mce/AMD: Do not perform shared bank check for future processors
2016-01-25 19:41 [PATCH 0/8] tip-queue 2016-01-25 Borislav Petkov
` (2 preceding siblings ...)
2016-01-25 19:41 ` [PATCH 3/8] x86/mce: Fix order of AMD MCE init function call Borislav Petkov
@ 2016-01-25 19:41 ` Borislav Petkov
2016-02-01 11:40 ` [tip:ras/core] " tip-bot for Aravind Gopalakrishnan
2016-01-25 19:41 ` [PATCH 5/8] x86/mce/AMD: Reduce number of blocks scanned per bank Borislav Petkov
` (3 subsequent siblings)
7 siblings, 1 reply; 17+ messages in thread
From: Borislav Petkov @ 2016-01-25 19:41 UTC (permalink / raw)
To: Ingo Molnar; +Cc: LKML
From: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
Fam17h and above should not require a check to see if a bank is shared
or not. For shared banks, there will always be only one core that has
visibility over the MSRs and only that particular core will be allowed
to write to the MSRs.
Fix the code to return early if we have Scalable MCA support. No change
in functionality for earlier processors.
Boris: Fold in fix from kbuild test robot for:
arch/x86/kernel/cpu/mcheck/mce_amd.c:93:9-10: WARNING: return of 0/1 in function 'is_shared_bank' with return type bool
Generated by: scripts/coccinelle/misc/boolreturn.cocci
Signed-off-by: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
Cc: linux-edac <linux-edac@vger.kernel.org>
Cc: Tony Luck <tony.luck@intel.com>
Cc: x86-ml <x86@kernel.org>
Link: http://lkml.kernel.org/r/1452901836-27632-3-git-send-email-Aravind.Gopalakrishnan@amd.com
Signed-off-by: Fengguang Wu <fengguang.wu@intel.com>
[ Boris: massage text. ]
Signed-off-by: Borislav Petkov <bp@suse.de>
---
arch/x86/kernel/cpu/mcheck/mce_amd.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c
index e99b15077e94..3068ce25dfa1 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_amd.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c
@@ -84,6 +84,13 @@ struct thresh_restart {
static inline bool is_shared_bank(int bank)
{
+ /*
+ * Scalable MCA provides for only one core to have access to the MSRs of
+ * a shared bank.
+ */
+ if (mce_flags.smca)
+ return false;
+
/* Bank 4 is for northbridge reporting and is thus shared */
return (bank == 4);
}
--
2.3.5
^ permalink raw reply related [flat|nested] 17+ messages in thread* [tip:ras/core] x86/mce/AMD: Do not perform shared bank check for future processors
2016-01-25 19:41 ` [PATCH 4/8] x86/mce/AMD: Do not perform shared bank check for future processors Borislav Petkov
@ 2016-02-01 11:40 ` tip-bot for Aravind Gopalakrishnan
0 siblings, 0 replies; 17+ messages in thread
From: tip-bot for Aravind Gopalakrishnan @ 2016-02-01 11:40 UTC (permalink / raw)
To: linux-tip-commits
Cc: linux-edac, linux-kernel, mingo, bp, peterz, tglx, torvalds,
Aravind.Gopalakrishnan, bp, tony.luck, hpa, fengguang.wu
Commit-ID: 284b965c146f482b4a411133f62288d52b7e3a72
Gitweb: http://git.kernel.org/tip/284b965c146f482b4a411133f62288d52b7e3a72
Author: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
AuthorDate: Mon, 25 Jan 2016 20:41:49 +0100
Committer: Ingo Molnar <mingo@kernel.org>
CommitDate: Mon, 1 Feb 2016 10:53:56 +0100
x86/mce/AMD: Do not perform shared bank check for future processors
Fam17h and above should not require a check to see if a bank is
shared or not. For shared banks, there will always be only one
core that has visibility over the MSRs and only that particular
core will be allowed to write to the MSRs.
Fix the code to return early if we have Scalable MCA support. No
change in functionality for earlier processors.
Signed-off-by: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
Signed-off-by: Fengguang Wu <fengguang.wu@intel.com>
[ Massaged the changelog text, fixed kbuild test robot build warning. ]
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Tony Luck <tony.luck@intel.com>
Cc: linux-edac <linux-edac@vger.kernel.org>
Link: http://lkml.kernel.org/r/1453750913-4781-5-git-send-email-bp@alien8.de
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
arch/x86/kernel/cpu/mcheck/mce_amd.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c
index e99b150..3068ce2 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_amd.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c
@@ -84,6 +84,13 @@ struct thresh_restart {
static inline bool is_shared_bank(int bank)
{
+ /*
+ * Scalable MCA provides for only one core to have access to the MSRs of
+ * a shared bank.
+ */
+ if (mce_flags.smca)
+ return false;
+
/* Bank 4 is for northbridge reporting and is thus shared */
return (bank == 4);
}
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 5/8] x86/mce/AMD: Reduce number of blocks scanned per bank
2016-01-25 19:41 [PATCH 0/8] tip-queue 2016-01-25 Borislav Petkov
` (3 preceding siblings ...)
2016-01-25 19:41 ` [PATCH 4/8] x86/mce/AMD: Do not perform shared bank check for future processors Borislav Petkov
@ 2016-01-25 19:41 ` Borislav Petkov
2016-02-01 11:41 ` [tip:ras/core] " tip-bot for Aravind Gopalakrishnan
2016-01-25 19:41 ` [PATCH 6/8] x86/mce/AMD: Fix LVT offset configuration for thresholding Borislav Petkov
` (2 subsequent siblings)
7 siblings, 1 reply; 17+ messages in thread
From: Borislav Petkov @ 2016-01-25 19:41 UTC (permalink / raw)
To: Ingo Molnar; +Cc: LKML
From: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
>From Fam17h onwards, the number of extended MCx_MISC register blocks is
reduced to 4. It is an architectural change from what we had on earlier
processors.
Although theoritically the total number of extended MCx_MISC registers
was 8 in earlier processor families, in practice we only had to use the
extra registers for MC4. And only 2 of those were used. So this change
does not affect older processors. Tested on Fam10h and Fam15h systems.
Signed-off-by: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
Cc: linux-edac <linux-edac@vger.kernel.org>
Cc: Tony Luck <tony.luck@intel.com>
Cc: x86-ml <x86@kernel.org>
Link: http://lkml.kernel.org/r/1452901836-27632-4-git-send-email-Aravind.Gopalakrishnan@amd.com
Signed-off-by: Borislav Petkov <bp@suse.de>
---
arch/x86/kernel/cpu/mcheck/mce_amd.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c
index 3068ce25dfa1..5982227990c9 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_amd.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c
@@ -28,7 +28,7 @@
#include <asm/msr.h>
#include <asm/trace/irq_vectors.h>
-#define NR_BLOCKS 9
+#define NR_BLOCKS 5
#define THRESHOLD_MAX 0xFFF
#define INT_TYPE_APIC 0x00020000
#define MASK_VALID_HI 0x80000000
--
2.3.5
^ permalink raw reply related [flat|nested] 17+ messages in thread* [tip:ras/core] x86/mce/AMD: Reduce number of blocks scanned per bank
2016-01-25 19:41 ` [PATCH 5/8] x86/mce/AMD: Reduce number of blocks scanned per bank Borislav Petkov
@ 2016-02-01 11:41 ` tip-bot for Aravind Gopalakrishnan
0 siblings, 0 replies; 17+ messages in thread
From: tip-bot for Aravind Gopalakrishnan @ 2016-02-01 11:41 UTC (permalink / raw)
To: linux-tip-commits
Cc: tony.luck, mingo, linux-kernel, tglx, linux-edac, peterz, bp,
Aravind.Gopalakrishnan, hpa, torvalds, bp
Commit-ID: 60f116fca162d9488f783f5014779463243ab7a2
Gitweb: http://git.kernel.org/tip/60f116fca162d9488f783f5014779463243ab7a2
Author: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
AuthorDate: Mon, 25 Jan 2016 20:41:50 +0100
Committer: Ingo Molnar <mingo@kernel.org>
CommitDate: Mon, 1 Feb 2016 10:53:57 +0100
x86/mce/AMD: Reduce number of blocks scanned per bank
>From Fam17h onwards, the number of extended MCx_MISC register blocks is
reduced to 4. It is an architectural change from what we had on
earlier processors.
Although theoritically the total number of extended MCx_MISC
registers was 8 in earlier processor families, in practice we
only had to use the extra registers for MC4. And only 2 of those
were used. So this change does not affect older processors.
Tested on Fam10h and Fam15h systems.
Signed-off-by: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Tony Luck <tony.luck@intel.com>
Cc: linux-edac <linux-edac@vger.kernel.org>
Link: http://lkml.kernel.org/r/1453750913-4781-6-git-send-email-bp@alien8.de
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
arch/x86/kernel/cpu/mcheck/mce_amd.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c
index 3068ce2..5982227 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_amd.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c
@@ -28,7 +28,7 @@
#include <asm/msr.h>
#include <asm/trace/irq_vectors.h>
-#define NR_BLOCKS 9
+#define NR_BLOCKS 5
#define THRESHOLD_MAX 0xFFF
#define INT_TYPE_APIC 0x00020000
#define MASK_VALID_HI 0x80000000
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 6/8] x86/mce/AMD: Fix LVT offset configuration for thresholding
2016-01-25 19:41 [PATCH 0/8] tip-queue 2016-01-25 Borislav Petkov
` (4 preceding siblings ...)
2016-01-25 19:41 ` [PATCH 5/8] x86/mce/AMD: Reduce number of blocks scanned per bank Borislav Petkov
@ 2016-01-25 19:41 ` Borislav Petkov
2016-02-01 11:41 ` [tip:ras/core] " tip-bot for Aravind Gopalakrishnan
2016-01-25 19:41 ` [PATCH 7/8] x86/mce/AMD: Carve out threshold block preparation Borislav Petkov
2016-01-25 19:41 ` [PATCH 8/8] x86/mce/AMD: Set MCAX Enable bit Borislav Petkov
7 siblings, 1 reply; 17+ messages in thread
From: Borislav Petkov @ 2016-01-25 19:41 UTC (permalink / raw)
To: Ingo Molnar; +Cc: LKML
From: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
For processor families with the Scalable MCA feature, the LVT offset for
threshold interrupts is configured only in MSR 0xC0000410 and not in
each per bank MISC register as was done in earlier families.
Obtain the LVT offset from the correct MSR for those families.
Signed-off-by: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
Cc: linux-edac <linux-edac@vger.kernel.org>
Cc: Tony Luck <tony.luck@intel.com>
Cc: x86-ml <x86@kernel.org>
Link: http://lkml.kernel.org/r/1452901836-27632-5-git-send-email-Aravind.Gopalakrishnan@amd.com
Signed-off-by: Borislav Petkov <bp@suse.de>
---
arch/x86/kernel/cpu/mcheck/mce_amd.c | 27 ++++++++++++++++++++++++++-
1 file changed, 26 insertions(+), 1 deletion(-)
diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c
index 5982227990c9..35ca4ec7fc65 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_amd.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c
@@ -49,6 +49,11 @@
#define DEF_LVT_OFF 0x2
#define DEF_INT_TYPE_APIC 0x2
+/* Scalable MCA: */
+
+/* Threshold LVT offset is at MSR0xC0000410[15:12] */
+#define SMCA_THR_LVT_OFF 0xF000
+
static const char * const th_names[] = {
"load_store",
"insn_fetch",
@@ -142,6 +147,14 @@ static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi)
}
if (apic != msr) {
+ /*
+ * On SMCA CPUs, LVT offset is programmed at different MSR and
+ * BIOS provides the value. The original field where LVT offset
+ * was set is Reserved. Return early here.
+ */
+ if (mce_flags.smca)
+ return 0;
+
pr_err(FW_BUG "cpu %d, invalid threshold interrupt offset %d "
"for bank %d, block %d (MSR%08X=0x%x%08x)\n",
b->cpu, apic, b->bank, b->block, b->address, hi, lo);
@@ -300,7 +313,19 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c)
goto init;
b.interrupt_enable = 1;
- new = (high & MASK_LVTOFF_HI) >> 20;
+
+ if (mce_flags.smca) {
+ u32 smca_low, smca_high;
+
+ /* Gather LVT offset for thresholding */
+ if (rdmsr_safe(MSR_CU_DEF_ERR, &smca_low, &smca_high))
+ break;
+
+ new = (smca_low & SMCA_THR_LVT_OFF) >> 12;
+ } else {
+ new = (high & MASK_LVTOFF_HI) >> 20;
+ }
+
offset = setup_APIC_mce_threshold(offset, new);
if ((offset == new) &&
--
2.3.5
^ permalink raw reply related [flat|nested] 17+ messages in thread* [tip:ras/core] x86/mce/AMD: Fix LVT offset configuration for thresholding
2016-01-25 19:41 ` [PATCH 6/8] x86/mce/AMD: Fix LVT offset configuration for thresholding Borislav Petkov
@ 2016-02-01 11:41 ` tip-bot for Aravind Gopalakrishnan
0 siblings, 0 replies; 17+ messages in thread
From: tip-bot for Aravind Gopalakrishnan @ 2016-02-01 11:41 UTC (permalink / raw)
To: linux-tip-commits
Cc: linux-kernel, bp, peterz, torvalds, linux-edac, tony.luck, bp,
mingo, Aravind.Gopalakrishnan, tglx, hpa
Commit-ID: f57a1f3c14b9182f1fea667f5a38a1094699db7c
Gitweb: http://git.kernel.org/tip/f57a1f3c14b9182f1fea667f5a38a1094699db7c
Author: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
AuthorDate: Mon, 25 Jan 2016 20:41:51 +0100
Committer: Ingo Molnar <mingo@kernel.org>
CommitDate: Mon, 1 Feb 2016 10:53:57 +0100
x86/mce/AMD: Fix LVT offset configuration for thresholding
For processor families with the Scalable MCA feature, the LVT
offset for threshold interrupts is configured only in MSR
0xC0000410 and not in each per bank MISC register as was done in
earlier families.
Obtain the LVT offset from the correct MSR for those families.
Signed-off-by: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Tony Luck <tony.luck@intel.com>
Cc: linux-edac <linux-edac@vger.kernel.org>
Link: http://lkml.kernel.org/r/1453750913-4781-7-git-send-email-bp@alien8.de
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
arch/x86/kernel/cpu/mcheck/mce_amd.c | 27 ++++++++++++++++++++++++++-
1 file changed, 26 insertions(+), 1 deletion(-)
diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c
index 5982227..a77a452 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_amd.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c
@@ -49,6 +49,11 @@
#define DEF_LVT_OFF 0x2
#define DEF_INT_TYPE_APIC 0x2
+/* Scalable MCA: */
+
+/* Threshold LVT offset is at MSR0xC0000410[15:12] */
+#define SMCA_THR_LVT_OFF 0xF000
+
static const char * const th_names[] = {
"load_store",
"insn_fetch",
@@ -142,6 +147,14 @@ static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi)
}
if (apic != msr) {
+ /*
+ * On SMCA CPUs, LVT offset is programmed at a different MSR, and
+ * the BIOS provides the value. The original field where LVT offset
+ * was set is reserved. Return early here:
+ */
+ if (mce_flags.smca)
+ return 0;
+
pr_err(FW_BUG "cpu %d, invalid threshold interrupt offset %d "
"for bank %d, block %d (MSR%08X=0x%x%08x)\n",
b->cpu, apic, b->bank, b->block, b->address, hi, lo);
@@ -300,7 +313,19 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c)
goto init;
b.interrupt_enable = 1;
- new = (high & MASK_LVTOFF_HI) >> 20;
+
+ if (mce_flags.smca) {
+ u32 smca_low, smca_high;
+
+ /* Gather LVT offset for thresholding: */
+ if (rdmsr_safe(MSR_CU_DEF_ERR, &smca_low, &smca_high))
+ break;
+
+ new = (smca_low & SMCA_THR_LVT_OFF) >> 12;
+ } else {
+ new = (high & MASK_LVTOFF_HI) >> 20;
+ }
+
offset = setup_APIC_mce_threshold(offset, new);
if ((offset == new) &&
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 7/8] x86/mce/AMD: Carve out threshold block preparation
2016-01-25 19:41 [PATCH 0/8] tip-queue 2016-01-25 Borislav Petkov
` (5 preceding siblings ...)
2016-01-25 19:41 ` [PATCH 6/8] x86/mce/AMD: Fix LVT offset configuration for thresholding Borislav Petkov
@ 2016-01-25 19:41 ` Borislav Petkov
2016-02-01 11:41 ` [tip:ras/core] " tip-bot for Borislav Petkov
2016-01-25 19:41 ` [PATCH 8/8] x86/mce/AMD: Set MCAX Enable bit Borislav Petkov
7 siblings, 1 reply; 17+ messages in thread
From: Borislav Petkov @ 2016-01-25 19:41 UTC (permalink / raw)
To: Ingo Molnar; +Cc: LKML
From: Borislav Petkov <bp@suse.de>
mce_amd_feature_init() was getting pretty fat, carve out the
threshold_block setup into a separate function in order to simplify flow
and make it more understandable.
No functionality change.
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
---
arch/x86/kernel/cpu/mcheck/mce_amd.c | 88 ++++++++++++++++++++----------------
1 file changed, 50 insertions(+), 38 deletions(-)
diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c
index 35ca4ec7fc65..e5ac583ae915 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_amd.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c
@@ -267,14 +267,60 @@ static void deferred_error_interrupt_enable(struct cpuinfo_x86 *c)
wrmsr(MSR_CU_DEF_ERR, low, high);
}
+static int
+prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr,
+ int offset, u32 misc_high)
+{
+ unsigned int cpu = smp_processor_id();
+ struct threshold_block b;
+ int new;
+
+ if (!block)
+ per_cpu(bank_map, cpu) |= (1 << bank);
+
+ memset(&b, 0, sizeof(b));
+ b.cpu = cpu;
+ b.bank = bank;
+ b.block = block;
+ b.address = addr;
+ b.interrupt_capable = lvt_interrupt_supported(bank, misc_high);
+
+ if (!b.interrupt_capable)
+ goto done;
+
+ b.interrupt_enable = 1;
+
+ if (mce_flags.smca) {
+ u32 smca_low, smca_high;
+
+ /* Gather LVT offset for thresholding */
+ if (rdmsr_safe(MSR_CU_DEF_ERR, &smca_low, &smca_high))
+ goto out;
+
+ new = (smca_low & SMCA_THR_LVT_OFF) >> 12;
+ } else {
+ new = (misc_high & MASK_LVTOFF_HI) >> 20;
+ }
+
+ offset = setup_APIC_mce_threshold(offset, new);
+
+ if ((offset == new) &&
+ (mce_threshold_vector != amd_threshold_interrupt))
+ mce_threshold_vector = amd_threshold_interrupt;
+
+done:
+ mce_threshold_block_init(&b, offset);
+
+out:
+ return offset;
+}
+
/* cpu init entry point, called from mce.c with preempt off */
void mce_amd_feature_init(struct cpuinfo_x86 *c)
{
- struct threshold_block b;
- unsigned int cpu = smp_processor_id();
u32 low = 0, high = 0, address = 0;
unsigned int bank, block;
- int offset = -1, new;
+ int offset = -1;
for (bank = 0; bank < mca_cfg.banks; ++bank) {
for (block = 0; block < NR_BLOCKS; ++block) {
@@ -299,41 +345,7 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c)
(high & MASK_LOCKED_HI))
continue;
- if (!block)
- per_cpu(bank_map, cpu) |= (1 << bank);
-
- memset(&b, 0, sizeof(b));
- b.cpu = cpu;
- b.bank = bank;
- b.block = block;
- b.address = address;
- b.interrupt_capable = lvt_interrupt_supported(bank, high);
-
- if (!b.interrupt_capable)
- goto init;
-
- b.interrupt_enable = 1;
-
- if (mce_flags.smca) {
- u32 smca_low, smca_high;
-
- /* Gather LVT offset for thresholding */
- if (rdmsr_safe(MSR_CU_DEF_ERR, &smca_low, &smca_high))
- break;
-
- new = (smca_low & SMCA_THR_LVT_OFF) >> 12;
- } else {
- new = (high & MASK_LVTOFF_HI) >> 20;
- }
-
- offset = setup_APIC_mce_threshold(offset, new);
-
- if ((offset == new) &&
- (mce_threshold_vector != amd_threshold_interrupt))
- mce_threshold_vector = amd_threshold_interrupt;
-
-init:
- mce_threshold_block_init(&b, offset);
+ offset = prepare_threshold_block(bank, block, address, offset, high);
}
}
--
2.3.5
^ permalink raw reply related [flat|nested] 17+ messages in thread* [tip:ras/core] x86/mce/AMD: Carve out threshold block preparation
2016-01-25 19:41 ` [PATCH 7/8] x86/mce/AMD: Carve out threshold block preparation Borislav Petkov
@ 2016-02-01 11:41 ` tip-bot for Borislav Petkov
0 siblings, 0 replies; 17+ messages in thread
From: tip-bot for Borislav Petkov @ 2016-02-01 11:41 UTC (permalink / raw)
To: linux-tip-commits
Cc: bp, hpa, tony.luck, linux-kernel, torvalds, mingo,
Aravind.Gopalakrishnan, peterz, bp, tglx
Commit-ID: 429893b16d35d309ed6b35136aad5f908a08d9b9
Gitweb: http://git.kernel.org/tip/429893b16d35d309ed6b35136aad5f908a08d9b9
Author: Borislav Petkov <bp@suse.de>
AuthorDate: Mon, 25 Jan 2016 20:41:52 +0100
Committer: Ingo Molnar <mingo@kernel.org>
CommitDate: Mon, 1 Feb 2016 10:53:58 +0100
x86/mce/AMD: Carve out threshold block preparation
mce_amd_feature_init() was getting pretty fat, carve out the
threshold_block setup into a separate function in order to
simplify flow and make it more understandable.
No functionality change.
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Tony Luck <tony.luck@intel.com>
Link: http://lkml.kernel.org/r/1453750913-4781-8-git-send-email-bp@alien8.de
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
arch/x86/kernel/cpu/mcheck/mce_amd.c | 87 ++++++++++++++++++++----------------
1 file changed, 49 insertions(+), 38 deletions(-)
diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c
index a77a452..f2860a1 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_amd.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c
@@ -267,14 +267,59 @@ static void deferred_error_interrupt_enable(struct cpuinfo_x86 *c)
wrmsr(MSR_CU_DEF_ERR, low, high);
}
+static int
+prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr,
+ int offset, u32 misc_high)
+{
+ unsigned int cpu = smp_processor_id();
+ struct threshold_block b;
+ int new;
+
+ if (!block)
+ per_cpu(bank_map, cpu) |= (1 << bank);
+
+ memset(&b, 0, sizeof(b));
+ b.cpu = cpu;
+ b.bank = bank;
+ b.block = block;
+ b.address = addr;
+ b.interrupt_capable = lvt_interrupt_supported(bank, misc_high);
+
+ if (!b.interrupt_capable)
+ goto done;
+
+ b.interrupt_enable = 1;
+
+ if (mce_flags.smca) {
+ u32 smca_low, smca_high;
+
+ /* Gather LVT offset for thresholding: */
+ if (rdmsr_safe(MSR_CU_DEF_ERR, &smca_low, &smca_high))
+ goto out;
+
+ new = (smca_low & SMCA_THR_LVT_OFF) >> 12;
+ } else {
+ new = (misc_high & MASK_LVTOFF_HI) >> 20;
+ }
+
+ offset = setup_APIC_mce_threshold(offset, new);
+
+ if ((offset == new) && (mce_threshold_vector != amd_threshold_interrupt))
+ mce_threshold_vector = amd_threshold_interrupt;
+
+done:
+ mce_threshold_block_init(&b, offset);
+
+out:
+ return offset;
+}
+
/* cpu init entry point, called from mce.c with preempt off */
void mce_amd_feature_init(struct cpuinfo_x86 *c)
{
- struct threshold_block b;
- unsigned int cpu = smp_processor_id();
u32 low = 0, high = 0, address = 0;
unsigned int bank, block;
- int offset = -1, new;
+ int offset = -1;
for (bank = 0; bank < mca_cfg.banks; ++bank) {
for (block = 0; block < NR_BLOCKS; ++block) {
@@ -299,41 +344,7 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c)
(high & MASK_LOCKED_HI))
continue;
- if (!block)
- per_cpu(bank_map, cpu) |= (1 << bank);
-
- memset(&b, 0, sizeof(b));
- b.cpu = cpu;
- b.bank = bank;
- b.block = block;
- b.address = address;
- b.interrupt_capable = lvt_interrupt_supported(bank, high);
-
- if (!b.interrupt_capable)
- goto init;
-
- b.interrupt_enable = 1;
-
- if (mce_flags.smca) {
- u32 smca_low, smca_high;
-
- /* Gather LVT offset for thresholding: */
- if (rdmsr_safe(MSR_CU_DEF_ERR, &smca_low, &smca_high))
- break;
-
- new = (smca_low & SMCA_THR_LVT_OFF) >> 12;
- } else {
- new = (high & MASK_LVTOFF_HI) >> 20;
- }
-
- offset = setup_APIC_mce_threshold(offset, new);
-
- if ((offset == new) &&
- (mce_threshold_vector != amd_threshold_interrupt))
- mce_threshold_vector = amd_threshold_interrupt;
-
-init:
- mce_threshold_block_init(&b, offset);
+ offset = prepare_threshold_block(bank, block, address, offset, high);
}
}
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 8/8] x86/mce/AMD: Set MCAX Enable bit
2016-01-25 19:41 [PATCH 0/8] tip-queue 2016-01-25 Borislav Petkov
` (6 preceding siblings ...)
2016-01-25 19:41 ` [PATCH 7/8] x86/mce/AMD: Carve out threshold block preparation Borislav Petkov
@ 2016-01-25 19:41 ` Borislav Petkov
2016-02-01 11:42 ` [tip:ras/core] " tip-bot for Aravind Gopalakrishnan
7 siblings, 1 reply; 17+ messages in thread
From: Borislav Petkov @ 2016-01-25 19:41 UTC (permalink / raw)
To: Ingo Molnar; +Cc: LKML
From: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
It is required for the OS to acknowledge that it is using the MCAX
register set and its associated fields by setting the 'McaXEnable' bit
in each bank's MCi_CONFIG register. If it is not set, then all UC errors
will cause a system panic.
Signed-off-by: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
Cc: linux-edac <linux-edac@vger.kernel.org>
Cc: Tony Luck <tony.luck@intel.com>
Cc: x86-ml <x86@kernel.org>
Link: http://lkml.kernel.org/r/1452901836-27632-6-git-send-email-Aravind.Gopalakrishnan@amd.com
Signed-off-by: Borislav Petkov <bp@suse.de>
---
arch/x86/include/asm/msr-index.h | 4 ++++
arch/x86/kernel/cpu/mcheck/mce_amd.c | 14 ++++++++++++++
2 files changed, 18 insertions(+)
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index b05402ef3b84..5b1aa4c05c4f 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -264,6 +264,10 @@
#define MSR_IA32_MC0_CTL2 0x00000280
#define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x))
+/* AMD64 Scalable MCA */
+#define MSR_AMD64_SMCA_MC0_CONFIG 0xc0002004
+#define MSR_AMD64_SMCA_MCx_CONFIG(x) (MSR_AMD64_SMCA_MC0_CONFIG + 0x10*(x))
+
#define MSR_P6_PERFCTR0 0x000000c1
#define MSR_P6_PERFCTR1 0x000000c2
#define MSR_P6_EVNTSEL0 0x00000186
diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c
index e5ac583ae915..e1f05e8854d1 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_amd.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c
@@ -54,6 +54,14 @@
/* Threshold LVT offset is at MSR0xC0000410[15:12] */
#define SMCA_THR_LVT_OFF 0xF000
+/*
+ * OS is required to set the MCAX bit to acknowledge that it is now using the
+ * new MSR ranges and new registers under each bank. It also means that OS will
+ * configure Deferred errors in the new MCx_CONFIG register. If the bit is not
+ * set, uncorrectable errors will cause system panic.
+ */
+#define SMCA_MCAX_EN_OFF 0x1
+
static const char * const th_names[] = {
"load_store",
"insn_fetch",
@@ -292,6 +300,12 @@ prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr,
if (mce_flags.smca) {
u32 smca_low, smca_high;
+ u32 smca_addr = MSR_AMD64_SMCA_MCx_CONFIG(bank);
+
+ if (!rdmsr_safe(smca_addr, &smca_low, &smca_high)) {
+ smca_high |= SMCA_MCAX_EN_OFF;
+ wrmsr(smca_addr, smca_low, smca_high);
+ }
/* Gather LVT offset for thresholding */
if (rdmsr_safe(MSR_CU_DEF_ERR, &smca_low, &smca_high))
--
2.3.5
^ permalink raw reply related [flat|nested] 17+ messages in thread* [tip:ras/core] x86/mce/AMD: Set MCAX Enable bit
2016-01-25 19:41 ` [PATCH 8/8] x86/mce/AMD: Set MCAX Enable bit Borislav Petkov
@ 2016-02-01 11:42 ` tip-bot for Aravind Gopalakrishnan
0 siblings, 0 replies; 17+ messages in thread
From: tip-bot for Aravind Gopalakrishnan @ 2016-02-01 11:42 UTC (permalink / raw)
To: linux-tip-commits
Cc: hpa, linux-edac, torvalds, bp, linux-kernel, bp, peterz, tglx,
Aravind.Gopalakrishnan, tony.luck, mingo
Commit-ID: e6c8f1873be8a14c7e44202df1f7e6ea61bf3352
Gitweb: http://git.kernel.org/tip/e6c8f1873be8a14c7e44202df1f7e6ea61bf3352
Author: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
AuthorDate: Mon, 25 Jan 2016 20:41:53 +0100
Committer: Ingo Molnar <mingo@kernel.org>
CommitDate: Mon, 1 Feb 2016 10:53:59 +0100
x86/mce/AMD: Set MCAX Enable bit
It is required for the OS to acknowledge that it is using the
MCAX register set and its associated fields by setting the
'McaXEnable' bit in each bank's MCi_CONFIG register. If it is
not set, then all UC errors will cause a system panic.
Signed-off-by: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Tony Luck <tony.luck@intel.com>
Cc: linux-edac <linux-edac@vger.kernel.org>
Link: http://lkml.kernel.org/r/1453750913-4781-9-git-send-email-bp@alien8.de
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
arch/x86/include/asm/msr-index.h | 4 ++++
arch/x86/kernel/cpu/mcheck/mce_amd.c | 14 ++++++++++++++
2 files changed, 18 insertions(+)
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index b05402e..5523465 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -264,6 +264,10 @@
#define MSR_IA32_MC0_CTL2 0x00000280
#define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x))
+/* 'SMCA': AMD64 Scalable MCA */
+#define MSR_AMD64_SMCA_MC0_CONFIG 0xc0002004
+#define MSR_AMD64_SMCA_MCx_CONFIG(x) (MSR_AMD64_SMCA_MC0_CONFIG + 0x10*(x))
+
#define MSR_P6_PERFCTR0 0x000000c1
#define MSR_P6_PERFCTR1 0x000000c2
#define MSR_P6_EVNTSEL0 0x00000186
diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c
index f2860a1..88de27b 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_amd.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c
@@ -54,6 +54,14 @@
/* Threshold LVT offset is at MSR0xC0000410[15:12] */
#define SMCA_THR_LVT_OFF 0xF000
+/*
+ * OS is required to set the MCAX bit to acknowledge that it is now using the
+ * new MSR ranges and new registers under each bank. It also means that the OS
+ * will configure deferred errors in the new MCx_CONFIG register. If the bit is
+ * not set, uncorrectable errors will cause a system panic.
+ */
+#define SMCA_MCAX_EN_OFF 0x1
+
static const char * const th_names[] = {
"load_store",
"insn_fetch",
@@ -292,6 +300,12 @@ prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr,
if (mce_flags.smca) {
u32 smca_low, smca_high;
+ u32 smca_addr = MSR_AMD64_SMCA_MCx_CONFIG(bank);
+
+ if (!rdmsr_safe(smca_addr, &smca_low, &smca_high)) {
+ smca_high |= SMCA_MCAX_EN_OFF;
+ wrmsr(smca_addr, smca_low, smca_high);
+ }
/* Gather LVT offset for thresholding: */
if (rdmsr_safe(MSR_CU_DEF_ERR, &smca_low, &smca_high))
^ permalink raw reply related [flat|nested] 17+ messages in thread