From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933992AbcAYTmU (ORCPT ); Mon, 25 Jan 2016 14:42:20 -0500 Received: from mail.skyhub.de ([78.46.96.112]:33192 "EHLO mail.skyhub.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933784AbcAYTl5 (ORCPT ); Mon, 25 Jan 2016 14:41:57 -0500 From: Borislav Petkov To: Ingo Molnar Cc: LKML Subject: [PATCH 6/8] x86/mce/AMD: Fix LVT offset configuration for thresholding Date: Mon, 25 Jan 2016 20:41:51 +0100 Message-Id: <1453750913-4781-7-git-send-email-bp@alien8.de> X-Mailer: git-send-email 2.3.5 In-Reply-To: <1453750913-4781-1-git-send-email-bp@alien8.de> References: <1453750913-4781-1-git-send-email-bp@alien8.de> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Aravind Gopalakrishnan For processor families with the Scalable MCA feature, the LVT offset for threshold interrupts is configured only in MSR 0xC0000410 and not in each per bank MISC register as was done in earlier families. Obtain the LVT offset from the correct MSR for those families. Signed-off-by: Aravind Gopalakrishnan Cc: linux-edac Cc: Tony Luck Cc: x86-ml Link: http://lkml.kernel.org/r/1452901836-27632-5-git-send-email-Aravind.Gopalakrishnan@amd.com Signed-off-by: Borislav Petkov --- arch/x86/kernel/cpu/mcheck/mce_amd.c | 27 ++++++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c index 5982227990c9..35ca4ec7fc65 100644 --- a/arch/x86/kernel/cpu/mcheck/mce_amd.c +++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c @@ -49,6 +49,11 @@ #define DEF_LVT_OFF 0x2 #define DEF_INT_TYPE_APIC 0x2 +/* Scalable MCA: */ + +/* Threshold LVT offset is at MSR0xC0000410[15:12] */ +#define SMCA_THR_LVT_OFF 0xF000 + static const char * const th_names[] = { "load_store", "insn_fetch", @@ -142,6 +147,14 @@ static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi) } if (apic != msr) { + /* + * On SMCA CPUs, LVT offset is programmed at different MSR and + * BIOS provides the value. The original field where LVT offset + * was set is Reserved. Return early here. + */ + if (mce_flags.smca) + return 0; + pr_err(FW_BUG "cpu %d, invalid threshold interrupt offset %d " "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu, apic, b->bank, b->block, b->address, hi, lo); @@ -300,7 +313,19 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c) goto init; b.interrupt_enable = 1; - new = (high & MASK_LVTOFF_HI) >> 20; + + if (mce_flags.smca) { + u32 smca_low, smca_high; + + /* Gather LVT offset for thresholding */ + if (rdmsr_safe(MSR_CU_DEF_ERR, &smca_low, &smca_high)) + break; + + new = (smca_low & SMCA_THR_LVT_OFF) >> 12; + } else { + new = (high & MASK_LVTOFF_HI) >> 20; + } + offset = setup_APIC_mce_threshold(offset, new); if ((offset == new) && -- 2.3.5