From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx2.suse.de ([195.135.220.15]:60027 "EHLO mx2.suse.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S967186AbcA1Kwd (ORCPT ); Thu, 28 Jan 2016 05:52:33 -0500 From: Jiri Slaby To: stable@vger.kernel.org Cc: Paul Bolle , Roland Dreier , Jiri Slaby Subject: [patch added to 3.12-stable] RDMA/cxgb4: Fix gcc warning on 32-bit arch Date: Thu, 28 Jan 2016 11:51:57 +0100 Message-Id: <1453978346-20237-6-git-send-email-jslaby@suse.cz> In-Reply-To: <1453978346-20237-1-git-send-email-jslaby@suse.cz> References: <1453978346-20237-1-git-send-email-jslaby@suse.cz> Sender: stable-owner@vger.kernel.org List-ID: From: Paul Bolle This patch has been added to the 3.12 stable tree. If you have any objections, please let us know. =============== commit 298589b1cb626adf4beba6dd8e3cd4b64e8799be upstream. Building mem.o for 32 bits x86 triggers a GCC warning: drivers/infiniband/hw/cxgb4/mem.c: In function '_c4iw_write_mem_dma_aligned': drivers/infiniband/hw/cxgb4/mem.c:79:25: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] Silence that warning by casting "&wr_wait" to unsigned long before casting it to __be64. That's what _c4iw_write_mem_inline() already does. Signed-off-by: Paul Bolle Acked-by: Steve Wise Signed-off-by: Roland Dreier Signed-off-by: Jiri Slaby --- drivers/infiniband/hw/cxgb4/mem.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/infiniband/hw/cxgb4/mem.c b/drivers/infiniband/hw/cxgb4/mem.c index 4cb8eb24497c..a80503b3795c 100644 --- a/drivers/infiniband/hw/cxgb4/mem.c +++ b/drivers/infiniband/hw/cxgb4/mem.c @@ -76,7 +76,7 @@ static int _c4iw_write_mem_dma_aligned(struct c4iw_rdev *rdev, u32 addr, INIT_ULPTX_WR(req, wr_len, 0, 0); req->wr.wr_hi = cpu_to_be32(FW_WR_OP(FW_ULPTX_WR) | (wait ? FW_WR_COMPL(1) : 0)); - req->wr.wr_lo = wait ? (__force __be64)&wr_wait : 0; + req->wr.wr_lo = wait ? (__force __be64)(unsigned long) &wr_wait : 0L; req->wr.wr_mid = cpu_to_be32(FW_WR_LEN16(DIV_ROUND_UP(wr_len, 16))); req->cmd = cpu_to_be32(ULPTX_CMD(ULP_TX_MEM_WRITE)); req->cmd |= cpu_to_be32(V_T5_ULP_MEMIO_ORDER(1)); -- 2.7.0