From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755999AbcA2MEy (ORCPT ); Fri, 29 Jan 2016 07:04:54 -0500 Received: from mail-bn1bon0116.outbound.protection.outlook.com ([157.56.111.116]:23648 "EHLO na01-bn1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1755368AbcA2MEu (ORCPT ); Fri, 29 Jan 2016 07:04:50 -0500 X-Greylist: delayed 909 seconds by postgrey-1.27 at vger.kernel.org; Fri, 29 Jan 2016 07:04:50 EST Authentication-Results: spf=permerror (sender IP is 192.88.168.50) smtp.mailfrom=freescale.com; nxp.com; dkim=none (message not signed) header.d=none;nxp.com; dmarc=none action=none header.from=freescale.com; From: Yunhui Cui To: , , CC: , , , Subject: [PATCH 3/3] mtd:spi-nor:fsl-quadspi:Add fast-read mode support Date: Fri, 29 Jan 2016 19:41:09 +0800 Message-ID: <1454067669-35274-4-git-send-email-B56489@freescale.com> X-Mailer: git-send-email 2.1.0.27.g96db324 In-Reply-To: <1454067669-35274-1-git-send-email-B56489@freescale.com> References: <1454067669-35274-1-git-send-email-B56489@freescale.com> X-EOPAttributedMessage: 0 X-Microsoft-Exchange-Diagnostics: 1;BL2FFO11OLC004;1:aVQlEy4nr8HET0arc4HWyS5WZp5MdEwWbfM5xiruWdN0QK/YqEGlrlGnxMNEZQ2xldyy8s1kojbElqP7TAq+301rxdkXAJFoDMr0TJL6monxnunJonNfOEJilYZ7lNNaTkS2lyjv+4cfNPvAahsUoknBwF8y/1ON2S4sVdrqzavEITtkKg2S8lNzUm7qIH8O0oUhAcCNiaQ3SKYCk1K9LF39Z8iBiYJlghZTVh2WFr+Y9YdX2SaM9D1CdmPMpCapgHzgnDD5mj17QY1bEe0G6fcDr7o7Z2lUzel/HOyaFNFxbSC04zICEvZK45S7Xnf6AkXlQiYc/CtM8ZBkkFo6TVkhelm7M+3ja+dlGkqL4C1IdNaF9JbuBtrFohP7IgxQ25DHCmPAw3JLPav6uzyYdUCqwij+5v6PyCaxgEoAdHZJ2mGN9Gv27SXPVgbSyxhcHv1UhgszFJ99AMMKs0FG1A== X-Forefront-Antispam-Report: CIP:192.88.168.50;CTRY:US;IPV:NLI;EFV:NLI;SFV:NSPM;SFS:(10019020)(6009001)(2980300002)(448002)(199003)(189002)(11100500001)(87936001)(6806005)(76176999)(5008740100001)(50226001)(586003)(36756003)(4001450100002)(77096005)(5001770100001)(189998001)(104016004)(1220700001)(1096002)(50986999)(2950100001)(5001960100002)(92566002)(47776003)(5003940100001)(2906002)(48376002)(4326007)(19580405001)(50466002)(85326001)(19580395003)(2201001)(575784001)(86362001)(106466001)(229853001)(3470700001)(7059030);DIR:OUT;SFP:1102;SCL:1;SRVR:BY2PR03MB076;H:tx30smr01.am.freescale.net;FPR:;SPF:PermError;MLV:sfv;A:1;MX:1;LANG:en; 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Also add some special operations for Micron flash read/write in spi-nor.c. Signed-off-by: Yunhui Cui --- drivers/mtd/spi-nor/fsl-quadspi.c | 27 +++++++++++++++++++++------ drivers/mtd/spi-nor/spi-nor.c | 6 +++++- 2 files changed, 26 insertions(+), 7 deletions(-) diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-quadspi.c index 9861290..fc4451d 100644 --- a/drivers/mtd/spi-nor/fsl-quadspi.c +++ b/drivers/mtd/spi-nor/fsl-quadspi.c @@ -389,11 +389,21 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) /* Read */ lut_base = SEQID_READ * 4; - qspi_writel(q, LUT0(CMD, PAD1, read_op) | LUT1(ADDR, PAD1, addrlen), - base + QUADSPI_LUT(lut_base)); - qspi_writel(q, LUT0(DUMMY, PAD1, read_dm) | - LUT1(FSL_READ, PAD4, rxfifo), - base + QUADSPI_LUT(lut_base + 1)); + if (nor->flash_read == SPI_NOR_FAST) { + qspi_writel(q, LUT0(CMD, PAD1, read_op) | + LUT1(ADDR, PAD1, addrlen), + base + QUADSPI_LUT(lut_base)); + qspi_writel(q, LUT0(DUMMY, PAD1, read_dm) | + LUT1(FSL_READ, PAD1, rxfifo), + base + QUADSPI_LUT(lut_base + 1)); + } else if (nor->flash_read == SPI_NOR_QUAD) { + qspi_writel(q, LUT0(CMD, PAD1, read_op) | + LUT1(ADDR, PAD1, addrlen), + base + QUADSPI_LUT(lut_base)); + qspi_writel(q, LUT0(DUMMY, PAD1, read_dm) | + LUT1(FSL_READ, PAD4, rxfifo), + base + QUADSPI_LUT(lut_base + 1)); + } /* Write enable */ lut_base = SEQID_WREN * 4; @@ -468,6 +478,7 @@ static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd) { switch (cmd) { case SPINOR_OP_READ_1_1_4: + case SPINOR_OP_READ_FAST: return SEQID_READ; case SPINOR_OP_WREN: return SEQID_WREN; @@ -963,6 +974,7 @@ static int fsl_qspi_probe(struct platform_device *pdev) struct spi_nor *nor; struct mtd_info *mtd; int ret, i = 0; + enum read_mode mode = SPI_NOR_QUAD; q = devm_kzalloc(dev, sizeof(*q), GFP_KERNEL); if (!q) @@ -1064,7 +1076,10 @@ static int fsl_qspi_probe(struct platform_device *pdev) /* set the chip address for READID */ fsl_qspi_set_base_addr(q, nor); - ret = spi_nor_scan(nor, NULL, SPI_NOR_QUAD); + ret = of_property_read_bool(np, "fast-read"); + mode = (ret) ? SPI_NOR_FAST : SPI_NOR_QUAD; + + ret = spi_nor_scan(nor, NULL, mode); if (ret) goto mutex_failed; diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index ed0c19c..79a025c 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -763,7 +763,8 @@ static const struct flash_info spi_nor_ids[] = { { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ) }, - { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ) }, + { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SPI_NOR_FAST | + SPI_NOR_QUAD_READ) }, { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) }, { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, @@ -1233,6 +1234,7 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode) if (JEDEC_MFR(info) == SNOR_MFR_ATMEL || JEDEC_MFR(info) == SNOR_MFR_INTEL || + JEDEC_MFR(info) == SNOR_MFR_MICRON || JEDEC_MFR(info) == SNOR_MFR_SST) { write_enable(nor); write_sr(nor, 0); @@ -1317,6 +1319,8 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode) nor->flash_read = SPI_NOR_QUAD; } else if (mode == SPI_NOR_DUAL && info->flags & SPI_NOR_DUAL_READ) { nor->flash_read = SPI_NOR_DUAL; + } else if (mode == SPI_NOR_FAST && info->flags & SPI_NOR_FAST) { + nor->flash_read = SPI_NOR_FAST; } /* Default commands */ -- 2.1.0.27.g96db324 From mboxrd@z Thu Jan 1 00:00:00 1970 From: B56489@freescale.com (Yunhui Cui) Date: Fri, 29 Jan 2016 19:41:09 +0800 Subject: [PATCH 3/3] mtd:spi-nor:fsl-quadspi:Add fast-read mode support In-Reply-To: <1454067669-35274-1-git-send-email-B56489@freescale.com> References: <1454067669-35274-1-git-send-email-B56489@freescale.com> Message-ID: <1454067669-35274-4-git-send-email-B56489@freescale.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org The qspi driver add generic fast-read mode for different flash venders, including Micron family. Also add some special operations for Micron flash read/write in spi-nor.c. Signed-off-by: Yunhui Cui --- drivers/mtd/spi-nor/fsl-quadspi.c | 27 +++++++++++++++++++++------ drivers/mtd/spi-nor/spi-nor.c | 6 +++++- 2 files changed, 26 insertions(+), 7 deletions(-) diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-quadspi.c index 9861290..fc4451d 100644 --- a/drivers/mtd/spi-nor/fsl-quadspi.c +++ b/drivers/mtd/spi-nor/fsl-quadspi.c @@ -389,11 +389,21 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) /* Read */ lut_base = SEQID_READ * 4; - qspi_writel(q, LUT0(CMD, PAD1, read_op) | LUT1(ADDR, PAD1, addrlen), - base + QUADSPI_LUT(lut_base)); - qspi_writel(q, LUT0(DUMMY, PAD1, read_dm) | - LUT1(FSL_READ, PAD4, rxfifo), - base + QUADSPI_LUT(lut_base + 1)); + if (nor->flash_read == SPI_NOR_FAST) { + qspi_writel(q, LUT0(CMD, PAD1, read_op) | + LUT1(ADDR, PAD1, addrlen), + base + QUADSPI_LUT(lut_base)); + qspi_writel(q, LUT0(DUMMY, PAD1, read_dm) | + LUT1(FSL_READ, PAD1, rxfifo), + base + QUADSPI_LUT(lut_base + 1)); + } else if (nor->flash_read == SPI_NOR_QUAD) { + qspi_writel(q, LUT0(CMD, PAD1, read_op) | + LUT1(ADDR, PAD1, addrlen), + base + QUADSPI_LUT(lut_base)); + qspi_writel(q, LUT0(DUMMY, PAD1, read_dm) | + LUT1(FSL_READ, PAD4, rxfifo), + base + QUADSPI_LUT(lut_base + 1)); + } /* Write enable */ lut_base = SEQID_WREN * 4; @@ -468,6 +478,7 @@ static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd) { switch (cmd) { case SPINOR_OP_READ_1_1_4: + case SPINOR_OP_READ_FAST: return SEQID_READ; case SPINOR_OP_WREN: return SEQID_WREN; @@ -963,6 +974,7 @@ static int fsl_qspi_probe(struct platform_device *pdev) struct spi_nor *nor; struct mtd_info *mtd; int ret, i = 0; + enum read_mode mode = SPI_NOR_QUAD; q = devm_kzalloc(dev, sizeof(*q), GFP_KERNEL); if (!q) @@ -1064,7 +1076,10 @@ static int fsl_qspi_probe(struct platform_device *pdev) /* set the chip address for READID */ fsl_qspi_set_base_addr(q, nor); - ret = spi_nor_scan(nor, NULL, SPI_NOR_QUAD); + ret = of_property_read_bool(np, "fast-read"); + mode = (ret) ? SPI_NOR_FAST : SPI_NOR_QUAD; + + ret = spi_nor_scan(nor, NULL, mode); if (ret) goto mutex_failed; diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index ed0c19c..79a025c 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -763,7 +763,8 @@ static const struct flash_info spi_nor_ids[] = { { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ) }, - { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ) }, + { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SPI_NOR_FAST | + SPI_NOR_QUAD_READ) }, { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) }, { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, @@ -1233,6 +1234,7 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode) if (JEDEC_MFR(info) == SNOR_MFR_ATMEL || JEDEC_MFR(info) == SNOR_MFR_INTEL || + JEDEC_MFR(info) == SNOR_MFR_MICRON || JEDEC_MFR(info) == SNOR_MFR_SST) { write_enable(nor); write_sr(nor, 0); @@ -1317,6 +1319,8 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode) nor->flash_read = SPI_NOR_QUAD; } else if (mode == SPI_NOR_DUAL && info->flags & SPI_NOR_DUAL_READ) { nor->flash_read = SPI_NOR_DUAL; + } else if (mode == SPI_NOR_FAST && info->flags & SPI_NOR_FAST) { + nor->flash_read = SPI_NOR_FAST; } /* Default commands */ -- 2.1.0.27.g96db324