[U-Boot] [PATCH 00/23] x86: Convert to use DM PCI APIs completely

[U-Boot] [PATCH 00/23] x86: Convert to use DM PCI APIs completely

[Bin Meng]

There are still some codes that use the legacy PCI APIs to access
the configuration space registers. This series converts those codes
to completely use DM PCI APIs.

This includes adding several new ops to the PCH uclass driver, and
some clean up to the SPI/GPIO/IRQ drivers.

Tested on QEMU and Crown Bay. This series is available in pci-working
branch of u-boot-x86 repo.


Bin Meng (23):
  spi: ich: Some clean up
  spi: ich: Use compatible strings to distinguish controller version
  spi: ich: Change PCHV_ to ICHV_
  x86: tnc: Drop unprotect_spi_flash()
  x86: quark: Drop unprotect_spi_flash()
  dm: pch: Remove pch_get_version op
  dm: pch: Rename get_sbase op to get_spi_base
  dm: pch: Add get_gpio_base op
  x86: pch: Implement get_gpio_base op
  dm: pch: Add get_io_base op
  x86: pch9: Implement get_io_base op
  x86: ich6_gpio: Convert to use proper DM API
  x86: Drop asm/arch/gpio.h
  x86: minnowmax: Drop io-base property in the pch_pinctrl node
  x86: irq: Get irq_router's bdf via dm_pci_get_bdf()
  x86: irq: Move irq_router to a per driver priv
  x86: irq: Convert to use DM PCI API
  x86: tnc: Change disable_igd() to have a return value
  x86: tnc: Use DM PCI API in disable_igd()
  x86: tnc: Remove IGD and SDVO devices from driver model
  x86: qemu: Convert to use DM PCI API
  x86: pci: Use DM PCI APIs in pci_assign_irqs()
  x86: pci: Drop legacy PCI APIs

 arch/x86/cpu/irq.c                         |  80 +++++++++---------
 arch/x86/cpu/ivybridge/bd82x6x.c           |  43 ++++++++--
 arch/x86/cpu/pci.c                         |  59 +-------------
 arch/x86/cpu/qemu/qemu.c                   |  34 ++++----
 arch/x86/cpu/quark/quark.c                 |  17 ----
 arch/x86/cpu/queensbay/irq.c               |   2 +-
 arch/x86/cpu/queensbay/tnc.c               |  80 +++++++++++++-----
 arch/x86/dts/bayleybay.dts                 |  88 ++++++++++----------
 arch/x86/dts/broadwell_som-6896.dts        |   2 +-
 arch/x86/dts/chromebook_link.dts           |  44 +++++-----
 arch/x86/dts/chromebox_panther.dts         |  46 ++++++-----
 arch/x86/dts/crownbay.dts                  |  32 ++++----
 arch/x86/dts/galileo.dts                   |  30 +++----
 arch/x86/dts/minnowmax.dts                 |  89 ++++++++++----------
 arch/x86/include/asm/arch-baytrail/gpio.h  |  13 ---
 arch/x86/include/asm/arch-coreboot/gpio.h  |  13 ---
 arch/x86/include/asm/arch-efi/gpio.h       |  10 ---
 arch/x86/include/asm/arch-ivybridge/gpio.h |  13 ---
 arch/x86/include/asm/arch-qemu/gpio.h      |  13 ---
 arch/x86/include/asm/arch-quark/gpio.h     |  13 ---
 arch/x86/include/asm/arch-queensbay/gpio.h |  13 ---
 arch/x86/include/asm/gpio.h                |   1 -
 arch/x86/include/asm/pci.h                 |  12 ---
 arch/x86/include/asm/pirq_routing.h        |  12 ++-
 arch/x86/lib/pirq_routing.c                |  12 +--
 board/intel/galileo/galileo.c              |   5 +-
 drivers/gpio/intel_ich6_gpio.c             | 125 ++++++-----------------------
 drivers/pch/pch-uclass.c                   |  30 ++++---
 drivers/pch/pch7.c                         |  43 ++++++++--
 drivers/pch/pch9.c                         |  54 +++++++++++--
 drivers/spi/ich.c                          |  76 ++++++++----------
 drivers/spi/ich.h                          |  61 ++++++++++----
 include/configs/crownbay.h                 |   1 -
 include/pch.h                              |  64 +++++++++------
 34 files changed, 588 insertions(+), 642 deletions(-)
 delete mode 100644 arch/x86/include/asm/arch-baytrail/gpio.h
 delete mode 100644 arch/x86/include/asm/arch-coreboot/gpio.h
 delete mode 100644 arch/x86/include/asm/arch-efi/gpio.h
 delete mode 100644 arch/x86/include/asm/arch-ivybridge/gpio.h
 delete mode 100644 arch/x86/include/asm/arch-qemu/gpio.h
 delete mode 100644 arch/x86/include/asm/arch-quark/gpio.h
 delete mode 100644 arch/x86/include/asm/arch-queensbay/gpio.h

-- 
1.8.2.1

[U-Boot] [PATCH 01/23] spi: ich: Some clean up

[Bin Meng]

This cleans up the ich spi driver a little bit:
- Remove struct ich_spi_slave that is not referenced anywhere
- Remove ending period in some comments
- Move struct ich_spi_platdata and struct ich_spi_priv to ich.h
- Add #ifndef _ICH_H_ .. in ich.h

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

 drivers/spi/ich.c | 38 +++++--------------------------------
 drivers/spi/ich.h | 56 +++++++++++++++++++++++++++++++++++++++++--------------
 2 files changed, 47 insertions(+), 47 deletions(-)

diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c
index e543b8f..22b5419 100644
--- a/drivers/spi/ich.c
+++ b/drivers/spi/ich.c
@@ -5,6 +5,7 @@
  *
  * This file is derived from the flashrom project.
  */
+
 #include <common.h>
 #include <dm.h>
 #include <errno.h>
@@ -17,41 +18,12 @@
 
 #include "ich.h"
 
-#define SPI_OPCODE_WREN      0x06
-#define SPI_OPCODE_FAST_READ 0x0b
-
 #ifdef DEBUG_TRACE
 #define debug_trace(fmt, args...) debug(fmt, ##args)
 #else
 #define debug_trace(x, args...)
 #endif
 
-struct ich_spi_platdata {
-	enum pch_version ich_version;	/* Controller version, 7 or 9 */
-};
-
-struct ich_spi_priv {
-	int ichspi_lock;
-	int locked;
-	int opmenu;
-	int menubytes;
-	void *base;		/* Base of register set */
-	int preop;
-	int optype;
-	int addr;
-	int data;
-	unsigned databytes;
-	int status;
-	int control;
-	int bbar;
-	int bcr;
-	uint32_t *pr;		/* only for ich9 */
-	int speed;		/* pointer to speed control */
-	ulong max_speed;	/* Maximum bus speed in MHz */
-	ulong cur_speed;	/* Current bus speed */
-	struct spi_trans trans;	/* current transaction in progress */
-};
-
 static u8 ich_readb(struct ich_spi_priv *priv, int reg)
 {
 	u8 value = readb(priv->base + reg);
@@ -217,7 +189,7 @@ static void spi_setup_type(struct spi_trans *trans, int data_bytes)
 {
 	trans->type = 0xFF;
 
-	/* Try to guess spi type from read/write sizes. */
+	/* Try to guess spi type from read/write sizes */
 	if (trans->bytesin == 0) {
 		if (trans->bytesout + data_bytes > 4)
 			/*
@@ -301,7 +273,7 @@ static int spi_setup_opcode(struct ich_spi_priv *ctlr, struct spi_trans *trans)
 
 static int spi_setup_offset(struct spi_trans *trans)
 {
-	/* Separate the SPI address and data. */
+	/* Separate the SPI address and data */
 	switch (trans->type) {
 	case SPI_OPCODE_TYPE_READ_NO_ADDRESS:
 	case SPI_OPCODE_TYPE_WRITE_NO_ADDRESS:
@@ -410,7 +382,7 @@ static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen,
 	trans->in = din;
 	trans->bytesin = din ? bytes : 0;
 
-	/* There has to always at least be an opcode. */
+	/* There has to always at least be an opcode */
 	if (!trans->bytesout) {
 		debug("ICH SPI: No opcode for transfer\n");
 		return -EPROTO;
@@ -541,7 +513,7 @@ static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen,
 		/* write it */
 		ich_writew(ctlr, control, ctlr->control);
 
-		/* Wait for Cycle Done Status or Flash Cycle Error. */
+		/* Wait for Cycle Done Status or Flash Cycle Error */
 		status = ich_status_poll(ctlr, SPIS_CDS | SPIS_FCERR, 1);
 		if (status < 0)
 			return status;
diff --git a/drivers/spi/ich.h b/drivers/spi/ich.h
index 1419b23..6344e80 100644
--- a/drivers/spi/ich.h
+++ b/drivers/spi/ich.h
@@ -6,6 +6,9 @@
  * This file is derived from the flashrom project.
  */
 
+#ifndef _ICH_H_
+#define _ICH_H_
+
 struct ich7_spi_regs {
 	uint16_t spis;
 	uint16_t spic;
@@ -19,34 +22,34 @@ struct ich7_spi_regs {
 } __packed;
 
 struct ich9_spi_regs {
-	uint32_t bfpr;			/* 0x00 */
+	uint32_t bfpr;		/* 0x00 */
 	uint16_t hsfs;
 	uint16_t hsfc;
 	uint32_t faddr;
 	uint32_t _reserved0;
-	uint32_t fdata[16];		/* 0x10 */
-	uint32_t frap;			/* 0x50 */
+	uint32_t fdata[16];	/* 0x10 */
+	uint32_t frap;		/* 0x50 */
 	uint32_t freg[5];
 	uint32_t _reserved1[3];
-	uint32_t pr[5];			/* 0x74 */
+	uint32_t pr[5];		/* 0x74 */
 	uint32_t _reserved2[2];
-	uint8_t ssfs;			/* 0x90 */
+	uint8_t ssfs;		/* 0x90 */
 	uint8_t ssfc[3];
-	uint16_t preop;			/* 0x94 */
+	uint16_t preop;		/* 0x94 */
 	uint16_t optype;
-	uint8_t opmenu[8];		/* 0x98 */
+	uint8_t opmenu[8];	/* 0x98 */
 	uint32_t bbar;
 	uint8_t _reserved3[12];
-	uint32_t fdoc;			/* 0xb0 */
+	uint32_t fdoc;		/* 0xb0 */
 	uint32_t fdod;
 	uint8_t _reserved4[8];
-	uint32_t afc;			/* 0xc0 */
+	uint32_t afc;		/* 0xc0 */
 	uint32_t lvscc;
 	uint32_t uvscc;
 	uint8_t _reserved5[4];
-	uint32_t fpb;			/* 0xd0 */
+	uint32_t fpb;		/* 0xd0 */
 	uint8_t _reserved6[28];
-	uint32_t srdl;			/* 0xf0 */
+	uint32_t srdl;		/* 0xf0 */
 	uint32_t srdc;
 	uint32_t scs;
 	uint32_t bcr;
@@ -121,8 +124,33 @@ struct spi_trans {
 	uint32_t offset;
 };
 
-struct ich_spi_slave {
-	struct spi_slave slave;
+#define SPI_OPCODE_WREN		0x06
+#define SPI_OPCODE_FAST_READ	0x0b
+
+struct ich_spi_platdata {
+	enum pch_version ich_version;	/* Controller version, 7 or 9 */
+};
+
+struct ich_spi_priv {
+	int ichspi_lock;
+	int locked;
+	int opmenu;
+	int menubytes;
+	void *base;		/* Base of register set */
+	int preop;
+	int optype;
+	int addr;
+	int data;
+	unsigned databytes;
+	int status;
+	int control;
+	int bbar;
+	int bcr;
+	uint32_t *pr;		/* only for ich9 */
+	int speed;		/* pointer to speed control */
+	ulong max_speed;	/* Maximum bus speed in MHz */
+	ulong cur_speed;	/* Current bus speed */
 	struct spi_trans trans;	/* current transaction in progress */
-	int speed;		/* SPI speed in Hz */
 };
+
+#endif /* _ICH_H_ */
-- 
1.8.2.1

[U-Boot] [PATCH 02/23] spi: ich: Use compatible strings to distinguish controller version

[Bin Meng]

At present ich spi driver gets the controller version information via
pch, but this can be simply retrieved via spi node's compatible string.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

 arch/x86/dts/bayleybay.dts          |  2 +-
 arch/x86/dts/broadwell_som-6896.dts |  2 +-
 arch/x86/dts/chromebook_link.dts    |  2 +-
 arch/x86/dts/chromebox_panther.dts  |  2 +-
 arch/x86/dts/crownbay.dts           |  2 +-
 arch/x86/dts/galileo.dts            |  2 +-
 arch/x86/dts/minnowmax.dts          |  2 +-
 drivers/spi/ich.c                   | 28 ++++++++++++++++++++++++----
 8 files changed, 31 insertions(+), 11 deletions(-)

diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts
index fbca467..cdd5121 100644
--- a/arch/x86/dts/bayleybay.dts
+++ b/arch/x86/dts/bayleybay.dts
@@ -187,7 +187,7 @@
 			spi: spi {
 				#address-cells = <1>;
 				#size-cells = <0>;
-				compatible = "intel,ich-spi";
+				compatible = "intel,ich9-spi";
 				spi-flash at 0 {
 					#address-cells = <1>;
 					#size-cells = <1>;
diff --git a/arch/x86/dts/broadwell_som-6896.dts b/arch/x86/dts/broadwell_som-6896.dts
index 7b2c515..4bb0a34 100644
--- a/arch/x86/dts/broadwell_som-6896.dts
+++ b/arch/x86/dts/broadwell_som-6896.dts
@@ -37,7 +37,7 @@
 			spi: spi {
 				#address-cells = <1>;
 				#size-cells = <0>;
-				compatible = "intel,ich-spi";
+				compatible = "intel,ich9-spi";
 				spi-flash at 0 {
 					reg = <0>;
 					compatible = "winbond,w25q128", "spi-flash";
diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts
index 5807203..e5d77b6 100644
--- a/arch/x86/dts/chromebook_link.dts
+++ b/arch/x86/dts/chromebook_link.dts
@@ -255,7 +255,7 @@
 			spi: spi {
 				#address-cells = <1>;
 				#size-cells = <0>;
-				compatible = "intel,ich-spi";
+				compatible = "intel,ich9-spi";
 				spi-flash at 0 {
 					#size-cells = <1>;
 					#address-cells = <1>;
diff --git a/arch/x86/dts/chromebox_panther.dts b/arch/x86/dts/chromebox_panther.dts
index 48f0c77..ce8825f 100644
--- a/arch/x86/dts/chromebox_panther.dts
+++ b/arch/x86/dts/chromebox_panther.dts
@@ -59,7 +59,7 @@
 			spi: spi {
 				#address-cells = <1>;
 				#size-cells = <0>;
-				compatible = "intel,ich-spi";
+				compatible = "intel,ich9-spi";
 				spi-flash at 0 {
 					#size-cells = <1>;
 					#address-cells = <1>;
diff --git a/arch/x86/dts/crownbay.dts b/arch/x86/dts/crownbay.dts
index 67398c4..ccf90fd 100644
--- a/arch/x86/dts/crownbay.dts
+++ b/arch/x86/dts/crownbay.dts
@@ -234,7 +234,7 @@
 			spi: spi {
 				#address-cells = <1>;
 				#size-cells = <0>;
-				compatible = "intel,ich-spi";
+				compatible = "intel,ich7-spi";
 				spi-flash at 0 {
 					reg = <0>;
 					compatible = "sst,25vf016b",
diff --git a/arch/x86/dts/galileo.dts b/arch/x86/dts/galileo.dts
index dd75fc4..a9b2994 100644
--- a/arch/x86/dts/galileo.dts
+++ b/arch/x86/dts/galileo.dts
@@ -118,7 +118,7 @@
 			spi: spi {
 				#address-cells = <1>;
 				#size-cells = <0>;
-				compatible = "intel,ich-spi";
+				compatible = "intel,ich7-spi";
 				spi-flash at 0 {
 					#size-cells = <1>;
 					#address-cells = <1>;
diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
index 7afdf6c..5b4da6c 100644
--- a/arch/x86/dts/minnowmax.dts
+++ b/arch/x86/dts/minnowmax.dts
@@ -221,7 +221,7 @@
 			spi: spi {
 				#address-cells = <1>;
 				#size-cells = <0>;
-				compatible = "intel,ich-spi";
+				compatible = "intel,ich9-spi";
 				spi-flash at 0 {
 					#address-cells = <1>;
 					#size-cells = <1>;
diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c
index 22b5419..b863539 100644
--- a/drivers/spi/ich.c
+++ b/drivers/spi/ich.c
@@ -18,6 +18,8 @@
 
 #include "ich.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #ifdef DEBUG_TRACE
 #define debug_trace(fmt, args...) debug(fmt, ##args)
 #else
@@ -594,9 +596,6 @@ static int ich_spi_probe(struct udevice *dev)
 	uint8_t bios_cntl;
 	int ret;
 
-	/* Check the ICH version */
-	plat->ich_version = pch_get_version(dev->parent);
-
 	ret = ich_init_controller(dev, plat, priv);
 	if (ret)
 		return ret;
@@ -658,6 +657,25 @@ static int ich_spi_child_pre_probe(struct udevice *dev)
 	return 0;
 }
 
+static int ich_spi_ofdata_to_platdata(struct udevice *dev)
+{
+	struct ich_spi_platdata *plat = dev_get_platdata(dev);
+	int ret;
+
+	ret = fdt_node_check_compatible(gd->fdt_blob, dev->of_offset,
+					"intel,ich7-spi");
+	if (ret == 0) {
+		plat->ich_version = PCHV_7;
+	} else {
+		ret = fdt_node_check_compatible(gd->fdt_blob, dev->of_offset,
+						"intel,ich9-spi");
+		if (ret == 0)
+			plat->ich_version = PCHV_9;
+	}
+
+	return ret;
+}
+
 static const struct dm_spi_ops ich_spi_ops = {
 	.xfer		= ich_spi_xfer,
 	.set_speed	= ich_spi_set_speed,
@@ -669,7 +687,8 @@ static const struct dm_spi_ops ich_spi_ops = {
 };
 
 static const struct udevice_id ich_spi_ids[] = {
-	{ .compatible = "intel,ich-spi" },
+	{ .compatible = "intel,ich7-spi" },
+	{ .compatible = "intel,ich9-spi" },
 	{ }
 };
 
@@ -678,6 +697,7 @@ U_BOOT_DRIVER(ich_spi) = {
 	.id	= UCLASS_SPI,
 	.of_match = ich_spi_ids,
 	.ops	= &ich_spi_ops,
+	.ofdata_to_platdata = ich_spi_ofdata_to_platdata,
 	.platdata_auto_alloc_size = sizeof(struct ich_spi_platdata),
 	.priv_auto_alloc_size = sizeof(struct ich_spi_priv),
 	.child_pre_probe = ich_spi_child_pre_probe,
-- 
1.8.2.1

[U-Boot] [PATCH 03/23] spi: ich: Change PCHV_ to ICHV_

[Bin Meng]

The ICH SPI controller supports two variants, one of which is ICH7
compatible and the other is ICH9 compatible. Change 'pch_version'
to 'ich_version' to better match its original name.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

 drivers/spi/ich.c | 14 +++++++-------
 drivers/spi/ich.h |  7 ++++++-
 2 files changed, 13 insertions(+), 8 deletions(-)

diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c
index b863539..1acdc88 100644
--- a/drivers/spi/ich.c
+++ b/drivers/spi/ich.c
@@ -123,7 +123,7 @@ static int ich_init_controller(struct udevice *dev,
 	sbase = (void *)sbase_addr;
 	debug("%s: sbase=%p\n", __func__, sbase);
 
-	if (plat->ich_version == PCHV_7) {
+	if (plat->ich_version == ICHV_7) {
 		struct ich7_spi_regs *ich7_spi = sbase;
 
 		ich7_spi = (struct ich7_spi_regs *)sbase;
@@ -139,7 +139,7 @@ static int ich_init_controller(struct udevice *dev,
 		ctlr->bbar = offsetof(struct ich7_spi_regs, bbar);
 		ctlr->preop = offsetof(struct ich7_spi_regs, preop);
 		ctlr->base = ich7_spi;
-	} else if (plat->ich_version == PCHV_9) {
+	} else if (plat->ich_version == ICHV_9) {
 		struct ich9_spi_regs *ich9_spi = sbase;
 
 		ctlr->ichspi_lock = readw(&ich9_spi->hsfs) & HSFS_FLOCKDN;
@@ -165,7 +165,7 @@ static int ich_init_controller(struct udevice *dev,
 
 	/* Work out the maximum speed we can support */
 	ctlr->max_speed = 20000000;
-	if (plat->ich_version == PCHV_9 && ich9_can_do_33mhz(dev))
+	if (plat->ich_version == ICHV_9 && ich9_can_do_33mhz(dev))
 		ctlr->max_speed = 33000000;
 	debug("ICH SPI: Version ID %d detected at %p, speed %ld\n",
 	      plat->ich_version, ctlr->base, ctlr->max_speed);
@@ -394,7 +394,7 @@ static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen,
 	if (ret < 0)
 		return ret;
 
-	if (plat->ich_version == PCHV_7)
+	if (plat->ich_version == ICHV_7)
 		ich_writew(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status);
 	else
 		ich_writeb(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status);
@@ -649,7 +649,7 @@ static int ich_spi_child_pre_probe(struct udevice *dev)
 	 * ICH 7 SPI controller only supports array read command
 	 * and byte program command for SST flash
 	 */
-	if (plat->ich_version == PCHV_7) {
+	if (plat->ich_version == ICHV_7) {
 		slave->mode_rx = SPI_RX_SLOW;
 		slave->mode = SPI_TX_BYTE;
 	}
@@ -665,12 +665,12 @@ static int ich_spi_ofdata_to_platdata(struct udevice *dev)
 	ret = fdt_node_check_compatible(gd->fdt_blob, dev->of_offset,
 					"intel,ich7-spi");
 	if (ret == 0) {
-		plat->ich_version = PCHV_7;
+		plat->ich_version = ICHV_7;
 	} else {
 		ret = fdt_node_check_compatible(gd->fdt_blob, dev->of_offset,
 						"intel,ich9-spi");
 		if (ret == 0)
-			plat->ich_version = PCHV_9;
+			plat->ich_version = ICHV_9;
 	}
 
 	return ret;
diff --git a/drivers/spi/ich.h b/drivers/spi/ich.h
index 6344e80..bd0a820 100644
--- a/drivers/spi/ich.h
+++ b/drivers/spi/ich.h
@@ -127,8 +127,13 @@ struct spi_trans {
 #define SPI_OPCODE_WREN		0x06
 #define SPI_OPCODE_FAST_READ	0x0b
 
+enum ich_version {
+	ICHV_7,
+	ICHV_9,
+};
+
 struct ich_spi_platdata {
-	enum pch_version ich_version;	/* Controller version, 7 or 9 */
+	enum ich_version ich_version;	/* Controller version, 7 or 9 */
 };
 
 struct ich_spi_priv {
-- 
1.8.2.1

[U-Boot] [PATCH 04/23] x86: tnc: Drop unprotect_spi_flash()

[Bin Meng]

Unprotecting SPI flash is now handled in the SPI controller driver,
via a call to the PCH driver. Drop the ad-hoc version.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

 arch/x86/cpu/queensbay/tnc.c | 16 ----------------
 include/configs/crownbay.h   |  1 -
 2 files changed, 17 deletions(-)

diff --git a/arch/x86/cpu/queensbay/tnc.c b/arch/x86/cpu/queensbay/tnc.c
index 75f7adb..f9fddc1 100644
--- a/arch/x86/cpu/queensbay/tnc.c
+++ b/arch/x86/cpu/queensbay/tnc.c
@@ -14,15 +14,6 @@
 #include <asm/fsp/fsp_support.h>
 #include <asm/processor.h>
 
-static void unprotect_spi_flash(void)
-{
-	u32 bc;
-
-	bc = x86_pci_read_config32(TNC_LPC, 0xd8);
-	bc |= 0x1;	/* unprotect the flash */
-	x86_pci_write_config32(TNC_LPC, 0xd8, bc);
-}
-
 static void __maybe_unused disable_igd(void)
 {
 	/*
@@ -68,10 +59,3 @@ int arch_early_init_r(void)
 
 	return 0;
 }
-
-int arch_misc_init(void)
-{
-	unprotect_spi_flash();
-
-	return 0;
-}
diff --git a/include/configs/crownbay.h b/include/configs/crownbay.h
index ffd65d5..fc1a8ba 100644
--- a/include/configs/crownbay.h
+++ b/include/configs/crownbay.h
@@ -16,7 +16,6 @@
 #define CONFIG_SYS_MONITOR_LEN		(1 << 20)
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_ARCH_EARLY_INIT_R
-#define CONFIG_ARCH_MISC_INIT
 
 #define CONFIG_SMSC_LPC47M
 
-- 
1.8.2.1

[U-Boot] [PATCH 05/23] x86: quark: Drop unprotect_spi_flash()

[Bin Meng]

Unprotecting SPI flash is now handled in the SPI controller driver,
via a call to the PCH driver. Drop the ad-hoc version.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

 arch/x86/cpu/quark/quark.c | 17 -----------------
 1 file changed, 17 deletions(-)

diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c
index 6e20930..afb3463 100644
--- a/arch/x86/cpu/quark/quark.c
+++ b/arch/x86/cpu/quark/quark.c
@@ -20,21 +20,6 @@ static struct pci_device_id mmc_supported[] = {
 	{},
 };
 
-/*
- * TODO:
- *
- * This whole routine should be removed until we fully convert the ICH SPI
- * driver to DM and make use of DT to pass the bios control register offset
- */
-static void unprotect_spi_flash(void)
-{
-	u32 bc;
-
-	qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, 0xd8, &bc);
-	bc |= 0x1;	/* unprotect the flash */
-	qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, 0xd8, bc);
-}
-
 static void quark_setup_mtrr(void)
 {
 	u32 base, mask;
@@ -259,8 +244,6 @@ int arch_cpu_init(void)
 	/* Turn on legacy segments (A/B/E/F) decode to system RAM */
 	quark_enable_legacy_seg();
 
-	unprotect_spi_flash();
-
 	return 0;
 }
 
-- 
1.8.2.1

[U-Boot] [PATCH 06/23] dm: pch: Remove pch_get_version op

[Bin Meng]

pch_get_version op was only used by the ich spi controller driver,
and does not really provide a good identification of pch controller
so far, since we see plenty of Intel PCH chipsets and one differs
from another a lot, which is not simply either a PCHV_7 or PCHV_9.
Now that ich spi controller driver was updated to not get such info
from pch, the pch_get_version op is useless now.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

 arch/x86/cpu/ivybridge/bd82x6x.c |  6 ------
 drivers/pch/pch-uclass.c         | 10 ----------
 drivers/pch/pch7.c               |  6 ------
 drivers/pch/pch9.c               |  6 ------
 include/pch.h                    | 20 --------------------
 5 files changed, 48 deletions(-)

diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c
index 2b172d4..16796de 100644
--- a/arch/x86/cpu/ivybridge/bd82x6x.c
+++ b/arch/x86/cpu/ivybridge/bd82x6x.c
@@ -182,11 +182,6 @@ static int bd82x6x_pch_get_sbase(struct udevice *dev, ulong *sbasep)
 	return 0;
 }
 
-static enum pch_version bd82x6x_pch_get_version(struct udevice *dev)
-{
-	return PCHV_9;
-}
-
 static int bd82x6x_set_spi_protect(struct udevice *dev, bool protect)
 {
 	uint8_t bios_cntl;
@@ -207,7 +202,6 @@ static int bd82x6x_set_spi_protect(struct udevice *dev, bool protect)
 
 static const struct pch_ops bd82x6x_pch_ops = {
 	.get_sbase	= bd82x6x_pch_get_sbase,
-	.get_version	= bd82x6x_pch_get_version,
 	.set_spi_protect = bd82x6x_set_spi_protect,
 };
 
diff --git a/drivers/pch/pch-uclass.c b/drivers/pch/pch-uclass.c
index 4579ed1..cae4f50 100644
--- a/drivers/pch/pch-uclass.c
+++ b/drivers/pch/pch-uclass.c
@@ -23,16 +23,6 @@ int pch_get_sbase(struct udevice *dev, ulong *sbasep)
 	return ops->get_sbase(dev, sbasep);
 }
 
-enum pch_version pch_get_version(struct udevice *dev)
-{
-	struct pch_ops *ops = pch_get_ops(dev);
-
-	if (!ops->get_version)
-		return -ENOSYS;
-
-	return ops->get_version(dev);
-}
-
 int pch_set_spi_protect(struct udevice *dev, bool protect)
 {
 	struct pch_ops *ops = pch_get_ops(dev);
diff --git a/drivers/pch/pch7.c b/drivers/pch/pch7.c
index ef72422..7c6a2ca 100644
--- a/drivers/pch/pch7.c
+++ b/drivers/pch/pch7.c
@@ -22,11 +22,6 @@ static int pch7_get_sbase(struct udevice *dev, ulong *sbasep)
 	return 0;
 }
 
-static enum pch_version pch7_get_version(struct udevice *dev)
-{
-	return PCHV_7;
-}
-
 static int pch7_set_spi_protect(struct udevice *dev, bool protect)
 {
 	uint8_t bios_cntl;
@@ -44,7 +39,6 @@ static int pch7_set_spi_protect(struct udevice *dev, bool protect)
 
 static const struct pch_ops pch7_ops = {
 	.get_sbase	= pch7_get_sbase,
-	.get_version	= pch7_get_version,
 	.set_spi_protect = pch7_set_spi_protect,
 };
 
diff --git a/drivers/pch/pch9.c b/drivers/pch/pch9.c
index 529cb02..27a9fda 100644
--- a/drivers/pch/pch9.c
+++ b/drivers/pch/pch9.c
@@ -20,14 +20,8 @@ static int pch9_get_sbase(struct udevice *dev, ulong *sbasep)
 	return 0;
 }
 
-static enum pch_version pch9_get_version(struct udevice *dev)
-{
-	return PCHV_9;
-}
-
 static const struct pch_ops pch9_ops = {
 	.get_sbase	= pch9_get_sbase,
-	.get_version	= pch9_get_version,
 };
 
 static const struct udevice_id pch9_ids[] = {
diff --git a/include/pch.h b/include/pch.h
index 79f49bd..f3899d8 100644
--- a/include/pch.h
+++ b/include/pch.h
@@ -8,12 +8,6 @@
 #ifndef __pch_h
 #define __pch_h
 
-enum pch_version {
-	PCHV_UNKNOWN,
-	PCHV_7,
-	PCHV_9,
-};
-
 #define PCH_RCBA		0xf0
 
 #define BIOS_CTRL_BIOSWE	BIT(0)
@@ -30,13 +24,6 @@ struct pch_ops {
 	int (*get_sbase)(struct udevice *dev, ulong *sbasep);
 
 	/**
-	 * get_version() - get the PCH version
-	 *
-	 * @return version, or -ENOSYS if unknown
-	 */
-	enum pch_version (*get_version)(struct udevice *dev);
-
-	/**
 	 * set_spi_protect() - set whether SPI flash is protected or not
 	 *
 	 * @dev:	PCH device to adjust
@@ -59,13 +46,6 @@ struct pch_ops {
 int pch_get_sbase(struct udevice *dev, ulong *sbasep);
 
 /**
- * pch_get_version() - get the PCH version
- *
- * @return version, or -ENOSYS if unknown
- */
-enum pch_version pch_get_version(struct udevice *dev);
-
-/**
  * set_spi_protect() - set whether SPI flash is protected or not
  *
  * @dev:	PCH device to adjust
-- 
1.8.2.1

[U-Boot] [PATCH 07/23] dm: pch: Rename get_sbase op to get_spi_base

[Bin Meng]

Spell out 'sbase' to 'spi_base' so that it looks clearer.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

 arch/x86/cpu/ivybridge/bd82x6x.c | 4 ++--
 drivers/pch/pch-uclass.c         | 6 +++---
 drivers/pch/pch7.c               | 4 ++--
 drivers/pch/pch9.c               | 4 ++--
 drivers/spi/ich.c                | 2 +-
 include/pch.h                    | 8 ++++----
 6 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c
index 16796de..66a8414 100644
--- a/arch/x86/cpu/ivybridge/bd82x6x.c
+++ b/arch/x86/cpu/ivybridge/bd82x6x.c
@@ -170,7 +170,7 @@ static int bd82x6x_probe(struct udevice *dev)
 	return 0;
 }
 
-static int bd82x6x_pch_get_sbase(struct udevice *dev, ulong *sbasep)
+static int bd82x6x_pch_get_spi_base(struct udevice *dev, ulong *sbasep)
 {
 	u32 rcba;
 
@@ -201,7 +201,7 @@ static int bd82x6x_set_spi_protect(struct udevice *dev, bool protect)
 }
 
 static const struct pch_ops bd82x6x_pch_ops = {
-	.get_sbase	= bd82x6x_pch_get_sbase,
+	.get_spi_base	= bd82x6x_pch_get_spi_base,
 	.set_spi_protect = bd82x6x_set_spi_protect,
 };
 
diff --git a/drivers/pch/pch-uclass.c b/drivers/pch/pch-uclass.c
index cae4f50..b33d502 100644
--- a/drivers/pch/pch-uclass.c
+++ b/drivers/pch/pch-uclass.c
@@ -12,15 +12,15 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-int pch_get_sbase(struct udevice *dev, ulong *sbasep)
+int pch_get_spi_base(struct udevice *dev, ulong *sbasep)
 {
 	struct pch_ops *ops = pch_get_ops(dev);
 
 	*sbasep = 0;
-	if (!ops->get_sbase)
+	if (!ops->get_spi_base)
 		return -ENOSYS;
 
-	return ops->get_sbase(dev, sbasep);
+	return ops->get_spi_base(dev, sbasep);
 }
 
 int pch_set_spi_protect(struct udevice *dev, bool protect)
diff --git a/drivers/pch/pch7.c b/drivers/pch/pch7.c
index 7c6a2ca..fe1fb85 100644
--- a/drivers/pch/pch7.c
+++ b/drivers/pch/pch7.c
@@ -10,7 +10,7 @@
 
 #define BIOS_CTRL	0xd8
 
-static int pch7_get_sbase(struct udevice *dev, ulong *sbasep)
+static int pch7_get_spi_base(struct udevice *dev, ulong *sbasep)
 {
 	u32 rcba;
 
@@ -38,7 +38,7 @@ static int pch7_set_spi_protect(struct udevice *dev, bool protect)
 }
 
 static const struct pch_ops pch7_ops = {
-	.get_sbase	= pch7_get_sbase,
+	.get_spi_base	= pch7_get_spi_base,
 	.set_spi_protect = pch7_set_spi_protect,
 };
 
diff --git a/drivers/pch/pch9.c b/drivers/pch/pch9.c
index 27a9fda..5ac2e8a 100644
--- a/drivers/pch/pch9.c
+++ b/drivers/pch/pch9.c
@@ -10,7 +10,7 @@
 
 #define SBASE_ADDR	0x54
 
-static int pch9_get_sbase(struct udevice *dev, ulong *sbasep)
+static int pch9_get_spi_base(struct udevice *dev, ulong *sbasep)
 {
 	uint32_t sbase_addr;
 
@@ -21,7 +21,7 @@ static int pch9_get_sbase(struct udevice *dev, ulong *sbasep)
 }
 
 static const struct pch_ops pch9_ops = {
-	.get_sbase	= pch9_get_sbase,
+	.get_spi_base	= pch9_get_spi_base,
 };
 
 static const struct udevice_id pch9_ids[] = {
diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c
index 1acdc88..00b2fed 100644
--- a/drivers/spi/ich.c
+++ b/drivers/spi/ich.c
@@ -119,7 +119,7 @@ static int ich_init_controller(struct udevice *dev,
 	void *sbase;
 
 	/* SBASE is similar */
-	pch_get_sbase(dev->parent, &sbase_addr);
+	pch_get_spi_base(dev->parent, &sbase_addr);
 	sbase = (void *)sbase_addr;
 	debug("%s: sbase=%p\n", __func__, sbase);
 
diff --git a/include/pch.h b/include/pch.h
index f3899d8..c04cfa3 100644
--- a/include/pch.h
+++ b/include/pch.h
@@ -15,13 +15,13 @@
 /* Operations for the Platform Controller Hub */
 struct pch_ops {
 	/**
-	 * get_sbase() - get the address of SPI base
+	 * get_spi_base() - get the address of SPI base
 	 *
 	 * @dev:	PCH device to check
 	 * @sbasep:	Returns address of SPI base if available, else 0
 	 * @return 0 if OK, -ve on error (e.g. there is no SPI base)
 	 */
-	int (*get_sbase)(struct udevice *dev, ulong *sbasep);
+	int (*get_spi_base)(struct udevice *dev, ulong *sbasep);
 
 	/**
 	 * set_spi_protect() - set whether SPI flash is protected or not
@@ -37,13 +37,13 @@ struct pch_ops {
 #define pch_get_ops(dev)        ((struct pch_ops *)(dev)->driver->ops)
 
 /**
- * pch_get_sbase() - get the address of SPI base
+ * pch_get_spi_base() - get the address of SPI base
  *
  * @dev:	PCH device to check
  * @sbasep:	Returns address of SPI base if available, else 0
  * @return 0 if OK, -ve on error (e.g. there is no SPI base)
  */
-int pch_get_sbase(struct udevice *dev, ulong *sbasep);
+int pch_get_spi_base(struct udevice *dev, ulong *sbasep);
 
 /**
  * set_spi_protect() - set whether SPI flash is protected or not
-- 
1.8.2.1

[U-Boot] [PATCH 08/23] dm: pch: Add get_gpio_base op

[Bin Meng]

x86 GPIO registers are accessed via I/O port whose base address is
configured in a PCI configuration register on the PCH device. Add
an op get_gpio_base to get the GPIO base address from PCH.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

 drivers/pch/pch-uclass.c | 11 +++++++++++
 include/pch.h            | 18 ++++++++++++++++++
 2 files changed, 29 insertions(+)

diff --git a/drivers/pch/pch-uclass.c b/drivers/pch/pch-uclass.c
index b33d502..48a3965 100644
--- a/drivers/pch/pch-uclass.c
+++ b/drivers/pch/pch-uclass.c
@@ -33,6 +33,17 @@ int pch_set_spi_protect(struct udevice *dev, bool protect)
 	return ops->set_spi_protect(dev, protect);
 }
 
+int pch_get_gpio_base(struct udevice *dev, u32 *gbasep)
+{
+	struct pch_ops *ops = pch_get_ops(dev);
+
+	*gbasep = 0;
+	if (!ops->get_gpio_base)
+		return -ENOSYS;
+
+	return ops->get_gpio_base(dev, gbasep);
+}
+
 static int pch_uclass_post_bind(struct udevice *bus)
 {
 	/*
diff --git a/include/pch.h b/include/pch.h
index c04cfa3..b378865 100644
--- a/include/pch.h
+++ b/include/pch.h
@@ -32,6 +32,15 @@ struct pch_ops {
 	 * @return 0 on success, -ENOSYS if not implemented
 	 */
 	int (*set_spi_protect)(struct udevice *dev, bool protect);
+
+	/**
+	 * get_gpio_base() - get the address of GPIO base
+	 *
+	 * @dev:	PCH device to check
+	 * @gbasep:	Returns address of GPIO base if available, else 0
+	 * @return 0 if OK, -ve on error (e.g. there is no GPIO base)
+	 */
+	int (*get_gpio_base)(struct udevice *dev, u32 *gbasep);
 };
 
 #define pch_get_ops(dev)        ((struct pch_ops *)(dev)->driver->ops)
@@ -55,4 +64,13 @@ int pch_get_spi_base(struct udevice *dev, ulong *sbasep);
  */
 int pch_set_spi_protect(struct udevice *dev, bool protect);
 
+/**
+ * pch_get_gpio_base() - get the address of GPIO base
+ *
+ * @dev:	PCH device to check
+ * @gbasep:	Returns address of GPIO base if available, else 0
+ * @return 0 if OK, -ve on error (e.g. there is no GPIO base)
+ */
+int pch_get_gpio_base(struct udevice *dev, u32 *gbasep);
+
 #endif
-- 
1.8.2.1

[U-Boot] [PATCH 09/23] x86: pch: Implement get_gpio_base op

[Bin Meng]

Implement get_gpio_base op for bd82x6x, pch7 and pch9 drivers.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

 arch/x86/cpu/ivybridge/bd82x6x.c | 33 +++++++++++++++++++++++++++++++++
 drivers/pch/pch7.c               | 33 +++++++++++++++++++++++++++++++++
 drivers/pch/pch9.c               | 33 +++++++++++++++++++++++++++++++++
 3 files changed, 99 insertions(+)

diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c
index 66a8414..996707b 100644
--- a/arch/x86/cpu/ivybridge/bd82x6x.c
+++ b/arch/x86/cpu/ivybridge/bd82x6x.c
@@ -19,6 +19,7 @@
 #include <asm/arch/pch.h>
 #include <asm/arch/sandybridge.h>
 
+#define GPIO_BASE	0x48
 #define BIOS_CTRL	0xdc
 
 static int pch_revision_id = -1;
@@ -200,9 +201,41 @@ static int bd82x6x_set_spi_protect(struct udevice *dev, bool protect)
 	return 0;
 }
 
+static int bd82x6x_get_gpio_base(struct udevice *dev, u32 *gbasep)
+{
+	u32 base;
+
+	/*
+	 * GPIO_BASE moved to its current offset with ICH6, but prior to
+	 * that it was unused (or undocumented). Check that it looks
+	 * okay: not all ones or zeros.
+	 *
+	 * Note we don't need check bit0 here, because the Tunnel Creek
+	 * GPIO base address register bit0 is reserved (read returns 0),
+	 * while on the Ivybridge the bit0 is used to indicate it is an
+	 * I/O space.
+	 */
+	dm_pci_read_config32(dev, GPIO_BASE, &base);
+	if (base == 0x00000000 || base == 0xffffffff) {
+		debug("%s: unexpected BASE value\n", __func__);
+		return -ENODEV;
+	}
+
+	/*
+	 * Okay, I guess we're looking at the right device. The actual
+	 * GPIO registers are in the PCI device's I/O space, starting
+	 * at the offset that we just read. Bit 0 indicates that it's
+	 * an I/O address, not a memory address, so mask that off.
+	 */
+	*gbasep = base & 1 ? base & ~3 : base & ~15;
+
+	return 0;
+}
+
 static const struct pch_ops bd82x6x_pch_ops = {
 	.get_spi_base	= bd82x6x_pch_get_spi_base,
 	.set_spi_protect = bd82x6x_set_spi_protect,
+	.get_gpio_base	= bd82x6x_get_gpio_base,
 };
 
 static const struct udevice_id bd82x6x_ids[] = {
diff --git a/drivers/pch/pch7.c b/drivers/pch/pch7.c
index fe1fb85..302c929 100644
--- a/drivers/pch/pch7.c
+++ b/drivers/pch/pch7.c
@@ -8,6 +8,7 @@
 #include <dm.h>
 #include <pch.h>
 
+#define GPIO_BASE	0x44
 #define BIOS_CTRL	0xd8
 
 static int pch7_get_spi_base(struct udevice *dev, ulong *sbasep)
@@ -37,9 +38,41 @@ static int pch7_set_spi_protect(struct udevice *dev, bool protect)
 	return 0;
 }
 
+static int pch7_get_gpio_base(struct udevice *dev, u32 *gbasep)
+{
+	u32 base;
+
+	/*
+	 * GPIO_BASE moved to its current offset with ICH6, but prior to
+	 * that it was unused (or undocumented). Check that it looks
+	 * okay: not all ones or zeros.
+	 *
+	 * Note we don't need check bit0 here, because the Tunnel Creek
+	 * GPIO base address register bit0 is reserved (read returns 0),
+	 * while on the Ivybridge the bit0 is used to indicate it is an
+	 * I/O space.
+	 */
+	dm_pci_read_config32(dev, GPIO_BASE, &base);
+	if (base == 0x00000000 || base == 0xffffffff) {
+		debug("%s: unexpected BASE value\n", __func__);
+		return -ENODEV;
+	}
+
+	/*
+	 * Okay, I guess we're looking at the right device. The actual
+	 * GPIO registers are in the PCI device's I/O space, starting
+	 * at the offset that we just read. Bit 0 indicates that it's
+	 * an I/O address, not a memory address, so mask that off.
+	 */
+	*gbasep = base & 1 ? base & ~3 : base & ~15;
+
+	return 0;
+}
+
 static const struct pch_ops pch7_ops = {
 	.get_spi_base	= pch7_get_spi_base,
 	.set_spi_protect = pch7_set_spi_protect,
+	.get_gpio_base	= pch7_get_gpio_base,
 };
 
 static const struct udevice_id pch7_ids[] = {
diff --git a/drivers/pch/pch9.c b/drivers/pch/pch9.c
index 5ac2e8a..2a212ce 100644
--- a/drivers/pch/pch9.c
+++ b/drivers/pch/pch9.c
@@ -8,6 +8,7 @@
 #include <dm.h>
 #include <pch.h>
 
+#define GPIO_BASE	0x48
 #define SBASE_ADDR	0x54
 
 static int pch9_get_spi_base(struct udevice *dev, ulong *sbasep)
@@ -20,8 +21,40 @@ static int pch9_get_spi_base(struct udevice *dev, ulong *sbasep)
 	return 0;
 }
 
+static int pch9_get_gpio_base(struct udevice *dev, u32 *gbasep)
+{
+	u32 base;
+
+	/*
+	 * GPIO_BASE moved to its current offset with ICH6, but prior to
+	 * that it was unused (or undocumented). Check that it looks
+	 * okay: not all ones or zeros.
+	 *
+	 * Note we don't need check bit0 here, because the Tunnel Creek
+	 * GPIO base address register bit0 is reserved (read returns 0),
+	 * while on the Ivybridge the bit0 is used to indicate it is an
+	 * I/O space.
+	 */
+	dm_pci_read_config32(dev, GPIO_BASE, &base);
+	if (base == 0x00000000 || base == 0xffffffff) {
+		debug("%s: unexpected BASE value\n", __func__);
+		return -ENODEV;
+	}
+
+	/*
+	 * Okay, I guess we're looking at the right device. The actual
+	 * GPIO registers are in the PCI device's I/O space, starting
+	 * at the offset that we just read. Bit 0 indicates that it's
+	 * an I/O address, not a memory address, so mask that off.
+	 */
+	*gbasep = base & 1 ? base & ~3 : base & ~15;
+
+	return 0;
+}
+
 static const struct pch_ops pch9_ops = {
 	.get_spi_base	= pch9_get_spi_base,
+	.get_gpio_base	= pch9_get_gpio_base,
 };
 
 static const struct udevice_id pch9_ids[] = {
-- 
1.8.2.1

[U-Boot] [PATCH 10/23] dm: pch: Add get_io_base op

[Bin Meng]

On some newer chipset (eg: BayTrail), there is an IO base address
register on the PCH device which configures the base address of a
memory-mapped I/O controller.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

 drivers/pch/pch-uclass.c | 11 +++++++++++
 include/pch.h            | 18 ++++++++++++++++++
 2 files changed, 29 insertions(+)

diff --git a/drivers/pch/pch-uclass.c b/drivers/pch/pch-uclass.c
index 48a3965..7216660 100644
--- a/drivers/pch/pch-uclass.c
+++ b/drivers/pch/pch-uclass.c
@@ -44,6 +44,17 @@ int pch_get_gpio_base(struct udevice *dev, u32 *gbasep)
 	return ops->get_gpio_base(dev, gbasep);
 }
 
+int pch_get_io_base(struct udevice *dev, u32 *iobasep)
+{
+	struct pch_ops *ops = pch_get_ops(dev);
+
+	*iobasep = 0;
+	if (!ops->get_io_base)
+		return -ENOSYS;
+
+	return ops->get_io_base(dev, iobasep);
+}
+
 static int pch_uclass_post_bind(struct udevice *bus)
 {
 	/*
diff --git a/include/pch.h b/include/pch.h
index b378865..222e908 100644
--- a/include/pch.h
+++ b/include/pch.h
@@ -41,6 +41,15 @@ struct pch_ops {
 	 * @return 0 if OK, -ve on error (e.g. there is no GPIO base)
 	 */
 	int (*get_gpio_base)(struct udevice *dev, u32 *gbasep);
+
+	/**
+	 * get_io_base() - get the address of IO base
+	 *
+	 * @dev:	PCH device to check
+	 * @iobasep:	Returns address of IO base if available, else 0
+	 * @return 0 if OK, -ve on error (e.g. there is no IO base)
+	 */
+	int (*get_io_base)(struct udevice *dev, u32 *iobasep);
 };
 
 #define pch_get_ops(dev)        ((struct pch_ops *)(dev)->driver->ops)
@@ -73,4 +82,13 @@ int pch_set_spi_protect(struct udevice *dev, bool protect);
  */
 int pch_get_gpio_base(struct udevice *dev, u32 *gbasep);
 
+/**
+ * pch_get_io_base() - get the address of IO base
+ *
+ * @dev:	PCH device to check
+ * @iobasep:	Returns address of IO base if available, else 0
+ * @return 0 if OK, -ve on error (e.g. there is no IO base)
+ */
+int pch_get_io_base(struct udevice *dev, u32 *iobasep);
+
 #endif
-- 
1.8.2.1

[U-Boot] [PATCH 11/23] x86: pch9: Implement get_io_base op

[Bin Meng]

IO_BASE is only seen on PCH9 device, implement the get_io_base op.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

 drivers/pch/pch9.c | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/drivers/pch/pch9.c b/drivers/pch/pch9.c
index 2a212ce..910eb61 100644
--- a/drivers/pch/pch9.c
+++ b/drivers/pch/pch9.c
@@ -9,6 +9,7 @@
 #include <pch.h>
 
 #define GPIO_BASE	0x48
+#define IO_BASE		0x4c
 #define SBASE_ADDR	0x54
 
 static int pch9_get_spi_base(struct udevice *dev, ulong *sbasep)
@@ -52,9 +53,25 @@ static int pch9_get_gpio_base(struct udevice *dev, u32 *gbasep)
 	return 0;
 }
 
+static int pch9_get_io_base(struct udevice *dev, u32 *iobasep)
+{
+	u32 base;
+
+	dm_pci_read_config32(dev, IO_BASE, &base);
+	if (base == 0x00000000 || base == 0xffffffff) {
+		debug("%s: unexpected BASE value\n", __func__);
+		return -ENODEV;
+	}
+
+	*iobasep = base & 1 ? base & ~3 : base & ~15;
+
+	return 0;
+}
+
 static const struct pch_ops pch9_ops = {
 	.get_spi_base	= pch9_get_spi_base,
 	.get_gpio_base	= pch9_get_gpio_base,
+	.get_io_base	= pch9_get_io_base,
 };
 
 static const struct udevice_id pch9_ids[] = {
-- 
1.8.2.1

[U-Boot] [PATCH 12/23] x86: ich6_gpio: Convert to use proper DM API

[Bin Meng]

At present this GPIO driver still uses the legacy PCI API. Now that
we have proper PCH drivers we can use those to obtain the information
we need. While the device tree has nodes for the GPIO peripheral it is
not in the right place. It should be on the PCI bus as a sub-peripheral
of the PCH device.

Update the device tree files to show the GPIO controller within the PCH,
so that PCI access works as expected. This also adds #address-cells and

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

 arch/x86/dts/bayleybay.dts         |  86 ++++++++++++-------------
 arch/x86/dts/chromebook_link.dts   |  42 ++++++-------
 arch/x86/dts/chromebox_panther.dts |  44 ++++++-------
 arch/x86/dts/crownbay.dts          |  30 ++++-----
 arch/x86/dts/galileo.dts           |  28 +++++----
 arch/x86/dts/minnowmax.dts         |  86 ++++++++++++-------------
 drivers/gpio/intel_ich6_gpio.c     | 125 +++++++------------------------------
 7 files changed, 186 insertions(+), 255 deletions(-)

diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts
index cdd5121..4ea9262 100644
--- a/arch/x86/dts/bayleybay.dts
+++ b/arch/x86/dts/bayleybay.dts
@@ -65,48 +65,6 @@
 		};
 	};
 
-	gpioa {
-		compatible = "intel,ich6-gpio";
-		u-boot,dm-pre-reloc;
-		reg = <0 0x20>;
-		bank-name = "A";
-	};
-
-	gpiob {
-		compatible = "intel,ich6-gpio";
-		u-boot,dm-pre-reloc;
-		reg = <0x20 0x20>;
-		bank-name = "B";
-	};
-
-	gpioc {
-		compatible = "intel,ich6-gpio";
-		u-boot,dm-pre-reloc;
-		reg = <0x40 0x20>;
-		bank-name = "C";
-	};
-
-	gpiod {
-		compatible = "intel,ich6-gpio";
-		u-boot,dm-pre-reloc;
-		reg = <0x60 0x20>;
-		bank-name = "D";
-	};
-
-	gpioe {
-		compatible = "intel,ich6-gpio";
-		u-boot,dm-pre-reloc;
-		reg = <0x80 0x20>;
-		bank-name = "E";
-	};
-
-	gpiof {
-		compatible = "intel,ich6-gpio";
-		u-boot,dm-pre-reloc;
-		reg = <0xA0 0x20>;
-		bank-name = "F";
-	};
-
 	pci {
 		compatible = "pci-x86";
 		#address-cells = <3>;
@@ -119,6 +77,8 @@
 		pch at 1f,0 {
 			reg = <0x0000f800 0 0 0 0>;
 			compatible = "intel,pch9";
+			#address-cells = <1>;
+			#size-cells = <1>;
 
 			irq-router {
 				compatible = "intel,irq-router";
@@ -201,6 +161,48 @@
 					};
 				};
 			};
+
+			gpioa {
+				compatible = "intel,ich6-gpio";
+				u-boot,dm-pre-reloc;
+				reg = <0 0x20>;
+				bank-name = "A";
+			};
+
+			gpiob {
+				compatible = "intel,ich6-gpio";
+				u-boot,dm-pre-reloc;
+				reg = <0x20 0x20>;
+				bank-name = "B";
+			};
+
+			gpioc {
+				compatible = "intel,ich6-gpio";
+				u-boot,dm-pre-reloc;
+				reg = <0x40 0x20>;
+				bank-name = "C";
+			};
+
+			gpiod {
+				compatible = "intel,ich6-gpio";
+				u-boot,dm-pre-reloc;
+				reg = <0x60 0x20>;
+				bank-name = "D";
+			};
+
+			gpioe {
+				compatible = "intel,ich6-gpio";
+				u-boot,dm-pre-reloc;
+				reg = <0x80 0x20>;
+				bank-name = "E";
+			};
+
+			gpiof {
+				compatible = "intel,ich6-gpio";
+				u-boot,dm-pre-reloc;
+				reg = <0xA0 0x20>;
+				bank-name = "F";
+			};
 		};
 	};
 
diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts
index e5d77b6..f85e55c 100644
--- a/arch/x86/dts/chromebook_link.dts
+++ b/arch/x86/dts/chromebook_link.dts
@@ -54,27 +54,6 @@
 
 	};
 
-	gpioa {
-		compatible = "intel,ich6-gpio";
-		u-boot,dm-pre-reloc;
-		reg = <0 0x10>;
-		bank-name = "A";
-	};
-
-	gpiob {
-		compatible = "intel,ich6-gpio";
-		u-boot,dm-pre-reloc;
-		reg = <0x30 0x10>;
-		bank-name = "B";
-	};
-
-	gpioc {
-		compatible = "intel,ich6-gpio";
-		u-boot,dm-pre-reloc;
-		reg = <0x40 0x10>;
-		bank-name = "C";
-	};
-
 	chosen {
 		stdout-path = "/serial";
 	};
@@ -270,6 +249,27 @@
 				};
 			};
 
+			gpioa {
+				compatible = "intel,ich6-gpio";
+				u-boot,dm-pre-reloc;
+				reg = <0 0x10>;
+				bank-name = "A";
+			};
+
+			gpiob {
+				compatible = "intel,ich6-gpio";
+				u-boot,dm-pre-reloc;
+				reg = <0x30 0x10>;
+				bank-name = "B";
+			};
+
+			gpioc {
+				compatible = "intel,ich6-gpio";
+				u-boot,dm-pre-reloc;
+				reg = <0x40 0x10>;
+				bank-name = "C";
+			};
+
 			lpc {
 				compatible = "intel,bd82x6x-lpc";
 				#address-cells = <1>;
diff --git a/arch/x86/dts/chromebox_panther.dts b/arch/x86/dts/chromebox_panther.dts
index ce8825f..480b366 100644
--- a/arch/x86/dts/chromebox_panther.dts
+++ b/arch/x86/dts/chromebox_panther.dts
@@ -18,27 +18,6 @@
 		no-keyboard;
 	};
 
-	gpioa {
-		compatible = "intel,ich6-gpio";
-		u-boot,dm-pre-reloc;
-		reg = <0 0x10>;
-		bank-name = "A";
-	};
-
-	gpiob {
-		compatible = "intel,ich6-gpio";
-		u-boot,dm-pre-reloc;
-		reg = <0x30 0x10>;
-		bank-name = "B";
-	};
-
-	gpioc {
-		compatible = "intel,ich6-gpio";
-		u-boot,dm-pre-reloc;
-		reg = <0x40 0x10>;
-		bank-name = "C";
-	};
-
 	chosen {
 		stdout-path = "/serial";
 	};
@@ -55,6 +34,8 @@
 		pch at 1f,0 {
 			reg = <0x0000f800 0 0 0 0>;
 			compatible = "intel,pch9";
+			#address-cells = <1>;
+			#size-cells = <1>;
 
 			spi: spi {
 				#address-cells = <1>;
@@ -73,6 +54,27 @@
 					};
 				};
 			};
+
+			gpioa {
+				compatible = "intel,ich6-gpio";
+				u-boot,dm-pre-reloc;
+				reg = <0 0x10>;
+				bank-name = "A";
+			};
+
+			gpiob {
+				compatible = "intel,ich6-gpio";
+				u-boot,dm-pre-reloc;
+				reg = <0x30 0x10>;
+				bank-name = "B";
+			};
+
+			gpioc {
+				compatible = "intel,ich6-gpio";
+				u-boot,dm-pre-reloc;
+				reg = <0x40 0x10>;
+				bank-name = "C";
+			};
 		};
 	};
 
diff --git a/arch/x86/dts/crownbay.dts b/arch/x86/dts/crownbay.dts
index ccf90fd..c6933cc 100644
--- a/arch/x86/dts/crownbay.dts
+++ b/arch/x86/dts/crownbay.dts
@@ -50,20 +50,6 @@
 
 	};
 
-	gpioa {
-		compatible = "intel,ich6-gpio";
-		u-boot,dm-pre-reloc;
-		reg = <0 0x20>;
-		bank-name = "A";
-	};
-
-	gpiob {
-		compatible = "intel,ich6-gpio";
-		u-boot,dm-pre-reloc;
-		reg = <0x20 0x20>;
-		bank-name = "B";
-	};
-
 	chosen {
 		/*
 		 * By default the legacy superio serial port is used as the
@@ -166,6 +152,8 @@
 		pch at 1f,0 {
 			reg = <0x0000f800 0 0 0 0>;
 			compatible = "intel,pch7";
+			#address-cells = <1>;
+			#size-cells = <1>;
 
 			irq-router {
 				compatible = "intel,queensbay-irq-router";
@@ -242,6 +230,20 @@
 					memory-map = <0xffe00000 0x00200000>;
 				};
 			};
+
+			gpioa {
+				compatible = "intel,ich6-gpio";
+				u-boot,dm-pre-reloc;
+				reg = <0 0x20>;
+				bank-name = "A";
+			};
+
+			gpiob {
+				compatible = "intel,ich6-gpio";
+				u-boot,dm-pre-reloc;
+				reg = <0x20 0x20>;
+				bank-name = "B";
+			};
 		};
 	};
 
diff --git a/arch/x86/dts/galileo.dts b/arch/x86/dts/galileo.dts
index a9b2994..21c3641 100644
--- a/arch/x86/dts/galileo.dts
+++ b/arch/x86/dts/galileo.dts
@@ -82,6 +82,8 @@
 		pch at 1f,0 {
 			reg = <0x0000f800 0 0 0 0>;
 			compatible = "intel,pch7";
+			#address-cells = <1>;
+			#size-cells = <1>;
 
 			irq-router {
 				compatible = "intel,quark-irq-router";
@@ -132,21 +134,21 @@
 					};
 				};
 			};
-		};
-	};
 
-	gpioa {
-		compatible = "intel,ich6-gpio";
-		u-boot,dm-pre-reloc;
-		reg = <0 0x20>;
-		bank-name = "A";
-	};
+			gpioa {
+				compatible = "intel,ich6-gpio";
+				u-boot,dm-pre-reloc;
+				reg = <0 0x20>;
+				bank-name = "A";
+			};
 
-	gpiob {
-		compatible = "intel,ich6-gpio";
-		u-boot,dm-pre-reloc;
-		reg = <0x20 0x20>;
-		bank-name = "B";
+			gpiob {
+				compatible = "intel,ich6-gpio";
+				u-boot,dm-pre-reloc;
+				reg = <0x20 0x20>;
+				bank-name = "B";
+			};
+		};
 	};
 
 };
diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
index 5b4da6c..b7e3ba4 100644
--- a/arch/x86/dts/minnowmax.dts
+++ b/arch/x86/dts/minnowmax.dts
@@ -75,48 +75,6 @@
 		};
 	};
 
-	gpioa {
-		compatible = "intel,ich6-gpio";
-		u-boot,dm-pre-reloc;
-		reg = <0 0x20>;
-		bank-name = "A";
-	};
-
-	gpiob {
-		compatible = "intel,ich6-gpio";
-		u-boot,dm-pre-reloc;
-		reg = <0x20 0x20>;
-		bank-name = "B";
-	};
-
-	gpioc {
-		compatible = "intel,ich6-gpio";
-		u-boot,dm-pre-reloc;
-		reg = <0x40 0x20>;
-		bank-name = "C";
-	};
-
-	gpiod {
-		compatible = "intel,ich6-gpio";
-		u-boot,dm-pre-reloc;
-		reg = <0x60 0x20>;
-		bank-name = "D";
-	};
-
-	gpioe {
-		compatible = "intel,ich6-gpio";
-		u-boot,dm-pre-reloc;
-		reg = <0x80 0x20>;
-		bank-name = "E";
-	};
-
-	gpiof {
-		compatible = "intel,ich6-gpio";
-		u-boot,dm-pre-reloc;
-		reg = <0xA0 0x20>;
-		bank-name = "F";
-	};
-
 	chosen {
 		stdout-path = "/serial";
 	};
@@ -153,6 +111,8 @@
 		pch at 1f,0 {
 			reg = <0x0000f800 0 0 0 0>;
 			compatible = "pci8086,0f1c", "intel,pch9";
+			#address-cells = <1>;
+			#size-cells = <1>;
 
 			irq-router {
 				compatible = "intel,irq-router";
@@ -235,6 +195,48 @@
 					};
 				};
 			};
+
+			gpioa {
+				compatible = "intel,ich6-gpio";
+				u-boot,dm-pre-reloc;
+				reg = <0 0x20>;
+				bank-name = "A";
+			};
+
+			gpiob {
+				compatible = "intel,ich6-gpio";
+				u-boot,dm-pre-reloc;
+				reg = <0x20 0x20>;
+				bank-name = "B";
+			};
+
+			gpioc {
+				compatible = "intel,ich6-gpio";
+				u-boot,dm-pre-reloc;
+				reg = <0x40 0x20>;
+				bank-name = "C";
+			};
+
+			gpiod {
+				compatible = "intel,ich6-gpio";
+				u-boot,dm-pre-reloc;
+				reg = <0x60 0x20>;
+				bank-name = "D";
+			};
+
+			gpioe {
+				compatible = "intel,ich6-gpio";
+				u-boot,dm-pre-reloc;
+				reg = <0x80 0x20>;
+				bank-name = "E";
+			};
+
+			gpiof {
+				compatible = "intel,ich6-gpio";
+				u-boot,dm-pre-reloc;
+				reg = <0xA0 0x20>;
+				bank-name = "F";
+			};
 		};
 	};
 
diff --git a/drivers/gpio/intel_ich6_gpio.c b/drivers/gpio/intel_ich6_gpio.c
index 67bf0a2..527ed6d 100644
--- a/drivers/gpio/intel_ich6_gpio.c
+++ b/drivers/gpio/intel_ich6_gpio.c
@@ -30,6 +30,7 @@
 #include <dm.h>
 #include <errno.h>
 #include <fdtdec.h>
+#include <pch.h>
 #include <pci.h>
 #include <asm/gpio.h>
 #include <asm/io.h>
@@ -62,91 +63,6 @@ void ich_gpio_set_gpio_map(const struct pch_gpio_map *map)
 	gd->arch.gpio_map = map;
 }
 
-static int gpio_ich6_get_base(unsigned long base)
-{
-	pci_dev_t pci_dev;			/* handle for 0:1f:0 */
-	u8 tmpbyte;
-	u16 tmpword;
-	u32 tmplong;
-
-	/* Where should it be? */
-	pci_dev = PCI_BDF(0, 0x1f, 0);
-
-	/* Is the device present? */
-	tmpword = x86_pci_read_config16(pci_dev, PCI_VENDOR_ID);
-	if (tmpword != PCI_VENDOR_ID_INTEL) {
-		debug("%s: wrong VendorID %x\n", __func__, tmpword);
-		return -ENODEV;
-	}
-
-	tmpword = x86_pci_read_config16(pci_dev, PCI_DEVICE_ID);
-	debug("Found %04x:%04x\n", PCI_VENDOR_ID_INTEL, tmpword);
-	/*
-	 * We'd like to validate the Device ID too, but pretty much any
-	 * value is either a) correct with slight differences, or b)
-	 * correct but undocumented. We'll have to check a bunch of other
-	 * things instead...
-	 */
-
-	/* I/O should already be enabled (it's a RO bit). */
-	tmpword = x86_pci_read_config16(pci_dev, PCI_COMMAND);
-	if (!(tmpword & PCI_COMMAND_IO)) {
-		debug("%s: device IO not enabled\n", __func__);
-		return -ENODEV;
-	}
-
-	/* Header Type must be normal (bits 6-0 only; see spec.) */
-	tmpbyte = x86_pci_read_config8(pci_dev, PCI_HEADER_TYPE);
-	if ((tmpbyte & 0x7f) != PCI_HEADER_TYPE_NORMAL) {
-		debug("%s: invalid Header type\n", __func__);
-		return -ENODEV;
-	}
-
-	/* Base Class must be a bridge device */
-	tmpbyte = x86_pci_read_config8(pci_dev, PCI_CLASS_CODE);
-	if (tmpbyte != PCI_CLASS_CODE_BRIDGE) {
-		debug("%s: invalid class\n", __func__);
-		return -ENODEV;
-	}
-	/* Sub Class must be ISA */
-	tmpbyte = x86_pci_read_config8(pci_dev, PCI_CLASS_SUB_CODE);
-	if (tmpbyte != PCI_CLASS_SUB_CODE_BRIDGE_ISA) {
-		debug("%s: invalid subclass\n", __func__);
-		return -ENODEV;
-	}
-
-	/* Programming Interface must be 0x00 (no others exist) */
-	tmpbyte = x86_pci_read_config8(pci_dev, PCI_CLASS_PROG);
-	if (tmpbyte != 0x00) {
-		debug("%s: invalid interface type\n", __func__);
-		return -ENODEV;
-	}
-
-	/*
-	 * GPIOBASE moved to its current offset with ICH6, but prior to
-	 * that it was unused (or undocumented). Check that it looks
-	 * okay: not all ones or zeros.
-	 *
-	 * Note we don't need check bit0 here, because the Tunnel Creek
-	 * GPIO base address register bit0 is reserved (read returns 0),
-	 * while on the Ivybridge the bit0 is used to indicate it is an
-	 * I/O space.
-	 */
-	tmplong = x86_pci_read_config32(pci_dev, base);
-	if (tmplong == 0x00000000 || tmplong == 0xffffffff) {
-		debug("%s: unexpected BASE value\n", __func__);
-		return -ENODEV;
-	}
-
-	/*
-	 * Okay, I guess we're looking at the right device. The actual
-	 * GPIO registers are in the PCI device's I/O space, starting
-	 * at the offset that we just read. Bit 0 indicates that it's
-	 * an I/O address, not a memory address, so mask that off.
-	 */
-	return tmplong & 1 ? tmplong & ~3 : tmplong & ~15;
-}
-
 static int _ich6_gpio_set_value(uint16_t base, unsigned offset, int value)
 {
 	u32 val;
@@ -288,20 +204,26 @@ static int _gpio_ich6_pinctrl_cfg_pin(s32 gpiobase, s32 iobase, int pin_node)
 
 int gpio_ich6_pinctrl_init(void)
 {
+	struct udevice *pch;
 	int pin_node;
 	int node;
 	int ret;
-	int gpiobase;
-	int iobase_offset;
-	int iobase = -1;
+	u32 gpiobase;
+	u32 iobase = -1;
+
+	ret = uclass_first_device(UCLASS_PCH, &pch);
+	if (ret)
+		return ret;
+	if (!pch)
+		return -ENODEV;
 
 	/*
 	 * Get the memory/io base address to configure every pins.
 	 * IOBASE is used to configure the mode/pads
 	 * GPIOBASE is used to configure the direction and default value
 	 */
-	gpiobase = gpio_ich6_get_base(PCI_CFG_GPIOBASE);
-	if (gpiobase < 0) {
+	ret = pch_get_gpio_base(pch, &gpiobase);
+	if (ret) {
 		debug("%s: invalid GPIOBASE address (%08x)\n", __func__,
 		      gpiobase);
 		return -EINVAL;
@@ -319,16 +241,11 @@ int gpio_ich6_pinctrl_init(void)
 	 * Get the IOBASE, this is not mandatory as this is not
 	 * supported by all the CPU
 	 */
-	iobase_offset = fdtdec_get_int(gd->fdt_blob, node, "io-base", -1);
-	if (iobase_offset == -1) {
-		debug("%s: io-base offset not present\n", __func__);
-	} else {
-		iobase = gpio_ich6_get_base(iobase_offset);
-		if (IS_ERR_VALUE(iobase)) {
-			debug("%s: invalid IOBASE address (%08x)\n", __func__,
-			      iobase);
-			return -EINVAL;
-		}
+	ret = pch_get_io_base(pch, &iobase);
+	if (ret && ret != -ENOSYS) {
+		debug("%s: invalid IOBASE address (%08x)\n", __func__,
+		      iobase);
+		return -EINVAL;
 	}
 
 	for (pin_node = fdt_first_subnode(gd->fdt_blob, node);
@@ -349,10 +266,14 @@ int gpio_ich6_pinctrl_init(void)
 static int gpio_ich6_ofdata_to_platdata(struct udevice *dev)
 {
 	struct ich6_bank_platdata *plat = dev_get_platdata(dev);
-	u16 gpiobase;
+	u32 gpiobase;
 	int offset;
+	int ret;
+
+	ret = pch_get_gpio_base(dev->parent, &gpiobase);
+	if (ret)
+		return ret;
 
-	gpiobase = gpio_ich6_get_base(PCI_CFG_GPIOBASE);
 	offset = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "reg", -1);
 	if (offset == -1) {
 		debug("%s: Invalid register offset %d\n", __func__, offset);
-- 
1.8.2.1

[U-Boot] [PATCH 13/23] x86: Drop asm/arch/gpio.h

[Bin Meng]

asm/arch/gpio.h is not needed anymore as we get the GPIO base from
PCH driver.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

 arch/x86/include/asm/arch-baytrail/gpio.h  | 13 -------------
 arch/x86/include/asm/arch-coreboot/gpio.h  | 13 -------------
 arch/x86/include/asm/arch-efi/gpio.h       | 10 ----------
 arch/x86/include/asm/arch-ivybridge/gpio.h | 13 -------------
 arch/x86/include/asm/arch-qemu/gpio.h      | 13 -------------
 arch/x86/include/asm/arch-quark/gpio.h     | 13 -------------
 arch/x86/include/asm/arch-queensbay/gpio.h | 13 -------------
 arch/x86/include/asm/gpio.h                |  1 -
 board/intel/galileo/galileo.c              |  5 ++---
 9 files changed, 2 insertions(+), 92 deletions(-)
 delete mode 100644 arch/x86/include/asm/arch-baytrail/gpio.h
 delete mode 100644 arch/x86/include/asm/arch-coreboot/gpio.h
 delete mode 100644 arch/x86/include/asm/arch-efi/gpio.h
 delete mode 100644 arch/x86/include/asm/arch-ivybridge/gpio.h
 delete mode 100644 arch/x86/include/asm/arch-qemu/gpio.h
 delete mode 100644 arch/x86/include/asm/arch-quark/gpio.h
 delete mode 100644 arch/x86/include/asm/arch-queensbay/gpio.h

diff --git a/arch/x86/include/asm/arch-baytrail/gpio.h b/arch/x86/include/asm/arch-baytrail/gpio.h
deleted file mode 100644
index 4e8987c..0000000
--- a/arch/x86/include/asm/arch-baytrail/gpio.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _X86_ARCH_GPIO_H_
-#define _X86_ARCH_GPIO_H_
-
-/* Where in config space is the register that points to the GPIO registers? */
-#define PCI_CFG_GPIOBASE 0x48
-
-#endif /* _X86_ARCH_GPIO_H_ */
diff --git a/arch/x86/include/asm/arch-coreboot/gpio.h b/arch/x86/include/asm/arch-coreboot/gpio.h
deleted file mode 100644
index 31edef9..0000000
--- a/arch/x86/include/asm/arch-coreboot/gpio.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * Copyright (c) 2014, Google Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _X86_ARCH_GPIO_H_
-#define _X86_ARCH_GPIO_H_
-
-/* Where in config space is the register that points to the GPIO registers? */
-#define PCI_CFG_GPIOBASE 0x48
-
-#endif /* _X86_ARCH_GPIO_H_ */
diff --git a/arch/x86/include/asm/arch-efi/gpio.h b/arch/x86/include/asm/arch-efi/gpio.h
deleted file mode 100644
index f044f07..0000000
--- a/arch/x86/include/asm/arch-efi/gpio.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/*
- * Copyright (c) 2015 Google, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _X86_ARCH_GPIO_H_
-#define _X86_ARCH_GPIO_H_
-
-#endif /* _X86_ARCH_GPIO_H_ */
diff --git a/arch/x86/include/asm/arch-ivybridge/gpio.h b/arch/x86/include/asm/arch-ivybridge/gpio.h
deleted file mode 100644
index 31edef9..0000000
--- a/arch/x86/include/asm/arch-ivybridge/gpio.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * Copyright (c) 2014, Google Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _X86_ARCH_GPIO_H_
-#define _X86_ARCH_GPIO_H_
-
-/* Where in config space is the register that points to the GPIO registers? */
-#define PCI_CFG_GPIOBASE 0x48
-
-#endif /* _X86_ARCH_GPIO_H_ */
diff --git a/arch/x86/include/asm/arch-qemu/gpio.h b/arch/x86/include/asm/arch-qemu/gpio.h
deleted file mode 100644
index ca8cba4..0000000
--- a/arch/x86/include/asm/arch-qemu/gpio.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _X86_ARCH_GPIO_H_
-#define _X86_ARCH_GPIO_H_
-
-/* Where in config space is the register that points to the GPIO registers? */
-#define PCI_CFG_GPIOBASE 0x44
-
-#endif /* _X86_ARCH_GPIO_H_ */
diff --git a/arch/x86/include/asm/arch-quark/gpio.h b/arch/x86/include/asm/arch-quark/gpio.h
deleted file mode 100644
index ca8cba4..0000000
--- a/arch/x86/include/asm/arch-quark/gpio.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _X86_ARCH_GPIO_H_
-#define _X86_ARCH_GPIO_H_
-
-/* Where in config space is the register that points to the GPIO registers? */
-#define PCI_CFG_GPIOBASE 0x44
-
-#endif /* _X86_ARCH_GPIO_H_ */
diff --git a/arch/x86/include/asm/arch-queensbay/gpio.h b/arch/x86/include/asm/arch-queensbay/gpio.h
deleted file mode 100644
index ab4e059..0000000
--- a/arch/x86/include/asm/arch-queensbay/gpio.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _X86_ARCH_GPIO_H_
-#define _X86_ARCH_GPIO_H_
-
-/* Where in config space is the register that points to the GPIO registers? */
-#define PCI_CFG_GPIOBASE 0x44
-
-#endif /* _X86_ARCH_GPIO_H_ */
diff --git a/arch/x86/include/asm/gpio.h b/arch/x86/include/asm/gpio.h
index ed85b08..403851b 100644
--- a/arch/x86/include/asm/gpio.h
+++ b/arch/x86/include/asm/gpio.h
@@ -7,7 +7,6 @@
 #define _X86_GPIO_H_
 
 #include <linux/compiler.h>
-#include <asm/arch/gpio.h>
 #include <asm-generic/gpio.h>
 
 struct ich6_bank_platdata {
diff --git a/board/intel/galileo/galileo.c b/board/intel/galileo/galileo.c
index c1087ac..212c970 100644
--- a/board/intel/galileo/galileo.c
+++ b/board/intel/galileo/galileo.c
@@ -7,7 +7,6 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/device.h>
-#include <asm/arch/gpio.h>
 #include <asm/arch/quark.h>
 
 int board_early_init_f(void)
@@ -30,7 +29,7 @@ void board_assert_perst(void)
 	u32 base, port, val;
 
 	/* retrieve the GPIO IO base */
-	qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, PCI_CFG_GPIOBASE, &base);
+	qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, LB_GBA, &base);
 	base = (base & 0xffff) & ~0x7f;
 
 	/* enable the pin */
@@ -57,7 +56,7 @@ void board_deassert_perst(void)
 	u32 base, port, val;
 
 	/* retrieve the GPIO IO base */
-	qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, PCI_CFG_GPIOBASE, &base);
+	qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, LB_GBA, &base);
 	base = (base & 0xffff) & ~0x7f;
 
 	/* pull it up (de-assert) */
-- 
1.8.2.1

[U-Boot] [PATCH 14/23] x86: minnowmax: Drop io-base property in the pch_pinctrl node

[Bin Meng]

IOBASE is now obtained from PCH driver, drop this <io-base> property.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

 arch/x86/dts/minnowmax.dts | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
index b7e3ba4..60bd05a 100644
--- a/arch/x86/dts/minnowmax.dts
+++ b/arch/x86/dts/minnowmax.dts
@@ -29,7 +29,6 @@
 
 	pch_pinctrl {
 		compatible = "intel,x86-pinctrl";
-		io-base = <0x4c>;
 
 		/* GPIO E0 */
 		soc_gpio_s5_0 at 0 {
-- 
1.8.2.1

[U-Boot] [PATCH 15/23] x86: irq: Get irq_router's bdf via dm_pci_get_bdf()

[Bin Meng]

There is no need to parse PCH's <reg> property as we have already
a DM PCI API dm_pci_get_bdf() that can handle this.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

 arch/x86/cpu/irq.c | 9 +--------
 1 file changed, 1 insertion(+), 8 deletions(-)

diff --git a/arch/x86/cpu/irq.c b/arch/x86/cpu/irq.c
index 0b36ace..cc0297f 100644
--- a/arch/x86/cpu/irq.c
+++ b/arch/x86/cpu/irq.c
@@ -86,26 +86,19 @@ static inline void fill_irq_info(struct irq_info *slot, int bus, int device,
 static int create_pirq_routing_table(struct udevice *dev)
 {
 	const void *blob = gd->fdt_blob;
-	struct fdt_pci_addr addr;
 	int node;
 	int len, count;
 	const u32 *cell;
 	struct irq_routing_table *rt;
 	struct irq_info *slot, *slot_base;
 	int irq_entries = 0;
-	int parent;
 	int i;
 	int ret;
 
 	node = dev->of_offset;
-	parent = dev->parent->of_offset;
-	ret = fdtdec_get_pci_addr(blob, parent, FDT_PCI_SPACE_CONFIG,
-				  "reg", &addr);
-	if (ret)
-		return ret;
 
 	/* extract the bdf from fdt_pci_addr */
-	irq_router.bdf = addr.phys_hi & 0xffff00;
+	irq_router.bdf = dm_pci_get_bdf(dev->parent);
 
 	ret = fdt_find_string(blob, node, "intel,pirq-config", "pci");
 	if (!ret) {
-- 
1.8.2.1

[U-Boot] [PATCH 16/23] x86: irq: Move irq_router to a per driver priv

[Bin Meng]

At present irq_router is declared as a static struct irq_router in
arch/x86/cpu/irq.c. Since it's a driver control block, it makes sense
to move it to a per driver priv. Adjust existing APIs to accept an
additional parameter of irq_router's udevice.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

 arch/x86/cpu/irq.c                  | 73 +++++++++++++++++++------------------
 arch/x86/include/asm/pirq_routing.h | 12 ++++--
 arch/x86/lib/pirq_routing.c         | 12 +++---
 3 files changed, 51 insertions(+), 46 deletions(-)

diff --git a/arch/x86/cpu/irq.c b/arch/x86/cpu/irq.c
index cc0297f..fea6f65 100644
--- a/arch/x86/cpu/irq.c
+++ b/arch/x86/cpu/irq.c
@@ -16,19 +16,18 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static struct irq_router irq_router;
 static struct irq_routing_table *pirq_routing_table;
 
-bool pirq_check_irq_routed(int link, u8 irq)
+bool pirq_check_irq_routed(struct udevice *dev, int link, u8 irq)
 {
+	struct irq_router *priv = dev_get_priv(dev);
 	u8 pirq;
-	int base = irq_router.link_base;
+	int base = priv->link_base;
 
-	if (irq_router.config == PIRQ_VIA_PCI)
-		pirq = x86_pci_read_config8(irq_router.bdf,
-					    LINK_N2V(link, base));
+	if (priv->config == PIRQ_VIA_PCI)
+		pirq = x86_pci_read_config8(priv->bdf, LINK_N2V(link, base));
 	else
-		pirq = readb(irq_router.ibase + LINK_N2V(link, base));
+		pirq = readb(priv->ibase + LINK_N2V(link, base));
 
 	pirq &= 0xf;
 
@@ -39,24 +38,26 @@ bool pirq_check_irq_routed(int link, u8 irq)
 	return pirq == irq ? true : false;
 }
 
-int pirq_translate_link(int link)
+int pirq_translate_link(struct udevice *dev, int link)
 {
-	return LINK_V2N(link, irq_router.link_base);
+	struct irq_router *priv = dev_get_priv(dev);
+
+	return LINK_V2N(link, priv->link_base);
 }
 
-void pirq_assign_irq(int link, u8 irq)
+void pirq_assign_irq(struct udevice *dev, int link, u8 irq)
 {
-	int base = irq_router.link_base;
+	struct irq_router *priv = dev_get_priv(dev);
+	int base = priv->link_base;
 
 	/* IRQ# 0/1/2/8/13 are reserved */
 	if (irq < 3 || irq == 8 || irq == 13)
 		return;
 
-	if (irq_router.config == PIRQ_VIA_PCI)
-		x86_pci_write_config8(irq_router.bdf,
-				      LINK_N2V(link, base), irq);
+	if (priv->config == PIRQ_VIA_PCI)
+		x86_pci_write_config8(priv->bdf, LINK_N2V(link, base), irq);
 	else
-		writeb(irq, irq_router.ibase + LINK_N2V(link, base));
+		writeb(irq, priv->ibase + LINK_N2V(link, base));
 }
 
 static struct irq_info *check_dup_entry(struct irq_info *slot_base,
@@ -74,17 +75,18 @@ static struct irq_info *check_dup_entry(struct irq_info *slot_base,
 	return (i == entry_num) ? NULL : slot;
 }
 
-static inline void fill_irq_info(struct irq_info *slot, int bus, int device,
-				 int pin, int pirq)
+static inline void fill_irq_info(struct irq_router *priv, struct irq_info *slot,
+				 int bus, int device, int pin, int pirq)
 {
 	slot->bus = bus;
 	slot->devfn = (device << 3) | 0;
-	slot->irq[pin - 1].link = LINK_N2V(pirq, irq_router.link_base);
-	slot->irq[pin - 1].bitmap = irq_router.irq_mask;
+	slot->irq[pin - 1].link = LINK_N2V(pirq, priv->link_base);
+	slot->irq[pin - 1].bitmap = priv->irq_mask;
 }
 
 static int create_pirq_routing_table(struct udevice *dev)
 {
+	struct irq_router *priv = dev_get_priv(dev);
 	const void *blob = gd->fdt_blob;
 	int node;
 	int len, count;
@@ -98,15 +100,15 @@ static int create_pirq_routing_table(struct udevice *dev)
 	node = dev->of_offset;
 
 	/* extract the bdf from fdt_pci_addr */
-	irq_router.bdf = dm_pci_get_bdf(dev->parent);
+	priv->bdf = dm_pci_get_bdf(dev->parent);
 
 	ret = fdt_find_string(blob, node, "intel,pirq-config", "pci");
 	if (!ret) {
-		irq_router.config = PIRQ_VIA_PCI;
+		priv->config = PIRQ_VIA_PCI;
 	} else {
 		ret = fdt_find_string(blob, node, "intel,pirq-config", "ibase");
 		if (!ret)
-			irq_router.config = PIRQ_VIA_IBASE;
+			priv->config = PIRQ_VIA_IBASE;
 		else
 			return -EINVAL;
 	}
@@ -114,12 +116,12 @@ static int create_pirq_routing_table(struct udevice *dev)
 	ret = fdtdec_get_int(blob, node, "intel,pirq-link", -1);
 	if (ret == -1)
 		return ret;
-	irq_router.link_base = ret;
+	priv->link_base = ret;
 
-	irq_router.irq_mask = fdtdec_get_int(blob, node,
-					     "intel,pirq-mask", PIRQ_BITMAP);
+	priv->irq_mask = fdtdec_get_int(blob, node,
+					"intel,pirq-mask", PIRQ_BITMAP);
 
-	if (irq_router.config == PIRQ_VIA_IBASE) {
+	if (priv->config == PIRQ_VIA_IBASE) {
 		int ibase_off;
 
 		ibase_off = fdtdec_get_int(blob, node, "intel,ibase-offset", 0);
@@ -136,9 +138,8 @@ static int create_pirq_routing_table(struct udevice *dev)
 		 *   2) memory range decoding is enabled.
 		 * Hence we don't do any santify test here.
 		 */
-		irq_router.ibase = x86_pci_read_config32(irq_router.bdf,
-							 ibase_off);
-		irq_router.ibase &= ~0xf;
+		priv->ibase = x86_pci_read_config32(priv->bdf, ibase_off);
+		priv->ibase &= ~0xf;
 	}
 
 	cell = fdt_getprop(blob, node, "intel,pirq-routing", &len);
@@ -153,9 +154,8 @@ static int create_pirq_routing_table(struct udevice *dev)
 	/* Populate the PIRQ table fields */
 	rt->signature = PIRQ_SIGNATURE;
 	rt->version = PIRQ_VERSION;
-	rt->rtr_bus = PCI_BUS(irq_router.bdf);
-	rt->rtr_devfn = (PCI_DEV(irq_router.bdf) << 3) |
-			PCI_FUNC(irq_router.bdf);
+	rt->rtr_bus = PCI_BUS(priv->bdf);
+	rt->rtr_devfn = (PCI_DEV(priv->bdf) << 3) | PCI_FUNC(priv->bdf);
 	rt->rtr_vendor = PCI_VENDOR_ID_INTEL;
 	rt->rtr_device = PCI_DEVICE_ID_INTEL_ICH7_31;
 
@@ -192,7 +192,7 @@ static int create_pirq_routing_table(struct udevice *dev)
 				 * routing information in the device tree.
 				 */
 				if (slot->irq[pr.pin - 1].link !=
-					LINK_N2V(pr.pirq, irq_router.link_base))
+					LINK_N2V(pr.pirq, priv->link_base))
 					debug("WARNING: Inconsistent PIRQ routing information\n");
 				continue;
 			}
@@ -200,8 +200,8 @@ static int create_pirq_routing_table(struct udevice *dev)
 			slot = slot_base + irq_entries++;
 		}
 		debug("writing INT%c\n", 'A' + pr.pin - 1);
-		fill_irq_info(slot, PCI_BUS(pr.bdf), PCI_DEV(pr.bdf), pr.pin,
-			      pr.pirq);
+		fill_irq_info(priv, slot, PCI_BUS(pr.bdf), PCI_DEV(pr.bdf),
+			      pr.pin, pr.pirq);
 	}
 
 	rt->size = irq_entries * sizeof(struct irq_info) + 32;
@@ -221,7 +221,7 @@ int irq_router_common_init(struct udevice *dev)
 		return ret;
 	}
 	/* Route PIRQ */
-	pirq_route_irqs(pirq_routing_table->slots,
+	pirq_route_irqs(dev, pirq_routing_table->slots,
 			get_irq_slot_count(pirq_routing_table));
 
 	return 0;
@@ -250,6 +250,7 @@ U_BOOT_DRIVER(irq_router_drv) = {
 	.id		= UCLASS_IRQ,
 	.of_match	= irq_router_ids,
 	.probe		= irq_router_probe,
+	.priv_auto_alloc_size = sizeof(struct irq_router),
 };
 
 UCLASS_DRIVER(irq) = {
diff --git a/arch/x86/include/asm/pirq_routing.h b/arch/x86/include/asm/pirq_routing.h
index ddc08e1..0afcb46 100644
--- a/arch/x86/include/asm/pirq_routing.h
+++ b/arch/x86/include/asm/pirq_routing.h
@@ -72,12 +72,13 @@ static inline int get_irq_slot_count(struct irq_routing_table *rt)
  * Note: this function should be provided by the platform codes, as the
  * implementation of interrupt router may be different.
  *
+ * @dev:	irq router's udevice
  * @link:	link number which represents a PIRQ
  * @irq:	the 8259 IRQ number
  * @return:	true if the irq is already routed to 8259 for a given link,
  *		false elsewise
  */
-bool pirq_check_irq_routed(int link, u8 irq);
+bool pirq_check_irq_routed(struct udevice *dev, int link, u8 irq);
 
 /**
  * pirq_translate_link() - Translate a link value
@@ -89,10 +90,11 @@ bool pirq_check_irq_routed(int link, u8 irq);
  * Note: this function should be provided by the platform codes, as the
  * implementation of interrupt router may be different.
  *
+ * @dev:	irq router's udevice
  * @link:	platform-specific link value
  * @return:	link number which represents a PIRQ
  */
-int pirq_translate_link(int link);
+int pirq_translate_link(struct udevice *dev, int link);
 
 /**
  * pirq_assign_irq() - Assign an IRQ to a PIRQ link
@@ -103,10 +105,11 @@ int pirq_translate_link(int link);
  * Note: this function should be provided by the platform codes, as the
  * implementation of interrupt router may be different.
  *
+ * @dev:	irq router's udevice
  * @link:	link number which represents a PIRQ
  * @irq:	IRQ to which the PIRQ is routed
  */
-void pirq_assign_irq(int link, u8 irq);
+void pirq_assign_irq(struct udevice *dev, int link, u8 irq);
 
 /**
  * pirq_route_irqs() - Route PIRQs to 8259 PIC
@@ -117,10 +120,11 @@ void pirq_assign_irq(int link, u8 irq);
  * The configuration source is taken from a struct irq_info table, the format
  * of which is defined in PIRQ routing table spec and PCI BIOS spec.
  *
+ * @dev:	irq router's udevice
  * @irq:	pointer to the base address of the struct irq_info
  * @num:	number of entries in the struct irq_info
  */
-void pirq_route_irqs(struct irq_info *irq, int num);
+void pirq_route_irqs(struct udevice *dev, struct irq_info *irq, int num);
 
 /**
  * copy_pirq_routing_table() - Copy a PIRQ routing table
diff --git a/arch/x86/lib/pirq_routing.c b/arch/x86/lib/pirq_routing.c
index ba41169..3cc6adb 100644
--- a/arch/x86/lib/pirq_routing.c
+++ b/arch/x86/lib/pirq_routing.c
@@ -14,7 +14,7 @@
 
 static bool irq_already_routed[16];
 
-static u8 pirq_get_next_free_irq(u8 *pirq, u16 bitmap)
+static u8 pirq_get_next_free_irq(struct udevice *dev, u8 *pirq, u16 bitmap)
 {
 	int i, link;
 	u8 irq = 0;
@@ -33,7 +33,7 @@ static u8 pirq_get_next_free_irq(u8 *pirq, u16 bitmap)
 			continue;
 
 		for (link = 0; link < CONFIG_MAX_PIRQ_LINKS; link++) {
-			if (pirq_check_irq_routed(link, irq)) {
+			if (pirq_check_irq_routed(dev, link, irq)) {
 				irq_already_routed[irq] = true;
 				break;
 			}
@@ -52,7 +52,7 @@ static u8 pirq_get_next_free_irq(u8 *pirq, u16 bitmap)
 	return irq;
 }
 
-void pirq_route_irqs(struct irq_info *irq, int num)
+void pirq_route_irqs(struct udevice *dev, struct irq_info *irq, int num)
 {
 	unsigned char irq_slot[MAX_INTX_ENTRIES];
 	unsigned char pirq[CONFIG_MAX_PIRQ_LINKS];
@@ -80,11 +80,11 @@ void pirq_route_irqs(struct irq_info *irq, int num)
 			}
 
 			/* translate link value to link number */
-			link = pirq_translate_link(link);
+			link = pirq_translate_link(dev, link);
 
 			/* yet not routed */
 			if (!pirq[link]) {
-				irq = pirq_get_next_free_irq(pirq, bitmap);
+				irq = pirq_get_next_free_irq(dev, pirq, bitmap);
 				pirq[link] = irq;
 			} else {
 				irq = pirq[link];
@@ -94,7 +94,7 @@ void pirq_route_irqs(struct irq_info *irq, int num)
 			irq_slot[intx] = irq;
 
 			/* Assign IRQ in the interrupt router */
-			pirq_assign_irq(link, irq);
+			pirq_assign_irq(dev, link, irq);
 		}
 
 		/* Bus, device, slots IRQs for {A,B,C,D} */
-- 
1.8.2.1

[U-Boot] [PATCH 17/23] x86: irq: Convert to use DM PCI API

[Bin Meng]

Now that we have irq router's udevice passed as a parameter, it's
time to start using the DM PCI API instead of those legacy ones.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

 arch/x86/cpu/irq.c           | 6 +++---
 arch/x86/cpu/queensbay/irq.c | 2 +-
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/x86/cpu/irq.c b/arch/x86/cpu/irq.c
index fea6f65..2950783 100644
--- a/arch/x86/cpu/irq.c
+++ b/arch/x86/cpu/irq.c
@@ -25,7 +25,7 @@ bool pirq_check_irq_routed(struct udevice *dev, int link, u8 irq)
 	int base = priv->link_base;
 
 	if (priv->config == PIRQ_VIA_PCI)
-		pirq = x86_pci_read_config8(priv->bdf, LINK_N2V(link, base));
+		dm_pci_read_config8(dev->parent, LINK_N2V(link, base), &pirq);
 	else
 		pirq = readb(priv->ibase + LINK_N2V(link, base));
 
@@ -55,7 +55,7 @@ void pirq_assign_irq(struct udevice *dev, int link, u8 irq)
 		return;
 
 	if (priv->config == PIRQ_VIA_PCI)
-		x86_pci_write_config8(priv->bdf, LINK_N2V(link, base), irq);
+		dm_pci_write_config8(dev->parent, LINK_N2V(link, base), irq);
 	else
 		writeb(irq, priv->ibase + LINK_N2V(link, base));
 }
@@ -138,7 +138,7 @@ static int create_pirq_routing_table(struct udevice *dev)
 		 *   2) memory range decoding is enabled.
 		 * Hence we don't do any santify test here.
 		 */
-		priv->ibase = x86_pci_read_config32(priv->bdf, ibase_off);
+		dm_pci_read_config32(dev->parent, ibase_off, &priv->ibase);
 		priv->ibase &= ~0xf;
 	}
 
diff --git a/arch/x86/cpu/queensbay/irq.c b/arch/x86/cpu/queensbay/irq.c
index 44369f7..63d0f35 100644
--- a/arch/x86/cpu/queensbay/irq.c
+++ b/arch/x86/cpu/queensbay/irq.c
@@ -18,7 +18,7 @@ int queensbay_irq_router_probe(struct udevice *dev)
 	struct tnc_rcba *rcba;
 	u32 base;
 
-	base = x86_pci_read_config32(TNC_LPC, LPC_RCBA);
+	dm_pci_read_config32(dev->parent, LPC_RCBA, &base);
 	base &= ~MEM_BAR_EN;
 	rcba = (struct tnc_rcba *)base;
 
-- 
1.8.2.1

[U-Boot] [PATCH 18/23] x86: tnc: Change disable_igd() to have a return value

[Bin Meng]

So far disable_igd() does not have any return value, but we may need
that in the future.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

 arch/x86/cpu/queensbay/tnc.c | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/arch/x86/cpu/queensbay/tnc.c b/arch/x86/cpu/queensbay/tnc.c
index f9fddc1..8b79505 100644
--- a/arch/x86/cpu/queensbay/tnc.c
+++ b/arch/x86/cpu/queensbay/tnc.c
@@ -14,7 +14,7 @@
 #include <asm/fsp/fsp_support.h>
 #include <asm/processor.h>
 
-static void __maybe_unused disable_igd(void)
+static int __maybe_unused disable_igd(void)
 {
 	/*
 	 * According to Atom E6xx datasheet, setting VGA Disable (bit17)
@@ -36,6 +36,8 @@ static void __maybe_unused disable_igd(void)
 	 */
 	x86_pci_write_config32(TNC_IGD, IGD_FD, FUNC_DISABLE);
 	x86_pci_write_config32(TNC_SDVO, IGD_FD, FUNC_DISABLE);
+
+	return 0;
 }
 
 int arch_cpu_init(void)
@@ -53,9 +55,11 @@ int arch_cpu_init(void)
 
 int arch_early_init_r(void)
 {
+	int ret = 0;
+
 #ifdef CONFIG_DISABLE_IGD
-	disable_igd();
+	ret = disable_igd();
 #endif
 
-	return 0;
+	return ret;
 }
-- 
1.8.2.1

[U-Boot] [PATCH 19/23] x86: tnc: Use DM PCI API in disable_igd()

[Bin Meng]

Once we get udevice of IGD and SDVO, we can use its udevice to
access PCI configuration space with dm_pci_write_config32().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

 arch/x86/cpu/queensbay/tnc.c | 22 +++++++++++++++++++---
 1 file changed, 19 insertions(+), 3 deletions(-)

diff --git a/arch/x86/cpu/queensbay/tnc.c b/arch/x86/cpu/queensbay/tnc.c
index 8b79505..38082c4 100644
--- a/arch/x86/cpu/queensbay/tnc.c
+++ b/arch/x86/cpu/queensbay/tnc.c
@@ -5,9 +5,10 @@
  */
 
 #include <common.h>
+#include <dm.h>
+#include <pci.h>
 #include <asm/io.h>
 #include <asm/irq.h>
-#include <asm/pci.h>
 #include <asm/post.h>
 #include <asm/arch/device.h>
 #include <asm/arch/tnc.h>
@@ -16,6 +17,21 @@
 
 static int __maybe_unused disable_igd(void)
 {
+	struct udevice *igd, *sdvo;
+	int ret;
+
+	ret = dm_pci_bus_find_bdf(TNC_IGD, &igd);
+	if (ret)
+		return ret;
+	if (!igd)
+		return 0;
+
+	ret = dm_pci_bus_find_bdf(TNC_SDVO, &sdvo);
+	if (ret)
+		return ret;
+	if (!sdvo)
+		return 0;
+
 	/*
 	 * According to Atom E6xx datasheet, setting VGA Disable (bit17)
 	 * of Graphics Controller register (offset 0x50) prevents IGD
@@ -34,8 +50,8 @@ static int __maybe_unused disable_igd(void)
 	 * two devices will be completely disabled (invisible in the PCI
 	 * configuration space) unless a system reset is performed.
 	 */
-	x86_pci_write_config32(TNC_IGD, IGD_FD, FUNC_DISABLE);
-	x86_pci_write_config32(TNC_SDVO, IGD_FD, FUNC_DISABLE);
+	dm_pci_write_config32(igd, IGD_FD, FUNC_DISABLE);
+	dm_pci_write_config32(sdvo, IGD_FD, FUNC_DISABLE);
 
 	return 0;
 }
-- 
1.8.2.1

[U-Boot] [PATCH 20/23] x86: tnc: Remove IGD and SDVO devices from driver model

[Bin Meng]

With recent DM PCI changes to vesa_fb driver, external graphics
card does not work any more. This is because: after setting the
function disable bit, IGD and SDVO devices will disappear in the
PCI configuration space. This however creates an inconsistent state
from a driver model PCI controller point of view, as these two PCI
devices are still attached to its parent's child device list as
maintained by the driver model. Some driver model PCI APIs like
dm_pci_find_class() used in the vesa_fb driver, are referring to
the list to speed up the finding process instead of re-enumerating
the whole PCI bus, so it gets the stale cached data which is wrong.

To fix this, manually remove these two devices.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

 arch/x86/cpu/queensbay/tnc.c | 36 ++++++++++++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)

diff --git a/arch/x86/cpu/queensbay/tnc.c b/arch/x86/cpu/queensbay/tnc.c
index 38082c4..b226e4c 100644
--- a/arch/x86/cpu/queensbay/tnc.c
+++ b/arch/x86/cpu/queensbay/tnc.c
@@ -6,6 +6,7 @@
 
 #include <common.h>
 #include <dm.h>
+#include <dm/device-internal.h>
 #include <pci.h>
 #include <asm/io.h>
 #include <asm/irq.h>
@@ -53,6 +54,41 @@ static int __maybe_unused disable_igd(void)
 	dm_pci_write_config32(igd, IGD_FD, FUNC_DISABLE);
 	dm_pci_write_config32(sdvo, IGD_FD, FUNC_DISABLE);
 
+	/*
+	 * After setting the function disable bit, IGD and SDVO devices will
+	 * disappear in the PCI configuration space. This however creates an
+	 * inconsistent state from a driver model PCI controller point of view,
+	 * as these two PCI devices are still attached to its parent's child
+	 * device list as maintained by the driver model. Some driver model PCI
+	 * APIs like dm_pci_find_class(), are referring to the list to speed up
+	 * the finding process instead of re-enumerating the whole PCI bus, so
+	 * it gets the stale cached data which is wrong.
+	 *
+	 * Note x86 PCI enueration normally happens twice, in pre-relocation
+	 * phase and post-relocation. One option might be to call disable_igd()
+	 * in one of the pre-relocation initialization hooks so that it gets
+	 * disabled in the first round, and when it comes to the second round
+	 * driver model PCI will construct a correct list. Unfortunately this
+	 * does not work as Intel FSP is used on this platform to perform low
+	 * level initialization, and fsp_init_phase_pci() is called only once
+	 * in the post-relocation phase. If we disable IGD and SDVO devices,
+	 * fsp_init_phase_pci() simply hangs and never returns.
+	 *
+	 * So the only option we have is to manually remove these two devices.
+	 */
+	ret = device_remove(igd);
+	if (ret)
+		return ret;
+	ret = device_unbind(igd);
+	if (ret)
+		return ret;
+	ret = device_remove(sdvo);
+	if (ret)
+		return ret;
+	ret = device_unbind(sdvo);
+	if (ret)
+		return ret;
+
 	return 0;
 }
 
-- 
1.8.2.1

[U-Boot] [PATCH 21/23] x86: qemu: Convert to use DM PCI API

[Bin Meng]

Use pci_[read|write]_config intead of x86_pci_[read|write]_config.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

 arch/x86/cpu/qemu/qemu.c | 34 +++++++++++++++++-----------------
 1 file changed, 17 insertions(+), 17 deletions(-)

diff --git a/arch/x86/cpu/qemu/qemu.c b/arch/x86/cpu/qemu/qemu.c
index f8af566..7ad0ee4 100644
--- a/arch/x86/cpu/qemu/qemu.c
+++ b/arch/x86/cpu/qemu/qemu.c
@@ -5,8 +5,8 @@
  */
 
 #include <common.h>
+#include <pci.h>
 #include <asm/irq.h>
-#include <asm/pci.h>
 #include <asm/post.h>
 #include <asm/processor.h>
 #include <asm/arch/device.h>
@@ -21,23 +21,23 @@ static void enable_pm_piix(void)
 	u16 cmd;
 
 	/* Set the PM I/O base */
-	x86_pci_write_config32(PIIX_PM, PMBA, CONFIG_ACPI_PM1_BASE | 1);
+	pci_write_config32(PIIX_PM, PMBA, CONFIG_ACPI_PM1_BASE | 1);
 
 	/* Enable access to the PM I/O space */
-	cmd = x86_pci_read_config16(PIIX_PM, PCI_COMMAND);
+	pci_read_config16(PIIX_PM, PCI_COMMAND, &cmd);
 	cmd |= PCI_COMMAND_IO;
-	x86_pci_write_config16(PIIX_PM, PCI_COMMAND, cmd);
+	pci_write_config16(PIIX_PM, PCI_COMMAND, cmd);
 
 	/* PM I/O Space Enable (PMIOSE) */
-	en = x86_pci_read_config8(PIIX_PM, PMREGMISC);
+	pci_read_config8(PIIX_PM, PMREGMISC, &en);
 	en |= PMIOSE;
-	x86_pci_write_config8(PIIX_PM, PMREGMISC, en);
+	pci_write_config8(PIIX_PM, PMREGMISC, en);
 }
 
 static void enable_pm_ich9(void)
 {
 	/* Set the PM I/O base */
-	x86_pci_write_config32(ICH9_PM, PMBA, CONFIG_ACPI_PM1_BASE | 1);
+	pci_write_config32(ICH9_PM, PMBA, CONFIG_ACPI_PM1_BASE | 1);
 }
 
 static void qemu_chipset_init(void)
@@ -50,7 +50,7 @@ static void qemu_chipset_init(void)
 	 * the same bitfield layout. Here we determine the offset based on its
 	 * PCI device ID.
 	 */
-	device = x86_pci_read_config16(PCI_BDF(0, 0, 0), PCI_DEVICE_ID);
+	pci_read_config16(PCI_BDF(0, 0, 0), PCI_DEVICE_ID, &device);
 	i440fx = (device == PCI_DEVICE_ID_INTEL_82441);
 	pam = i440fx ? I440FX_PAM : Q35_PAM;
 
@@ -60,7 +60,7 @@ static void qemu_chipset_init(void)
 	 * Configure legacy segments C/D/E/F to system RAM
 	 */
 	for (i = 0; i < PAM_NUM; i++)
-		x86_pci_write_config8(PCI_BDF(0, 0, 0), pam + i, PAM_RW);
+		pci_write_config8(PCI_BDF(0, 0, 0), pam + i, PAM_RW);
 
 	if (i440fx) {
 		/*
@@ -71,19 +71,19 @@ static void qemu_chipset_init(void)
 		 * registers to see whether legacy ports decode is turned on.
 		 * This is to make Linux ata_piix driver happy.
 		 */
-		x86_pci_write_config16(PIIX_IDE, IDE0_TIM, IDE_DECODE_EN);
-		x86_pci_write_config16(PIIX_IDE, IDE1_TIM, IDE_DECODE_EN);
+		pci_write_config16(PIIX_IDE, IDE0_TIM, IDE_DECODE_EN);
+		pci_write_config16(PIIX_IDE, IDE1_TIM, IDE_DECODE_EN);
 
 		/* Enable I/O APIC */
-		xbcs = x86_pci_read_config16(PIIX_ISA, XBCS);
+		pci_read_config16(PIIX_ISA, XBCS, &xbcs);
 		xbcs |= APIC_EN;
-		x86_pci_write_config16(PIIX_ISA, XBCS, xbcs);
+		pci_write_config16(PIIX_ISA, XBCS, xbcs);
 
 		enable_pm_piix();
 	} else {
 		/* Configure PCIe ECAM base address */
-		x86_pci_write_config32(PCI_BDF(0, 0, 0), PCIEX_BAR,
-				       CONFIG_PCIE_ECAM_BASE | BAR_EN);
+		pci_write_config32(PCI_BDF(0, 0, 0), PCIEX_BAR,
+				   CONFIG_PCIE_ECAM_BASE | BAR_EN);
 
 		enable_pm_ich9();
 	}
@@ -136,8 +136,8 @@ int mp_determine_pci_dstirq(int bus, int dev, int func, int pirq)
 		 * connected to I/O APIC INTPIN#16-19. Instead they are routed
 		 * to an irq number controled by the PIRQ routing register.
 		 */
-		irq = x86_pci_read_config8(PCI_BDF(bus, dev, func),
-					   PCI_INTERRUPT_LINE);
+		pci_read_config8(PCI_BDF(bus, dev, func),
+				 PCI_INTERRUPT_LINE, &irq);
 	} else {
 		/*
 		 * ICH9's PIRQ[A-H] are not consecutive numbers from 0 to 7.
-- 
1.8.2.1

[U-Boot] [PATCH 22/23] x86: pci: Use DM PCI APIs in pci_assign_irqs()

[Bin Meng]

Drop legacy PCI APIs usage in pci_assign_irqs() as well.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

 arch/x86/cpu/pci.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/x86/cpu/pci.c b/arch/x86/cpu/pci.c
index 7a31260..9cad57e 100644
--- a/arch/x86/cpu/pci.c
+++ b/arch/x86/cpu/pci.c
@@ -119,11 +119,11 @@ void pci_assign_irqs(int bus, int device, u8 irq[4])
 
 	for (func = 0; func < 8; func++) {
 		bdf = PCI_BDF(bus, device, func);
-		vendor = x86_pci_read_config16(bdf, PCI_VENDOR_ID);
+		pci_read_config16(bdf, PCI_VENDOR_ID, &vendor);
 		if (vendor == 0xffff || vendor == 0x0000)
 			continue;
 
-		pin = x86_pci_read_config8(bdf, PCI_INTERRUPT_PIN);
+		pci_read_config8(bdf, PCI_INTERRUPT_PIN, &pin);
 
 		/* PCI spec says all values except 1..4 are reserved */
 		if ((pin < 1) || (pin > 4))
@@ -136,6 +136,6 @@ void pci_assign_irqs(int bus, int device, u8 irq[4])
 		debug("Assigning IRQ %d to PCI device %d.%x.%d (INT%c)\n",
 		      line, bus, device, func, 'A' + pin - 1);
 
-		x86_pci_write_config8(bdf, PCI_INTERRUPT_LINE, line);
+		pci_write_config8(bdf, PCI_INTERRUPT_LINE, line);
 	}
 }
-- 
1.8.2.1

[U-Boot] [PATCH 23/23] x86: pci: Drop legacy PCI APIs

[Bin Meng]

Now that we have converted all x86 codes to use DM PCI APIs,
drop those legacy ones.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

---

 arch/x86/cpu/pci.c         | 53 ----------------------------------------------
 arch/x86/include/asm/pci.h | 12 -----------
 2 files changed, 65 deletions(-)

diff --git a/arch/x86/cpu/pci.c b/arch/x86/cpu/pci.c
index 9cad57e..c9c7637 100644
--- a/arch/x86/cpu/pci.c
+++ b/arch/x86/cpu/pci.c
@@ -19,59 +19,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static struct pci_controller *get_hose(void)
-{
-	if (gd->hose)
-		return gd->hose;
-
-	return pci_bus_to_hose(0);
-}
-
-unsigned int x86_pci_read_config8(pci_dev_t dev, unsigned where)
-{
-	uint8_t value;
-
-	if (pci_hose_read_config_byte(get_hose(), dev, where, &value))
-		return -1U;
-
-	return value;
-}
-
-unsigned int x86_pci_read_config16(pci_dev_t dev, unsigned where)
-{
-	uint16_t value;
-
-	if (pci_hose_read_config_word(get_hose(), dev, where, &value))
-		return -1U;
-
-	return value;
-}
-
-unsigned int x86_pci_read_config32(pci_dev_t dev, unsigned where)
-{
-	uint32_t value;
-
-	if (pci_hose_read_config_dword(get_hose(), dev, where, &value))
-		return -1U;
-
-	return value;
-}
-
-void x86_pci_write_config8(pci_dev_t dev, unsigned where, unsigned value)
-{
-	pci_hose_write_config_byte(get_hose(), dev, where, value);
-}
-
-void x86_pci_write_config16(pci_dev_t dev, unsigned where, unsigned value)
-{
-	pci_hose_write_config_word(get_hose(), dev, where, value);
-}
-
-void x86_pci_write_config32(pci_dev_t dev, unsigned where, unsigned value)
-{
-	pci_hose_write_config_dword(get_hose(), dev, where, value);
-}
-
 int pci_x86_read_config(struct udevice *bus, pci_dev_t bdf, uint offset,
 			ulong *valuep, enum pci_size_t size)
 {
diff --git a/arch/x86/include/asm/pci.h b/arch/x86/include/asm/pci.h
index a2945f1..46b992e 100644
--- a/arch/x86/include/asm/pci.h
+++ b/arch/x86/include/asm/pci.h
@@ -25,18 +25,6 @@ struct pci_controller;
 
 void pci_setup_type1(struct pci_controller *hose);
 
-/*
- * Simple PCI access routines - these work from either the early PCI hose
- * or the 'real' one, created after U-Boot has memory available
- */
-unsigned int x86_pci_read_config8(pci_dev_t dev, unsigned where);
-unsigned int x86_pci_read_config16(pci_dev_t dev, unsigned where);
-unsigned int x86_pci_read_config32(pci_dev_t dev, unsigned where);
-
-void x86_pci_write_config8(pci_dev_t dev, unsigned where, unsigned value);
-void x86_pci_write_config16(pci_dev_t dev, unsigned where, unsigned value);
-void x86_pci_write_config32(pci_dev_t dev, unsigned where, unsigned value);
-
 int pci_x86_read_config(struct udevice *bus, pci_dev_t bdf, uint offset,
 			ulong *valuep, enum pci_size_t size);
 
-- 
1.8.2.1

[U-Boot] [PATCH 00/23] x86: Convert to use DM PCI APIs completely

[Simon Glass]

Hi Bin,

On 1 February 2016 at 02:40, Bin Meng <bmeng.cn@gmail.com> wrote:
> There are still some codes that use the legacy PCI APIs to access
> the configuration space registers. This series converts those codes
> to completely use DM PCI APIs.
>
> This includes adding several new ops to the PCH uclass driver, and
> some clean up to the SPI/GPIO/IRQ drivers.
>
> Tested on QEMU and Crown Bay. This series is available in pci-working
> branch of u-boot-x86 repo.

Looks great! This is a big step forward.

I've tested it on minnowmax and will test on link in the next day or so.

Here are a few things that I think can still be cleaned up:
- void pci_assign_irqs(int bus, int device, u8 irq[4]) should use a
struct udevice
- pci_x86_read/write_config() move into drivers/pci/pci_x86.c (needs
ivybridge fix which I'll look at)
- disable DM_PCI_COMPAT for x86
- use the PCI mmio access method instead of I/O once it becomes possible
- moving vesa video to driver model (UCLASS_VIDEO)

Regards,
Simon

[U-Boot] [PATCH 01/23] spi: ich: Some clean up

[Simon Glass]

On 1 February 2016 at 02:40, Bin Meng <bmeng.cn@gmail.com> wrote:
>
> This cleans up the ich spi driver a little bit:
> - Remove struct ich_spi_slave that is not referenced anywhere
> - Remove ending period in some comments
> - Move struct ich_spi_platdata and struct ich_spi_priv to ich.h
> - Add #ifndef _ICH_H_ .. in ich.h
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
>  drivers/spi/ich.c | 38 +++++--------------------------------
>  drivers/spi/ich.h | 56 +++++++++++++++++++++++++++++++++++++++++--------------
>  2 files changed, 47 insertions(+), 47 deletions(-)


Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH 02/23] spi: ich: Use compatible strings to distinguish controller version

[Simon Glass]

On 1 February 2016 at 02:40, Bin Meng <bmeng.cn@gmail.com> wrote:
> At present ich spi driver gets the controller version information via
> pch, but this can be simply retrieved via spi node's compatible string.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
>  arch/x86/dts/bayleybay.dts          |  2 +-
>  arch/x86/dts/broadwell_som-6896.dts |  2 +-
>  arch/x86/dts/chromebook_link.dts    |  2 +-
>  arch/x86/dts/chromebox_panther.dts  |  2 +-
>  arch/x86/dts/crownbay.dts           |  2 +-
>  arch/x86/dts/galileo.dts            |  2 +-
>  arch/x86/dts/minnowmax.dts          |  2 +-
>  drivers/spi/ich.c                   | 28 ++++++++++++++++++++++++----
>  8 files changed, 31 insertions(+), 11 deletions(-)

Reviewed-by: Simon Glass <sjg@chromium.org>
Tested on Minnowmax:
Tested-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH 03/23] spi: ich: Change PCHV_ to ICHV_

[Simon Glass]

On 1 February 2016 at 02:40, Bin Meng <bmeng.cn@gmail.com> wrote:
> The ICH SPI controller supports two variants, one of which is ICH7
> compatible and the other is ICH9 compatible. Change 'pch_version'
> to 'ich_version' to better match its original name.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
>  drivers/spi/ich.c | 14 +++++++-------
>  drivers/spi/ich.h |  7 ++++++-
>  2 files changed, 13 insertions(+), 8 deletions(-)

Reviewed-by: Simon Glass <sjg@chromium.org>
Tested on Minnowmax:
Tested-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH 04/23] x86: tnc: Drop unprotect_spi_flash()

[Simon Glass]

On 1 February 2016 at 02:40, Bin Meng <bmeng.cn@gmail.com> wrote:
> Unprotecting SPI flash is now handled in the SPI controller driver,
> via a call to the PCH driver. Drop the ad-hoc version.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
>  arch/x86/cpu/queensbay/tnc.c | 16 ----------------
>  include/configs/crownbay.h   |  1 -
>  2 files changed, 17 deletions(-)

Reviewed-by: Simon Glass <sjg@chromium.org>
Tested on Minnowmax:
Tested-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH 05/23] x86: quark: Drop unprotect_spi_flash()

[Simon Glass]

On 1 February 2016 at 02:40, Bin Meng <bmeng.cn@gmail.com> wrote:
> Unprotecting SPI flash is now handled in the SPI controller driver,
> via a call to the PCH driver. Drop the ad-hoc version.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
>  arch/x86/cpu/quark/quark.c | 17 -----------------
>  1 file changed, 17 deletions(-)

Reviewed-by: Simon Glass <sjg@chromium.org>
Tested on Minnowmax:
Tested-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH 06/23] dm: pch: Remove pch_get_version op

[Simon Glass]

On 1 February 2016 at 02:40, Bin Meng <bmeng.cn@gmail.com> wrote:
> pch_get_version op was only used by the ich spi controller driver,
> and does not really provide a good identification of pch controller
> so far, since we see plenty of Intel PCH chipsets and one differs
> from another a lot, which is not simply either a PCHV_7 or PCHV_9.
> Now that ich spi controller driver was updated to not get such info
> from pch, the pch_get_version op is useless now.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
>  arch/x86/cpu/ivybridge/bd82x6x.c |  6 ------
>  drivers/pch/pch-uclass.c         | 10 ----------
>  drivers/pch/pch7.c               |  6 ------
>  drivers/pch/pch9.c               |  6 ------
>  include/pch.h                    | 20 --------------------
>  5 files changed, 48 deletions(-)

Reviewed-by: Simon Glass <sjg@chromium.org>
Tested on Minnowmax:
Tested-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH 07/23] dm: pch: Rename get_sbase op to get_spi_base

[Simon Glass]

On 1 February 2016 at 02:40, Bin Meng <bmeng.cn@gmail.com> wrote:
> Spell out 'sbase' to 'spi_base' so that it looks clearer.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
>  arch/x86/cpu/ivybridge/bd82x6x.c | 4 ++--
>  drivers/pch/pch-uclass.c         | 6 +++---
>  drivers/pch/pch7.c               | 4 ++--
>  drivers/pch/pch9.c               | 4 ++--
>  drivers/spi/ich.c                | 2 +-
>  include/pch.h                    | 8 ++++----
>  6 files changed, 14 insertions(+), 14 deletions(-)

Reviewed-by: Simon Glass <sjg@chromium.org>
Tested on Minnowmax:
Tested-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH 08/23] dm: pch: Add get_gpio_base op

[Simon Glass]

On 1 February 2016 at 02:40, Bin Meng <bmeng.cn@gmail.com> wrote:
> x86 GPIO registers are accessed via I/O port whose base address is
> configured in a PCI configuration register on the PCH device. Add
> an op get_gpio_base to get the GPIO base address from PCH.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
>  drivers/pch/pch-uclass.c | 11 +++++++++++
>  include/pch.h            | 18 ++++++++++++++++++
>  2 files changed, 29 insertions(+)

Reviewed-by: Simon Glass <sjg@chromium.org>
Tested on Minnowmax:
Tested-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH 09/23] x86: pch: Implement get_gpio_base op

[Simon Glass]

On 1 February 2016 at 02:40, Bin Meng <bmeng.cn@gmail.com> wrote:
> Implement get_gpio_base op for bd82x6x, pch7 and pch9 drivers.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
>  arch/x86/cpu/ivybridge/bd82x6x.c | 33 +++++++++++++++++++++++++++++++++
>  drivers/pch/pch7.c               | 33 +++++++++++++++++++++++++++++++++
>  drivers/pch/pch9.c               | 33 +++++++++++++++++++++++++++++++++
>  3 files changed, 99 insertions(+)

Reviewed-by: Simon Glass <sjg@chromium.org>
Tested on Minnowmax:
Tested-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH 10/23] dm: pch: Add get_io_base op

[Simon Glass]

On 1 February 2016 at 02:40, Bin Meng <bmeng.cn@gmail.com> wrote:
> On some newer chipset (eg: BayTrail), there is an IO base address
> register on the PCH device which configures the base address of a
> memory-mapped I/O controller.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
>  drivers/pch/pch-uclass.c | 11 +++++++++++
>  include/pch.h            | 18 ++++++++++++++++++
>  2 files changed, 29 insertions(+)

Reviewed-by: Simon Glass <sjg@chromium.org>
Tested on Minnowmax:
Tested-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH 11/23] x86: pch9: Implement get_io_base op

[Simon Glass]

On 1 February 2016 at 02:40, Bin Meng <bmeng.cn@gmail.com> wrote:
> IO_BASE is only seen on PCH9 device, implement the get_io_base op.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
>  drivers/pch/pch9.c | 17 +++++++++++++++++
>  1 file changed, 17 insertions(+)

Reviewed-by: Simon Glass <sjg@chromium.org>
Tested on Minnowmax:
Tested-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH 12/23] x86: ich6_gpio: Convert to use proper DM API

[Simon Glass]

On 1 February 2016 at 02:40, Bin Meng <bmeng.cn@gmail.com> wrote:
> At present this GPIO driver still uses the legacy PCI API. Now that
> we have proper PCH drivers we can use those to obtain the information
> we need. While the device tree has nodes for the GPIO peripheral it is
> not in the right place. It should be on the PCI bus as a sub-peripheral
> of the PCH device.
>
> Update the device tree files to show the GPIO controller within the PCH,
> so that PCI access works as expected. This also adds #address-cells and
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
>  arch/x86/dts/bayleybay.dts         |  86 ++++++++++++-------------
>  arch/x86/dts/chromebook_link.dts   |  42 ++++++-------
>  arch/x86/dts/chromebox_panther.dts |  44 ++++++-------
>  arch/x86/dts/crownbay.dts          |  30 ++++-----
>  arch/x86/dts/galileo.dts           |  28 +++++----
>  arch/x86/dts/minnowmax.dts         |  86 ++++++++++++-------------
>  drivers/gpio/intel_ich6_gpio.c     | 125 +++++++------------------------------
>  7 files changed, 186 insertions(+), 255 deletions(-)

Reviewed-by: Simon Glass <sjg@chromium.org>
Tested on Minnowmax:
Tested-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH 13/23] x86: Drop asm/arch/gpio.h

[Simon Glass]

On 1 February 2016 at 02:40, Bin Meng <bmeng.cn@gmail.com> wrote:
> asm/arch/gpio.h is not needed anymore as we get the GPIO base from
> PCH driver.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
>  arch/x86/include/asm/arch-baytrail/gpio.h  | 13 -------------
>  arch/x86/include/asm/arch-coreboot/gpio.h  | 13 -------------
>  arch/x86/include/asm/arch-efi/gpio.h       | 10 ----------
>  arch/x86/include/asm/arch-ivybridge/gpio.h | 13 -------------
>  arch/x86/include/asm/arch-qemu/gpio.h      | 13 -------------
>  arch/x86/include/asm/arch-quark/gpio.h     | 13 -------------
>  arch/x86/include/asm/arch-queensbay/gpio.h | 13 -------------
>  arch/x86/include/asm/gpio.h                |  1 -
>  board/intel/galileo/galileo.c              |  5 ++---
>  9 files changed, 2 insertions(+), 92 deletions(-)
>  delete mode 100644 arch/x86/include/asm/arch-baytrail/gpio.h
>  delete mode 100644 arch/x86/include/asm/arch-coreboot/gpio.h
>  delete mode 100644 arch/x86/include/asm/arch-efi/gpio.h
>  delete mode 100644 arch/x86/include/asm/arch-ivybridge/gpio.h
>  delete mode 100644 arch/x86/include/asm/arch-qemu/gpio.h
>  delete mode 100644 arch/x86/include/asm/arch-quark/gpio.h
>  delete mode 100644 arch/x86/include/asm/arch-queensbay/gpio.h

Reviewed-by: Simon Glass <sjg@chromium.org>
Tested on Minnowmax:
Tested-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH 14/23] x86: minnowmax: Drop io-base property in the pch_pinctrl node

[Simon Glass]

On 1 February 2016 at 02:40, Bin Meng <bmeng.cn@gmail.com> wrote:
> IOBASE is now obtained from PCH driver, drop this <io-base> property.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
>  arch/x86/dts/minnowmax.dts | 1 -
>  1 file changed, 1 deletion(-)

Reviewed-by: Simon Glass <sjg@chromium.org>
Tested on Minnowmax:
Tested-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH 15/23] x86: irq: Get irq_router's bdf via dm_pci_get_bdf()

[Simon Glass]

On 1 February 2016 at 02:40, Bin Meng <bmeng.cn@gmail.com> wrote:
> There is no need to parse PCH's <reg> property as we have already
> a DM PCI API dm_pci_get_bdf() that can handle this.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
>  arch/x86/cpu/irq.c | 9 +--------
>  1 file changed, 1 insertion(+), 8 deletions(-)

Reviewed-by: Simon Glass <sjg@chromium.org>
Tested on Minnowmax:
Tested-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH 16/23] x86: irq: Move irq_router to a per driver priv

[Simon Glass]

On 1 February 2016 at 02:40, Bin Meng <bmeng.cn@gmail.com> wrote:
> At present irq_router is declared as a static struct irq_router in
> arch/x86/cpu/irq.c. Since it's a driver control block, it makes sense
> to move it to a per driver priv. Adjust existing APIs to accept an
> additional parameter of irq_router's udevice.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
>  arch/x86/cpu/irq.c                  | 73 +++++++++++++++++++------------------
>  arch/x86/include/asm/pirq_routing.h | 12 ++++--
>  arch/x86/lib/pirq_routing.c         | 12 +++---
>  3 files changed, 51 insertions(+), 46 deletions(-)

Reviewed-by: Simon Glass <sjg@chromium.org>
Tested on Minnowmax:
Tested-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH 19/23] x86: tnc: Use DM PCI API in disable_igd()

[Simon Glass]

On 1 February 2016 at 02:40, Bin Meng <bmeng.cn@gmail.com> wrote:
> Once we get udevice of IGD and SDVO, we can use its udevice to
> access PCI configuration space with dm_pci_write_config32().
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
>  arch/x86/cpu/queensbay/tnc.c | 22 +++++++++++++++++++---
>  1 file changed, 19 insertions(+), 3 deletions(-)

Reviewed-by: Simon Glass <sjg@chromium.org>
Tested on Minnowmax:
Tested-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH 18/23] x86: tnc: Change disable_igd() to have a return value

[Simon Glass]

On 1 February 2016 at 02:40, Bin Meng <bmeng.cn@gmail.com> wrote:
> So far disable_igd() does not have any return value, but we may need
> that in the future.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
>  arch/x86/cpu/queensbay/tnc.c | 10 +++++++---
>  1 file changed, 7 insertions(+), 3 deletions(-)

Reviewed-by: Simon Glass <sjg@chromium.org>
Tested on Minnowmax:
Tested-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH 17/23] x86: irq: Convert to use DM PCI API

[Simon Glass]

On 1 February 2016 at 02:40, Bin Meng <bmeng.cn@gmail.com> wrote:
> Now that we have irq router's udevice passed as a parameter, it's
> time to start using the DM PCI API instead of those legacy ones.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
>  arch/x86/cpu/irq.c           | 6 +++---
>  arch/x86/cpu/queensbay/irq.c | 2 +-
>  2 files changed, 4 insertions(+), 4 deletions(-)

Reviewed-by: Simon Glass <sjg@chromium.org>
Tested on Minnowmax:
Tested-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH 20/23] x86: tnc: Remove IGD and SDVO devices from driver model

[Simon Glass]

Hi Bin,

On 1 February 2016 at 02:40, Bin Meng <bmeng.cn@gmail.com> wrote:
> With recent DM PCI changes to vesa_fb driver, external graphics
> card does not work any more. This is because: after setting the
> function disable bit, IGD and SDVO devices will disappear in the
> PCI configuration space. This however creates an inconsistent state
> from a driver model PCI controller point of view, as these two PCI
> devices are still attached to its parent's child device list as
> maintained by the driver model. Some driver model PCI APIs like
> dm_pci_find_class() used in the vesa_fb driver, are referring to
> the list to speed up the finding process instead of re-enumerating
> the whole PCI bus, so it gets the stale cached data which is wrong.
>
> To fix this, manually remove these two devices.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
>  arch/x86/cpu/queensbay/tnc.c | 36 ++++++++++++++++++++++++++++++++++++
>  1 file changed, 36 insertions(+)

Reviewed-by: Simon Glass <sjg@chromium.org>
Tested on Minnowmax:
Tested-by: Simon Glass <sjg@chromium.org>

I hope that this can be sorted out when x86 moves to driver model for
video. We should be able to probe the video quite late. I'm not quite
sure how it might work though.

Regards,
Simon

[U-Boot] [PATCH 21/23] x86: qemu: Convert to use DM PCI API

[Simon Glass]

On 1 February 2016 at 02:40, Bin Meng <bmeng.cn@gmail.com> wrote:
> Use pci_[read|write]_config intead of x86_pci_[read|write]_config.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
>  arch/x86/cpu/qemu/qemu.c | 34 +++++++++++++++++-----------------
>  1 file changed, 17 insertions(+), 17 deletions(-)

Reviewed-by: Simon Glass <sjg@chromium.org>
Tested on Minnowmax:
Tested-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH 22/23] x86: pci: Use DM PCI APIs in pci_assign_irqs()

[Simon Glass]

On 1 February 2016 at 02:40, Bin Meng <bmeng.cn@gmail.com> wrote:
> Drop legacy PCI APIs usage in pci_assign_irqs() as well.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
>  arch/x86/cpu/pci.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)

Reviewed-by: Simon Glass <sjg@chromium.org>
Tested on Minnowmax:
Tested-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH 23/23] x86: pci: Drop legacy PCI APIs

[Simon Glass]

On 1 February 2016 at 02:40, Bin Meng <bmeng.cn@gmail.com> wrote:
> Now that we have converted all x86 codes to use DM PCI APIs,
> drop those legacy ones.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>
> ---
>
>  arch/x86/cpu/pci.c         | 53 ----------------------------------------------
>  arch/x86/include/asm/pci.h | 12 -----------
>  2 files changed, 65 deletions(-)

Reviewed-by: Simon Glass <sjg@chromium.org>
Tested on Minnowmax:
Tested-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH 00/23] x86: Convert to use DM PCI APIs completely

[Bin Meng]

Hi Simon,

On Tue, Feb 2, 2016 at 12:19 AM, Simon Glass <sjg@chromium.org> wrote:
> Hi Bin,
>
> On 1 February 2016 at 02:40, Bin Meng <bmeng.cn@gmail.com> wrote:
>> There are still some codes that use the legacy PCI APIs to access
>> the configuration space registers. This series converts those codes
>> to completely use DM PCI APIs.
>>
>> This includes adding several new ops to the PCH uclass driver, and
>> some clean up to the SPI/GPIO/IRQ drivers.
>>
>> Tested on QEMU and Crown Bay. This series is available in pci-working
>> branch of u-boot-x86 repo.
>
> Looks great! This is a big step forward.
>
> I've tested it on minnowmax and will test on link in the next day or so.
>
> Here are a few things that I think can still be cleaned up:
> - void pci_assign_irqs(int bus, int device, u8 irq[4]) should use a
> struct udevice

I guess no, unless we expand struct udevice to include interrupt
routing information? But that's not generic across architectures. I am
not sure how.

> - pci_x86_read/write_config() move into drivers/pci/pci_x86.c (needs
> ivybridge fix which I'll look at)

Yep. I wanted to do this when reviewing one of previous patches.

> - disable DM_PCI_COMPAT for x86

Looks e1000 and pch_gbe (Crown Bay) ethernet drivers are still using
legacy PCI APIs. e1000 might need quite amount of work as it is being
widely used on lots of boards. I can update pch_gbe driver later.

> - use the PCI mmio access method instead of I/O once it becomes possible

Yep.

> - moving vesa video to driver model (UCLASS_VIDEO)

I was not following the dm video changes recently, but I guess yes.

Regards,
Bin

[U-Boot] [PATCH 00/23] x86: Convert to use DM PCI APIs completely

[Simon Glass]

Hi Bin,

On 1 February 2016 at 19:25, Bin Meng <bmeng.cn@gmail.com> wrote:
> Hi Simon,
>
> On Tue, Feb 2, 2016 at 12:19 AM, Simon Glass <sjg@chromium.org> wrote:
>> Hi Bin,
>>
>> On 1 February 2016 at 02:40, Bin Meng <bmeng.cn@gmail.com> wrote:
>>> There are still some codes that use the legacy PCI APIs to access
>>> the configuration space registers. This series converts those codes
>>> to completely use DM PCI APIs.
>>>
>>> This includes adding several new ops to the PCH uclass driver, and
>>> some clean up to the SPI/GPIO/IRQ drivers.
>>>
>>> Tested on QEMU and Crown Bay. This series is available in pci-working
>>> branch of u-boot-x86 repo.
>>
>> Looks great! This is a big step forward.
>>
>> I've tested it on minnowmax and will test on link in the next day or so.
>>
>> Here are a few things that I think can still be cleaned up:
>> - void pci_assign_irqs(int bus, int device, u8 irq[4]) should use a
>> struct udevice
>
> I guess no, unless we expand struct udevice to include interrupt
> routing information? But that's not generic across architectures. I am
> not sure how.

I suppose we can adjust it to take a struct udevice and drop the bus
and device parameters. But then we need to be able to support reading
from different functions, so will need to use pci_bus_read_config().
But at least that is a DM function. Hmmm....

>
>> - pci_x86_read/write_config() move into drivers/pci/pci_x86.c (needs
>> ivybridge fix which I'll look at)
>
> Yep. I wanted to do this when reviewing one of previous patches.

OK let's see what I find.

>
>> - disable DM_PCI_COMPAT for x86
>
> Looks e1000 and pch_gbe (Crown Bay) ethernet drivers are still using
> legacy PCI APIs. e1000 might need quite amount of work as it is being
> widely used on lots of boards. I can update pch_gbe driver later.

I converted rtl8169 using #ifdef and it seemed to work OK. We don't
need to remove the old code.

>
>> - use the PCI mmio access method instead of I/O once it becomes possible
>
> Yep.
>
>> - moving vesa video to driver model (UCLASS_VIDEO)
>
> I was not following the dm video changes recently, but I guess yes.

It only merged recently. I haven't tried looking at that.

On another note, I just got an Edison. What do you think about
supporting that in U-Boot?

Regards,
Simon

[U-Boot] [PATCH 00/23] x86: Convert to use DM PCI APIs completely

[Bin Meng]

Hi Simon,

On Tue, Feb 2, 2016 at 11:55 AM, Simon Glass <sjg@chromium.org> wrote:
> Hi Bin,
>
> On 1 February 2016 at 19:25, Bin Meng <bmeng.cn@gmail.com> wrote:
>> Hi Simon,
>>
>> On Tue, Feb 2, 2016 at 12:19 AM, Simon Glass <sjg@chromium.org> wrote:
>>> Hi Bin,
>>>
>>> On 1 February 2016 at 02:40, Bin Meng <bmeng.cn@gmail.com> wrote:
>>>> There are still some codes that use the legacy PCI APIs to access
>>>> the configuration space registers. This series converts those codes
>>>> to completely use DM PCI APIs.
>>>>
>>>> This includes adding several new ops to the PCH uclass driver, and
>>>> some clean up to the SPI/GPIO/IRQ drivers.
>>>>
>>>> Tested on QEMU and Crown Bay. This series is available in pci-working
>>>> branch of u-boot-x86 repo.
>>>
>>> Looks great! This is a big step forward.
>>>
>>> I've tested it on minnowmax and will test on link in the next day or so.
>>>
>>> Here are a few things that I think can still be cleaned up:
>>> - void pci_assign_irqs(int bus, int device, u8 irq[4]) should use a
>>> struct udevice
>>
>> I guess no, unless we expand struct udevice to include interrupt
>> routing information? But that's not generic across architectures. I am
>> not sure how.
>
> I suppose we can adjust it to take a struct udevice and drop the bus
> and device parameters. But then we need to be able to support reading
> from different functions, so will need to use pci_bus_read_config().
> But at least that is a DM function. Hmmm....
>

Currently bus and device parameters come from the device tree
<intel,pirq-routing> property. If we just pass struct udevice, that
means we have to saving the routing information <INTx mapping to
PIRQx) somewhere in the udevice. I doubt that will be generic.

>>
>>> - pci_x86_read/write_config() move into drivers/pci/pci_x86.c (needs
>>> ivybridge fix which I'll look at)
>>
>> Yep. I wanted to do this when reviewing one of previous patches.
>
> OK let's see what I find.
>
>>
>>> - disable DM_PCI_COMPAT for x86
>>
>> Looks e1000 and pch_gbe (Crown Bay) ethernet drivers are still using
>> legacy PCI APIs. e1000 might need quite amount of work as it is being
>> widely used on lots of boards. I can update pch_gbe driver later.
>
> I converted rtl8169 using #ifdef and it seemed to work OK. We don't
> need to remove the old code.
>
>>
>>> - use the PCI mmio access method instead of I/O once it becomes possible
>>
>> Yep.
>>
>>> - moving vesa video to driver model (UCLASS_VIDEO)
>>
>> I was not following the dm video changes recently, but I guess yes.
>
> It only merged recently. I haven't tried looking at that.
>
> On another note, I just got an Edison. What do you think about
> supporting that in U-Boot?
>

I think that's Intel Edison [1] you are talking about? It's based on
one Atom (don't know which exact model it is) plus one Quark
processor. Did Intel release any open source SDK for this board?

[1] http://www.intel.com/buy/us/en/product/emergingtechnologies/intel-edison-compute-module-iot-463633

Regards,
Bin

[U-Boot] [PATCH 01/23] spi: ich: Some clean up

[Jagan Teki]

On 1 February 2016 at 21:49, Simon Glass <sjg@chromium.org> wrote:
> On 1 February 2016 at 02:40, Bin Meng <bmeng.cn@gmail.com> wrote:
>>
>> This cleans up the ich spi driver a little bit:
>> - Remove struct ich_spi_slave that is not referenced anywhere
>> - Remove ending period in some comments
>> - Move struct ich_spi_platdata and struct ich_spi_priv to ich.h
>> - Add #ifndef _ICH_H_ .. in ich.h
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>> ---
>>
>>  drivers/spi/ich.c | 38 +++++--------------------------------
>>  drivers/spi/ich.h | 56 +++++++++++++++++++++++++++++++++++++++++--------------
>>  2 files changed, 47 insertions(+), 47 deletions(-)
>
>
> Reviewed-by: Simon Glass <sjg@chromium.org>

Reviewed-by: Jagan Teki <jteki@openedev.com>

-- 
Jagan.

[U-Boot] [PATCH 02/23] spi: ich: Use compatible strings to distinguish controller version

[Jagan Teki]

On 1 February 2016 at 21:49, Simon Glass <sjg@chromium.org> wrote:
> On 1 February 2016 at 02:40, Bin Meng <bmeng.cn@gmail.com> wrote:
>> At present ich spi driver gets the controller version information via
>> pch, but this can be simply retrieved via spi node's compatible string.
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>> ---
>>
>>  arch/x86/dts/bayleybay.dts          |  2 +-
>>  arch/x86/dts/broadwell_som-6896.dts |  2 +-
>>  arch/x86/dts/chromebook_link.dts    |  2 +-
>>  arch/x86/dts/chromebox_panther.dts  |  2 +-
>>  arch/x86/dts/crownbay.dts           |  2 +-
>>  arch/x86/dts/galileo.dts            |  2 +-
>>  arch/x86/dts/minnowmax.dts          |  2 +-
>>  drivers/spi/ich.c                   | 28 ++++++++++++++++++++++++----
>>  8 files changed, 31 insertions(+), 11 deletions(-)
>
> Reviewed-by: Simon Glass <sjg@chromium.org>
> Tested on Minnowmax:
> Tested-by: Simon Glass <sjg@chromium.org>

Reviewed-by: Jagan Teki <jteki@openedev.com>

-- 
Jagan.

[U-Boot] [PATCH 03/23] spi: ich: Change PCHV_ to ICHV_

[Jagan Teki]

On 1 February 2016 at 21:49, Simon Glass <sjg@chromium.org> wrote:
> On 1 February 2016 at 02:40, Bin Meng <bmeng.cn@gmail.com> wrote:
>> The ICH SPI controller supports two variants, one of which is ICH7
>> compatible and the other is ICH9 compatible. Change 'pch_version'
>> to 'ich_version' to better match its original name.
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>> ---
>>
>>  drivers/spi/ich.c | 14 +++++++-------
>>  drivers/spi/ich.h |  7 ++++++-
>>  2 files changed, 13 insertions(+), 8 deletions(-)
>
> Reviewed-by: Simon Glass <sjg@chromium.org>
> Tested on Minnowmax:
> Tested-by: Simon Glass <sjg@chromium.org>

Reviewed-by: Jagan Teki <jteki@openedev.com>

-- 
Jagan.

[U-Boot] [PATCH 00/23] x86: Convert to use DM PCI APIs completely

[Simon Glass]

Hi Bin,

On 1 February 2016 at 23:34, Bin Meng <bmeng.cn@gmail.com> wrote:
> Hi Simon,
>
> On Tue, Feb 2, 2016 at 11:55 AM, Simon Glass <sjg@chromium.org> wrote:
>> Hi Bin,
>>
>> On 1 February 2016 at 19:25, Bin Meng <bmeng.cn@gmail.com> wrote:
>>> Hi Simon,
>>>
>>> On Tue, Feb 2, 2016 at 12:19 AM, Simon Glass <sjg@chromium.org> wrote:
>>>> Hi Bin,
>>>>
>>>> On 1 February 2016 at 02:40, Bin Meng <bmeng.cn@gmail.com> wrote:
>>>>> There are still some codes that use the legacy PCI APIs to access
>>>>> the configuration space registers. This series converts those codes
>>>>> to completely use DM PCI APIs.
>>>>>
>>>>> This includes adding several new ops to the PCH uclass driver, and
>>>>> some clean up to the SPI/GPIO/IRQ drivers.
>>>>>
>>>>> Tested on QEMU and Crown Bay. This series is available in pci-working
>>>>> branch of u-boot-x86 repo.
>>>>
>>>> Looks great! This is a big step forward.
>>>>
>>>> I've tested it on minnowmax and will test on link in the next day or so.
>>>>
>>>> Here are a few things that I think can still be cleaned up:
>>>> - void pci_assign_irqs(int bus, int device, u8 irq[4]) should use a
>>>> struct udevice
>>>
>>> I guess no, unless we expand struct udevice to include interrupt
>>> routing information? But that's not generic across architectures. I am
>>> not sure how.
>>
>> I suppose we can adjust it to take a struct udevice and drop the bus
>> and device parameters. But then we need to be able to support reading
>> from different functions, so will need to use pci_bus_read_config().
>> But at least that is a DM function. Hmmm....
>>
>
> Currently bus and device parameters come from the device tree
> <intel,pirq-routing> property. If we just pass struct udevice, that
> means we have to saving the routing information <INTx mapping to
> PIRQx) somewhere in the udevice. I doubt that will be generic.

OK let's worry about it later.

This series:

Tested on link
Tested-by: Simon Glass <sjg@chromium.org>

>
>>>
>>>> - pci_x86_read/write_config() move into drivers/pci/pci_x86.c (needs
>>>> ivybridge fix which I'll look at)
>>>
>>> Yep. I wanted to do this when reviewing one of previous patches.
>>
>> OK let's see what I find.
>>
>>>
>>>> - disable DM_PCI_COMPAT for x86
>>>
>>> Looks e1000 and pch_gbe (Crown Bay) ethernet drivers are still using
>>> legacy PCI APIs. e1000 might need quite amount of work as it is being
>>> widely used on lots of boards. I can update pch_gbe driver later.
>>
>> I converted rtl8169 using #ifdef and it seemed to work OK. We don't
>> need to remove the old code.
>>
>>>
>>>> - use the PCI mmio access method instead of I/O once it becomes possible
>>>
>>> Yep.
>>>
>>>> - moving vesa video to driver model (UCLASS_VIDEO)
>>>
>>> I was not following the dm video changes recently, but I guess yes.
>>
>> It only merged recently. I haven't tried looking at that.
>>
>> On another note, I just got an Edison. What do you think about
>> supporting that in U-Boot?
>>
>
> I think that's Intel Edison [1] you are talking about? It's based on
> one Atom (don't know which exact model it is) plus one Quark
> processor. Did Intel release any open source SDK for this board?
>
> [1] http://www.intel.com/buy/us/en/product/emergingtechnologies/intel-edison-compute-module-iot-463633

It seems that it uses U-Boot:

git at github.com:01org/edison-u-boot.git

I'll see if I can find someone at Intel to ask if they plan to upstream it.

Regards,
Simon

[U-Boot] [PATCH 00/23] x86: Convert to use DM PCI APIs completely

[Simon Glass]

HI Bin,

On 1 February 2016 at 09:19, Simon Glass <sjg@chromium.org> wrote:
> Hi Bin,
>
> On 1 February 2016 at 02:40, Bin Meng <bmeng.cn@gmail.com> wrote:
>> There are still some codes that use the legacy PCI APIs to access
>> the configuration space registers. This series converts those codes
>> to completely use DM PCI APIs.
>>
>> This includes adding several new ops to the PCH uclass driver, and
>> some clean up to the SPI/GPIO/IRQ drivers.
>>
>> Tested on QEMU and Crown Bay. This series is available in pci-working
>> branch of u-boot-x86 repo.
>
> Looks great! This is a big step forward.
>
> I've tested it on minnowmax and will test on link in the next day or so.
>
> Here are a few things that I think can still be cleaned up:
> - void pci_assign_irqs(int bus, int device, u8 irq[4]) should use a
> struct udevice
> - pci_x86_read/write_config() move into drivers/pci/pci_x86.c (needs
> ivybridge fix which I'll look at)

This is baord_debug_uart_init(), but I can't find a way to get rid of
this. Let me know if you have ideas. It is called very early, before
there is a PCI controller device.

> - disable DM_PCI_COMPAT for x86
> - use the PCI mmio access method instead of I/O once it becomes possible
> - moving vesa video to driver model (UCLASS_VIDEO)
>
> Regards,
> Simon

Regards,
Simon

[U-Boot] [PATCH 00/23] x86: Convert to use DM PCI APIs completely

[Bin Meng]

Hi Simon,

On Wed, Feb 3, 2016 at 11:30 AM, Simon Glass <sjg@chromium.org> wrote:
> Hi Bin,
>
> On 1 February 2016 at 23:34, Bin Meng <bmeng.cn@gmail.com> wrote:
>> Hi Simon,
>>
>> On Tue, Feb 2, 2016 at 11:55 AM, Simon Glass <sjg@chromium.org> wrote:
>>> Hi Bin,
>>>
>>> On 1 February 2016 at 19:25, Bin Meng <bmeng.cn@gmail.com> wrote:
>>>> Hi Simon,
>>>>
>>>> On Tue, Feb 2, 2016 at 12:19 AM, Simon Glass <sjg@chromium.org> wrote:
>>>>> Hi Bin,
>>>>>
>>>>> On 1 February 2016 at 02:40, Bin Meng <bmeng.cn@gmail.com> wrote:
>>>>>> There are still some codes that use the legacy PCI APIs to access
>>>>>> the configuration space registers. This series converts those codes
>>>>>> to completely use DM PCI APIs.
>>>>>>
>>>>>> This includes adding several new ops to the PCH uclass driver, and
>>>>>> some clean up to the SPI/GPIO/IRQ drivers.
>>>>>>
>>>>>> Tested on QEMU and Crown Bay. This series is available in pci-working
>>>>>> branch of u-boot-x86 repo.
>>>>>
>>>>> Looks great! This is a big step forward.
>>>>>
>>>>> I've tested it on minnowmax and will test on link in the next day or so.
>>>>>
>>>>> Here are a few things that I think can still be cleaned up:
>>>>> - void pci_assign_irqs(int bus, int device, u8 irq[4]) should use a
>>>>> struct udevice
>>>>
>>>> I guess no, unless we expand struct udevice to include interrupt
>>>> routing information? But that's not generic across architectures. I am
>>>> not sure how.
>>>
>>> I suppose we can adjust it to take a struct udevice and drop the bus
>>> and device parameters. But then we need to be able to support reading
>>> from different functions, so will need to use pci_bus_read_config().
>>> But at least that is a DM function. Hmmm....
>>>
>>
>> Currently bus and device parameters come from the device tree
>> <intel,pirq-routing> property. If we just pass struct udevice, that
>> means we have to saving the routing information <INTx mapping to
>> PIRQx) somewhere in the udevice. I doubt that will be generic.
>
> OK let's worry about it later.
>
> This series:
>
> Tested on link
> Tested-by: Simon Glass <sjg@chromium.org>
>
>>
>>>>
>>>>> - pci_x86_read/write_config() move into drivers/pci/pci_x86.c (needs
>>>>> ivybridge fix which I'll look at)
>>>>
>>>> Yep. I wanted to do this when reviewing one of previous patches.
>>>
>>> OK let's see what I find.
>>>
>>>>
>>>>> - disable DM_PCI_COMPAT for x86
>>>>
>>>> Looks e1000 and pch_gbe (Crown Bay) ethernet drivers are still using
>>>> legacy PCI APIs. e1000 might need quite amount of work as it is being
>>>> widely used on lots of boards. I can update pch_gbe driver later.
>>>
>>> I converted rtl8169 using #ifdef and it seemed to work OK. We don't
>>> need to remove the old code.
>>>
>>>>
>>>>> - use the PCI mmio access method instead of I/O once it becomes possible
>>>>
>>>> Yep.
>>>>
>>>>> - moving vesa video to driver model (UCLASS_VIDEO)
>>>>
>>>> I was not following the dm video changes recently, but I guess yes.
>>>
>>> It only merged recently. I haven't tried looking at that.
>>>
>>> On another note, I just got an Edison. What do you think about
>>> supporting that in U-Boot?
>>>
>>
>> I think that's Intel Edison [1] you are talking about? It's based on
>> one Atom (don't know which exact model it is) plus one Quark
>> processor. Did Intel release any open source SDK for this board?
>>
>> [1] http://www.intel.com/buy/us/en/product/emergingtechnologies/intel-edison-compute-module-iot-463633
>
> It seems that it uses U-Boot:
>
> git at github.com:01org/edison-u-boot.git
>

This is great! Looks
https://github.com/01org/edison-u-boot/commits/edison-v2015.10 is the
branch and commits for edison.

> I'll see if I can find someone at Intel to ask if they plan to upstream it.
>

That would be nice if Intel is willing to contribute something to the
U-Boot x86 support!

Regards,
Bin

[U-Boot] [PATCH 00/23] x86: Convert to use DM PCI APIs completely

[Bin Meng]

Hi Simon,

On Wed, Feb 3, 2016 at 11:37 AM, Simon Glass <sjg@chromium.org> wrote:
> HI Bin,
>
> On 1 February 2016 at 09:19, Simon Glass <sjg@chromium.org> wrote:
>> Hi Bin,
>>
>> On 1 February 2016 at 02:40, Bin Meng <bmeng.cn@gmail.com> wrote:
>>> There are still some codes that use the legacy PCI APIs to access
>>> the configuration space registers. This series converts those codes
>>> to completely use DM PCI APIs.
>>>
>>> This includes adding several new ops to the PCH uclass driver, and
>>> some clean up to the SPI/GPIO/IRQ drivers.
>>>
>>> Tested on QEMU and Crown Bay. This series is available in pci-working
>>> branch of u-boot-x86 repo.
>>
>> Looks great! This is a big step forward.
>>
>> I've tested it on minnowmax and will test on link in the next day or so.
>>
>> Here are a few things that I think can still be cleaned up:
>> - void pci_assign_irqs(int bus, int device, u8 irq[4]) should use a
>> struct udevice
>> - pci_x86_read/write_config() move into drivers/pci/pci_x86.c (needs
>> ivybridge fix which I'll look at)
>
> This is baord_debug_uart_init(), but I can't find a way to get rid of
> this. Let me know if you have ideas. It is called very early, before
> there is a PCI controller device.

I see. Maybe we can move this baord_debug_uart_init() to
early_board_init in board/google/common/early_init.S? I see the
existing codes in early_init.S program something to a PCI
configuration register too.

>> - disable DM_PCI_COMPAT for x86
>> - use the PCI mmio access method instead of I/O once it becomes possible
>> - moving vesa video to driver model (UCLASS_VIDEO)

Regards,
Bin

[U-Boot] [PATCH 01/23] spi: ich: Some clean up

[Bin Meng]

On Tue, Feb 2, 2016 at 11:54 PM, Jagan Teki <jteki@openedev.com> wrote:
> On 1 February 2016 at 21:49, Simon Glass <sjg@chromium.org> wrote:
>> On 1 February 2016 at 02:40, Bin Meng <bmeng.cn@gmail.com> wrote:
>>>
>>> This cleans up the ich spi driver a little bit:
>>> - Remove struct ich_spi_slave that is not referenced anywhere
>>> - Remove ending period in some comments
>>> - Move struct ich_spi_platdata and struct ich_spi_priv to ich.h
>>> - Add #ifndef _ICH_H_ .. in ich.h
>>>
>>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>>> ---
>>>
>>>  drivers/spi/ich.c | 38 +++++--------------------------------
>>>  drivers/spi/ich.h | 56 +++++++++++++++++++++++++++++++++++++++++--------------
>>>  2 files changed, 47 insertions(+), 47 deletions(-)
>>
>>
>> Reviewed-by: Simon Glass <sjg@chromium.org>
>
> Reviewed-by: Jagan Teki <jteki@openedev.com>
>

applied to u-boot-x86/master, thanks!

[U-Boot] [PATCH 02/23] spi: ich: Use compatible strings to distinguish controller version

[Bin Meng]

On Tue, Feb 2, 2016 at 11:55 PM, Jagan Teki <jteki@openedev.com> wrote:
> On 1 February 2016 at 21:49, Simon Glass <sjg@chromium.org> wrote:
>> On 1 February 2016 at 02:40, Bin Meng <bmeng.cn@gmail.com> wrote:
>>> At present ich spi driver gets the controller version information via
>>> pch, but this can be simply retrieved via spi node's compatible string.
>>>
>>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>>> ---
>>>
>>>  arch/x86/dts/bayleybay.dts          |  2 +-
>>>  arch/x86/dts/broadwell_som-6896.dts |  2 +-
>>>  arch/x86/dts/chromebook_link.dts    |  2 +-
>>>  arch/x86/dts/chromebox_panther.dts  |  2 +-
>>>  arch/x86/dts/crownbay.dts           |  2 +-
>>>  arch/x86/dts/galileo.dts            |  2 +-
>>>  arch/x86/dts/minnowmax.dts          |  2 +-
>>>  drivers/spi/ich.c                   | 28 ++++++++++++++++++++++++----
>>>  8 files changed, 31 insertions(+), 11 deletions(-)
>>
>> Reviewed-by: Simon Glass <sjg@chromium.org>
>> Tested on Minnowmax:
>> Tested-by: Simon Glass <sjg@chromium.org>
>
> Reviewed-by: Jagan Teki <jteki@openedev.com>
>

applied to u-boot-x86/master, thanks!

[U-Boot] [PATCH 03/23] spi: ich: Change PCHV_ to ICHV_

[Bin Meng]

On Wed, Feb 3, 2016 at 12:01 AM, Jagan Teki <jteki@openedev.com> wrote:
> On 1 February 2016 at 21:49, Simon Glass <sjg@chromium.org> wrote:
>> On 1 February 2016 at 02:40, Bin Meng <bmeng.cn@gmail.com> wrote:
>>> The ICH SPI controller supports two variants, one of which is ICH7
>>> compatible and the other is ICH9 compatible. Change 'pch_version'
>>> to 'ich_version' to better match its original name.
>>>
>>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>>> ---
>>>
>>>  drivers/spi/ich.c | 14 +++++++-------
>>>  drivers/spi/ich.h |  7 ++++++-
>>>  2 files changed, 13 insertions(+), 8 deletions(-)
>>
>> Reviewed-by: Simon Glass <sjg@chromium.org>
>> Tested on Minnowmax:
>> Tested-by: Simon Glass <sjg@chromium.org>
>
> Reviewed-by: Jagan Teki <jteki@openedev.com>
>

applied to u-boot-x86/master, thanks!

[U-Boot] [PATCH 04/23] x86: tnc: Drop unprotect_spi_flash()

[Bin Meng]

On Tue, Feb 2, 2016 at 12:19 AM, Simon Glass <sjg@chromium.org> wrote:
> On 1 February 2016 at 02:40, Bin Meng <bmeng.cn@gmail.com> wrote:
>> Unprotecting SPI flash is now handled in the SPI controller driver,
>> via a call to the PCH driver. Drop the ad-hoc version.
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>> ---
>>
>>  arch/x86/cpu/queensbay/tnc.c | 16 ----------------
>>  include/configs/crownbay.h   |  1 -
>>  2 files changed, 17 deletions(-)
>
> Reviewed-by: Simon Glass <sjg@chromium.org>
> Tested on Minnowmax:
> Tested-by: Simon Glass <sjg@chromium.org>

applied to u-boot-x86/master, thanks!

[U-Boot] [PATCH 05/23] x86: quark: Drop unprotect_spi_flash()

[Bin Meng]

On Tue, Feb 2, 2016 at 12:19 AM, Simon Glass <sjg@chromium.org> wrote:
> On 1 February 2016 at 02:40, Bin Meng <bmeng.cn@gmail.com> wrote:
>> Unprotecting SPI flash is now handled in the SPI controller driver,
>> via a call to the PCH driver. Drop the ad-hoc version.
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>> ---
>>
>>  arch/x86/cpu/quark/quark.c | 17 -----------------
>>  1 file changed, 17 deletions(-)
>
> Reviewed-by: Simon Glass <sjg@chromium.org>
> Tested on Minnowmax:
> Tested-by: Simon Glass <sjg@chromium.org>

applied to u-boot-x86/master, thanks!

[U-Boot] [PATCH 06/23] dm: pch: Remove pch_get_version op

[Bin Meng]

On Tue, Feb 2, 2016 at 12:19 AM, Simon Glass <sjg@chromium.org> wrote:
> On 1 February 2016 at 02:40, Bin Meng <bmeng.cn@gmail.com> wrote:
>> pch_get_version op was only used by the ich spi controller driver,
>> and does not really provide a good identification of pch controller
>> so far, since we see plenty of Intel PCH chipsets and one differs
>> from another a lot, which is not simply either a PCHV_7 or PCHV_9.
>> Now that ich spi controller driver was updated to not get such info
>> from pch, the pch_get_version op is useless now.
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>> ---
>>
>>  arch/x86/cpu/ivybridge/bd82x6x.c |  6 ------
>>  drivers/pch/pch-uclass.c         | 10 ----------
>>  drivers/pch/pch7.c               |  6 ------
>>  drivers/pch/pch9.c               |  6 ------
>>  include/pch.h                    | 20 --------------------
>>  5 files changed, 48 deletions(-)
>
> Reviewed-by: Simon Glass <sjg@chromium.org>
> Tested on Minnowmax:
> Tested-by: Simon Glass <sjg@chromium.org>

applied to u-boot-x86/master, thanks!

[U-Boot] [PATCH 07/23] dm: pch: Rename get_sbase op to get_spi_base

[Bin Meng]

On Tue, Feb 2, 2016 at 12:19 AM, Simon Glass <sjg@chromium.org> wrote:
> On 1 February 2016 at 02:40, Bin Meng <bmeng.cn@gmail.com> wrote:
>> Spell out 'sbase' to 'spi_base' so that it looks clearer.
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>> ---
>>
>>  arch/x86/cpu/ivybridge/bd82x6x.c | 4 ++--
>>  drivers/pch/pch-uclass.c         | 6 +++---
>>  drivers/pch/pch7.c               | 4 ++--
>>  drivers/pch/pch9.c               | 4 ++--
>>  drivers/spi/ich.c                | 2 +-
>>  include/pch.h                    | 8 ++++----
>>  6 files changed, 14 insertions(+), 14 deletions(-)
>
> Reviewed-by: Simon Glass <sjg@chromium.org>
> Tested on Minnowmax:
> Tested-by: Simon Glass <sjg@chromium.org>

applied to u-boot-x86/master, thanks!

[U-Boot] [PATCH 08/23] dm: pch: Add get_gpio_base op

[Bin Meng]

On Tue, Feb 2, 2016 at 12:19 AM, Simon Glass <sjg@chromium.org> wrote:
> On 1 February 2016 at 02:40, Bin Meng <bmeng.cn@gmail.com> wrote:
>> x86 GPIO registers are accessed via I/O port whose base address is
>> configured in a PCI configuration register on the PCH device. Add
>> an op get_gpio_base to get the GPIO base address from PCH.
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>> ---
>>
>>  drivers/pch/pch-uclass.c | 11 +++++++++++
>>  include/pch.h            | 18 ++++++++++++++++++
>>  2 files changed, 29 insertions(+)
>
> Reviewed-by: Simon Glass <sjg@chromium.org>
> Tested on Minnowmax:
> Tested-by: Simon Glass <sjg@chromium.org>

applied to u-boot-x86/master, thanks!

[U-Boot] [PATCH 09/23] x86: pch: Implement get_gpio_base op

[Bin Meng]

On Tue, Feb 2, 2016 at 12:19 AM, Simon Glass <sjg@chromium.org> wrote:
> On 1 February 2016 at 02:40, Bin Meng <bmeng.cn@gmail.com> wrote:
>> Implement get_gpio_base op for bd82x6x, pch7 and pch9 drivers.
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>> ---
>>
>>  arch/x86/cpu/ivybridge/bd82x6x.c | 33 +++++++++++++++++++++++++++++++++
>>  drivers/pch/pch7.c               | 33 +++++++++++++++++++++++++++++++++
>>  drivers/pch/pch9.c               | 33 +++++++++++++++++++++++++++++++++
>>  3 files changed, 99 insertions(+)
>
> Reviewed-by: Simon Glass <sjg@chromium.org>
> Tested on Minnowmax:
> Tested-by: Simon Glass <sjg@chromium.org>

applied to u-boot-x86/master, thanks!

[U-Boot] [PATCH 10/23] dm: pch: Add get_io_base op

[Bin Meng]

On Tue, Feb 2, 2016 at 12:19 AM, Simon Glass <sjg@chromium.org> wrote:
> On 1 February 2016 at 02:40, Bin Meng <bmeng.cn@gmail.com> wrote:
>> On some newer chipset (eg: BayTrail), there is an IO base address
>> register on the PCH device which configures the base address of a
>> memory-mapped I/O controller.
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>> ---
>>
>>  drivers/pch/pch-uclass.c | 11 +++++++++++
>>  include/pch.h            | 18 ++++++++++++++++++
>>  2 files changed, 29 insertions(+)
>
> Reviewed-by: Simon Glass <sjg@chromium.org>
> Tested on Minnowmax:
> Tested-by: Simon Glass <sjg@chromium.org>

applied to u-boot-x86/master, thanks!

[U-Boot] [PATCH 11/23] x86: pch9: Implement get_io_base op

[Bin Meng]

On Tue, Feb 2, 2016 at 12:19 AM, Simon Glass <sjg@chromium.org> wrote:
> On 1 February 2016 at 02:40, Bin Meng <bmeng.cn@gmail.com> wrote:
>> IO_BASE is only seen on PCH9 device, implement the get_io_base op.
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>> ---
>>
>>  drivers/pch/pch9.c | 17 +++++++++++++++++
>>  1 file changed, 17 insertions(+)
>
> Reviewed-by: Simon Glass <sjg@chromium.org>
> Tested on Minnowmax:
> Tested-by: Simon Glass <sjg@chromium.org>

applied to u-boot-x86/master, thanks!

[U-Boot] [PATCH 12/23] x86: ich6_gpio: Convert to use proper DM API

[Bin Meng]

On Tue, Feb 2, 2016 at 12:20 AM, Simon Glass <sjg@chromium.org> wrote:
> On 1 February 2016 at 02:40, Bin Meng <bmeng.cn@gmail.com> wrote:
>> At present this GPIO driver still uses the legacy PCI API. Now that
>> we have proper PCH drivers we can use those to obtain the information
>> we need. While the device tree has nodes for the GPIO peripheral it is
>> not in the right place. It should be on the PCI bus as a sub-peripheral
>> of the PCH device.
>>
>> Update the device tree files to show the GPIO controller within the PCH,
>> so that PCI access works as expected. This also adds #address-cells and
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>> ---
>>
>>  arch/x86/dts/bayleybay.dts         |  86 ++++++++++++-------------
>>  arch/x86/dts/chromebook_link.dts   |  42 ++++++-------
>>  arch/x86/dts/chromebox_panther.dts |  44 ++++++-------
>>  arch/x86/dts/crownbay.dts          |  30 ++++-----
>>  arch/x86/dts/galileo.dts           |  28 +++++----
>>  arch/x86/dts/minnowmax.dts         |  86 ++++++++++++-------------
>>  drivers/gpio/intel_ich6_gpio.c     | 125 +++++++------------------------------
>>  7 files changed, 186 insertions(+), 255 deletions(-)
>
> Reviewed-by: Simon Glass <sjg@chromium.org>
> Tested on Minnowmax:
> Tested-by: Simon Glass <sjg@chromium.org>

applied to u-boot-x86/master, thanks!

[U-Boot] [PATCH 13/23] x86: Drop asm/arch/gpio.h

[Bin Meng]

On Tue, Feb 2, 2016 at 12:20 AM, Simon Glass <sjg@chromium.org> wrote:
> On 1 February 2016 at 02:40, Bin Meng <bmeng.cn@gmail.com> wrote:
>> asm/arch/gpio.h is not needed anymore as we get the GPIO base from
>> PCH driver.
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>> ---
>>
>>  arch/x86/include/asm/arch-baytrail/gpio.h  | 13 -------------
>>  arch/x86/include/asm/arch-coreboot/gpio.h  | 13 -------------
>>  arch/x86/include/asm/arch-efi/gpio.h       | 10 ----------
>>  arch/x86/include/asm/arch-ivybridge/gpio.h | 13 -------------
>>  arch/x86/include/asm/arch-qemu/gpio.h      | 13 -------------
>>  arch/x86/include/asm/arch-quark/gpio.h     | 13 -------------
>>  arch/x86/include/asm/arch-queensbay/gpio.h | 13 -------------
>>  arch/x86/include/asm/gpio.h                |  1 -
>>  board/intel/galileo/galileo.c              |  5 ++---
>>  9 files changed, 2 insertions(+), 92 deletions(-)
>>  delete mode 100644 arch/x86/include/asm/arch-baytrail/gpio.h
>>  delete mode 100644 arch/x86/include/asm/arch-coreboot/gpio.h
>>  delete mode 100644 arch/x86/include/asm/arch-efi/gpio.h
>>  delete mode 100644 arch/x86/include/asm/arch-ivybridge/gpio.h
>>  delete mode 100644 arch/x86/include/asm/arch-qemu/gpio.h
>>  delete mode 100644 arch/x86/include/asm/arch-quark/gpio.h
>>  delete mode 100644 arch/x86/include/asm/arch-queensbay/gpio.h
>
> Reviewed-by: Simon Glass <sjg@chromium.org>
> Tested on Minnowmax:
> Tested-by: Simon Glass <sjg@chromium.org>

applied to u-boot-x86/master, thanks!

[U-Boot] [PATCH 14/23] x86: minnowmax: Drop io-base property in the pch_pinctrl node

[Bin Meng]

On Tue, Feb 2, 2016 at 12:20 AM, Simon Glass <sjg@chromium.org> wrote:
> On 1 February 2016 at 02:40, Bin Meng <bmeng.cn@gmail.com> wrote:
>> IOBASE is now obtained from PCH driver, drop this <io-base> property.
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>> ---
>>
>>  arch/x86/dts/minnowmax.dts | 1 -
>>  1 file changed, 1 deletion(-)
>
> Reviewed-by: Simon Glass <sjg@chromium.org>
> Tested on Minnowmax:
> Tested-by: Simon Glass <sjg@chromium.org>

applied to u-boot-x86/master, thanks!

[U-Boot] [PATCH 15/23] x86: irq: Get irq_router's bdf via dm_pci_get_bdf()

[Bin Meng]

On Tue, Feb 2, 2016 at 12:20 AM, Simon Glass <sjg@chromium.org> wrote:
> On 1 February 2016 at 02:40, Bin Meng <bmeng.cn@gmail.com> wrote:
>> There is no need to parse PCH's <reg> property as we have already
>> a DM PCI API dm_pci_get_bdf() that can handle this.
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>> ---
>>
>>  arch/x86/cpu/irq.c | 9 +--------
>>  1 file changed, 1 insertion(+), 8 deletions(-)
>
> Reviewed-by: Simon Glass <sjg@chromium.org>
> Tested on Minnowmax:
> Tested-by: Simon Glass <sjg@chromium.org>

applied to u-boot-x86/master, thanks!

[U-Boot] [PATCH 16/23] x86: irq: Move irq_router to a per driver priv

[Bin Meng]

On Tue, Feb 2, 2016 at 12:20 AM, Simon Glass <sjg@chromium.org> wrote:
> On 1 February 2016 at 02:40, Bin Meng <bmeng.cn@gmail.com> wrote:
>> At present irq_router is declared as a static struct irq_router in
>> arch/x86/cpu/irq.c. Since it's a driver control block, it makes sense
>> to move it to a per driver priv. Adjust existing APIs to accept an
>> additional parameter of irq_router's udevice.
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>> ---
>>
>>  arch/x86/cpu/irq.c                  | 73 +++++++++++++++++++------------------
>>  arch/x86/include/asm/pirq_routing.h | 12 ++++--
>>  arch/x86/lib/pirq_routing.c         | 12 +++---
>>  3 files changed, 51 insertions(+), 46 deletions(-)
>
> Reviewed-by: Simon Glass <sjg@chromium.org>
> Tested on Minnowmax:
> Tested-by: Simon Glass <sjg@chromium.org>

applied to u-boot-x86/master, thanks!

[U-Boot] [PATCH 17/23] x86: irq: Convert to use DM PCI API

[Bin Meng]

On Tue, Feb 2, 2016 at 12:20 AM, Simon Glass <sjg@chromium.org> wrote:
> On 1 February 2016 at 02:40, Bin Meng <bmeng.cn@gmail.com> wrote:
>> Now that we have irq router's udevice passed as a parameter, it's
>> time to start using the DM PCI API instead of those legacy ones.
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>> ---
>>
>>  arch/x86/cpu/irq.c           | 6 +++---
>>  arch/x86/cpu/queensbay/irq.c | 2 +-
>>  2 files changed, 4 insertions(+), 4 deletions(-)
>
> Reviewed-by: Simon Glass <sjg@chromium.org>
> Tested on Minnowmax:
> Tested-by: Simon Glass <sjg@chromium.org>

applied to u-boot-x86/master, thanks!

[U-Boot] [PATCH 18/23] x86: tnc: Change disable_igd() to have a return value

[Bin Meng]

On Tue, Feb 2, 2016 at 12:20 AM, Simon Glass <sjg@chromium.org> wrote:
> On 1 February 2016 at 02:40, Bin Meng <bmeng.cn@gmail.com> wrote:
>> So far disable_igd() does not have any return value, but we may need
>> that in the future.
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>> ---
>>
>>  arch/x86/cpu/queensbay/tnc.c | 10 +++++++---
>>  1 file changed, 7 insertions(+), 3 deletions(-)
>
> Reviewed-by: Simon Glass <sjg@chromium.org>
> Tested on Minnowmax:
> Tested-by: Simon Glass <sjg@chromium.org>

applied to u-boot-x86/master, thanks!

[U-Boot] [PATCH 19/23] x86: tnc: Use DM PCI API in disable_igd()

[Bin Meng]

On Tue, Feb 2, 2016 at 12:20 AM, Simon Glass <sjg@chromium.org> wrote:
> On 1 February 2016 at 02:40, Bin Meng <bmeng.cn@gmail.com> wrote:
>> Once we get udevice of IGD and SDVO, we can use its udevice to
>> access PCI configuration space with dm_pci_write_config32().
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>> ---
>>
>>  arch/x86/cpu/queensbay/tnc.c | 22 +++++++++++++++++++---
>>  1 file changed, 19 insertions(+), 3 deletions(-)
>
> Reviewed-by: Simon Glass <sjg@chromium.org>
> Tested on Minnowmax:
> Tested-by: Simon Glass <sjg@chromium.org>

applied to u-boot-x86/master, thanks!

[U-Boot] [PATCH 20/23] x86: tnc: Remove IGD and SDVO devices from driver model

[Bin Meng]

On Tue, Feb 2, 2016 at 12:20 AM, Simon Glass <sjg@chromium.org> wrote:
> Hi Bin,
>
> On 1 February 2016 at 02:40, Bin Meng <bmeng.cn@gmail.com> wrote:
>> With recent DM PCI changes to vesa_fb driver, external graphics
>> card does not work any more. This is because: after setting the
>> function disable bit, IGD and SDVO devices will disappear in the
>> PCI configuration space. This however creates an inconsistent state
>> from a driver model PCI controller point of view, as these two PCI
>> devices are still attached to its parent's child device list as
>> maintained by the driver model. Some driver model PCI APIs like
>> dm_pci_find_class() used in the vesa_fb driver, are referring to
>> the list to speed up the finding process instead of re-enumerating
>> the whole PCI bus, so it gets the stale cached data which is wrong.
>>
>> To fix this, manually remove these two devices.
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>> ---
>>
>>  arch/x86/cpu/queensbay/tnc.c | 36 ++++++++++++++++++++++++++++++++++++
>>  1 file changed, 36 insertions(+)
>
> Reviewed-by: Simon Glass <sjg@chromium.org>
> Tested on Minnowmax:
> Tested-by: Simon Glass <sjg@chromium.org>
>

applied to u-boot-x86/master, thanks!

[U-Boot] [PATCH 21/23] x86: qemu: Convert to use DM PCI API

[Bin Meng]

On Tue, Feb 2, 2016 at 12:20 AM, Simon Glass <sjg@chromium.org> wrote:
> On 1 February 2016 at 02:40, Bin Meng <bmeng.cn@gmail.com> wrote:
>> Use pci_[read|write]_config intead of x86_pci_[read|write]_config.
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>> ---
>>
>>  arch/x86/cpu/qemu/qemu.c | 34 +++++++++++++++++-----------------
>>  1 file changed, 17 insertions(+), 17 deletions(-)
>
> Reviewed-by: Simon Glass <sjg@chromium.org>
> Tested on Minnowmax:
> Tested-by: Simon Glass <sjg@chromium.org>

applied to u-boot-x86/master, thanks!

[U-Boot] [PATCH 22/23] x86: pci: Use DM PCI APIs in pci_assign_irqs()

[Bin Meng]

On Tue, Feb 2, 2016 at 12:20 AM, Simon Glass <sjg@chromium.org> wrote:
> On 1 February 2016 at 02:40, Bin Meng <bmeng.cn@gmail.com> wrote:
>> Drop legacy PCI APIs usage in pci_assign_irqs() as well.
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>> ---
>>
>>  arch/x86/cpu/pci.c | 6 +++---
>>  1 file changed, 3 insertions(+), 3 deletions(-)
>
> Reviewed-by: Simon Glass <sjg@chromium.org>
> Tested on Minnowmax:
> Tested-by: Simon Glass <sjg@chromium.org>

applied to u-boot-x86/master, thanks!

[U-Boot] [PATCH 23/23] x86: pci: Drop legacy PCI APIs

[Bin Meng]

On Tue, Feb 2, 2016 at 12:20 AM, Simon Glass <sjg@chromium.org> wrote:
> On 1 February 2016 at 02:40, Bin Meng <bmeng.cn@gmail.com> wrote:
>> Now that we have converted all x86 codes to use DM PCI APIs,
>> drop those legacy ones.
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>>
>> ---
>>
>>  arch/x86/cpu/pci.c         | 53 ----------------------------------------------
>>  arch/x86/include/asm/pci.h | 12 -----------
>>  2 files changed, 65 deletions(-)
>
> Reviewed-by: Simon Glass <sjg@chromium.org>
> Tested on Minnowmax:
> Tested-by: Simon Glass <sjg@chromium.org>

applied to u-boot-x86/master, thanks!

[U-Boot] [PATCH 00/23] x86: Convert to use DM PCI APIs completely

[Simon Glass]

Hi Bin,

On 2 February 2016 at 20:44, Bin Meng <bmeng.cn@gmail.com> wrote:
> Hi Simon,
>
> On Wed, Feb 3, 2016 at 11:30 AM, Simon Glass <sjg@chromium.org> wrote:
>> Hi Bin,
>>
>> On 1 February 2016 at 23:34, Bin Meng <bmeng.cn@gmail.com> wrote:
>>> Hi Simon,
>>>
>>> On Tue, Feb 2, 2016 at 11:55 AM, Simon Glass <sjg@chromium.org> wrote:
>>>> Hi Bin,
>>>>
>>>> On 1 February 2016 at 19:25, Bin Meng <bmeng.cn@gmail.com> wrote:
>>>>> Hi Simon,
>>>>>
>>>>> On Tue, Feb 2, 2016 at 12:19 AM, Simon Glass <sjg@chromium.org> wrote:
>>>>>> Hi Bin,
>>>>>>
>>>>>> On 1 February 2016 at 02:40, Bin Meng <bmeng.cn@gmail.com> wrote:
>>>>>>> There are still some codes that use the legacy PCI APIs to access
>>>>>>> the configuration space registers. This series converts those codes
>>>>>>> to completely use DM PCI APIs.
>>>>>>>
>>>>>>> This includes adding several new ops to the PCH uclass driver, and
>>>>>>> some clean up to the SPI/GPIO/IRQ drivers.
>>>>>>>
>>>>>>> Tested on QEMU and Crown Bay. This series is available in pci-working
>>>>>>> branch of u-boot-x86 repo.
>>>>>>
>>>>>> Looks great! This is a big step forward.
>>>>>>
>>>>>> I've tested it on minnowmax and will test on link in the next day or so.
>>>>>>
>>>>>> Here are a few things that I think can still be cleaned up:
>>>>>> - void pci_assign_irqs(int bus, int device, u8 irq[4]) should use a
>>>>>> struct udevice
>>>>>
>>>>> I guess no, unless we expand struct udevice to include interrupt
>>>>> routing information? But that's not generic across architectures. I am
>>>>> not sure how.
>>>>
>>>> I suppose we can adjust it to take a struct udevice and drop the bus
>>>> and device parameters. But then we need to be able to support reading
>>>> from different functions, so will need to use pci_bus_read_config().
>>>> But at least that is a DM function. Hmmm....
>>>>
>>>
>>> Currently bus and device parameters come from the device tree
>>> <intel,pirq-routing> property. If we just pass struct udevice, that
>>> means we have to saving the routing information <INTx mapping to
>>> PIRQx) somewhere in the udevice. I doubt that will be generic.
>>
>> OK let's worry about it later.
>>
>> This series:
>>
>> Tested on link
>> Tested-by: Simon Glass <sjg@chromium.org>
>>
>>>
>>>>>
>>>>>> - pci_x86_read/write_config() move into drivers/pci/pci_x86.c (needs
>>>>>> ivybridge fix which I'll look at)
>>>>>
>>>>> Yep. I wanted to do this when reviewing one of previous patches.
>>>>
>>>> OK let's see what I find.
>>>>
>>>>>
>>>>>> - disable DM_PCI_COMPAT for x86
>>>>>
>>>>> Looks e1000 and pch_gbe (Crown Bay) ethernet drivers are still using
>>>>> legacy PCI APIs. e1000 might need quite amount of work as it is being
>>>>> widely used on lots of boards. I can update pch_gbe driver later.
>>>>
>>>> I converted rtl8169 using #ifdef and it seemed to work OK. We don't
>>>> need to remove the old code.
>>>>
>>>>>
>>>>>> - use the PCI mmio access method instead of I/O once it becomes possible
>>>>>
>>>>> Yep.
>>>>>
>>>>>> - moving vesa video to driver model (UCLASS_VIDEO)
>>>>>
>>>>> I was not following the dm video changes recently, but I guess yes.
>>>>
>>>> It only merged recently. I haven't tried looking at that.
>>>>
>>>> On another note, I just got an Edison. What do you think about
>>>> supporting that in U-Boot?
>>>>
>>>
>>> I think that's Intel Edison [1] you are talking about? It's based on
>>> one Atom (don't know which exact model it is) plus one Quark
>>> processor. Did Intel release any open source SDK for this board?
>>>
>>> [1] http://www.intel.com/buy/us/en/product/emergingtechnologies/intel-edison-compute-module-iot-463633
>>
>> It seems that it uses U-Boot:
>>
>> git at github.com:01org/edison-u-boot.git
>>
>
> This is great! Looks
> https://github.com/01org/edison-u-boot/commits/edison-v2015.10 is the
> branch and commits for edison.

Yes - I just built this and it boots OK on edison. I've sent an email
to two of the authors to see if they are interested in mainlining it.

>
>> I'll see if I can find someone at Intel to ask if they plan to upstream it.
>>
>
> That would be nice if Intel is willing to contribute something to the
> U-Boot x86 support!

Yes.

Regards,
Simon

[U-Boot] [PATCH 00/23] x86: Convert to use DM PCI APIs completely

[Simon Glass]

Hi Bin,

On 2 February 2016 at 20:58, Bin Meng <bmeng.cn@gmail.com> wrote:
> Hi Simon,
>
> On Wed, Feb 3, 2016 at 11:37 AM, Simon Glass <sjg@chromium.org> wrote:
>> HI Bin,
>>
>> On 1 February 2016 at 09:19, Simon Glass <sjg@chromium.org> wrote:
>>> Hi Bin,
>>>
>>> On 1 February 2016 at 02:40, Bin Meng <bmeng.cn@gmail.com> wrote:
>>>> There are still some codes that use the legacy PCI APIs to access
>>>> the configuration space registers. This series converts those codes
>>>> to completely use DM PCI APIs.
>>>>
>>>> This includes adding several new ops to the PCH uclass driver, and
>>>> some clean up to the SPI/GPIO/IRQ drivers.
>>>>
>>>> Tested on QEMU and Crown Bay. This series is available in pci-working
>>>> branch of u-boot-x86 repo.
>>>
>>> Looks great! This is a big step forward.
>>>
>>> I've tested it on minnowmax and will test on link in the next day or so.
>>>
>>> Here are a few things that I think can still be cleaned up:
>>> - void pci_assign_irqs(int bus, int device, u8 irq[4]) should use a
>>> struct udevice
>>> - pci_x86_read/write_config() move into drivers/pci/pci_x86.c (needs
>>> ivybridge fix which I'll look at)
>>
>> This is baord_debug_uart_init(), but I can't find a way to get rid of
>> this. Let me know if you have ideas. It is called very early, before
>> there is a PCI controller device.
>
> I see. Maybe we can move this baord_debug_uart_init() to
> early_board_init in board/google/common/early_init.S? I see the
> existing codes in early_init.S program something to a PCI
> configuration register too.

Thinking about it, I don't think it helps to duplicate the PCI access
code in link. Probably the way it is is better for now.

>
>>> - disable DM_PCI_COMPAT for x86
>>> - use the PCI mmio access method instead of I/O once it becomes possible
>>> - moving vesa video to driver model (UCLASS_VIDEO)
>
> Regards,
> Bin

Regards,
Simon