* Re: [APL PO PATCH] drm/i915/bxt: Additional MIPI clock divider form B0 stepping onwards
2016-02-03 10:43 [APL PO PATCH] drm/i915/bxt: Additional MIPI clock divider form B0 stepping onwards Deepak M
@ 2016-02-03 5:21 ` kbuild test robot
2016-02-03 11:16 ` [PATCH] " Deepak M
2016-02-03 9:47 ` ✓ Fi.CI.BAT: success for drm/i915/bxt: Additional MIPI clock divider form B0 stepping onwards (rev2) Patchwork
2016-02-16 10:39 ` ✓ Fi.CI.BAT: success for drm/i915/bxt: Additional MIPI clock divider form B0 stepping onwards (rev3) Patchwork
2 siblings, 1 reply; 14+ messages in thread
From: kbuild test robot @ 2016-02-03 5:21 UTC (permalink / raw)
Cc: Deepak M, intel-gfx, kbuild-all
[-- Attachment #1: Type: text/plain, Size: 1868 bytes --]
Hi Deepak,
[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on v4.5-rc2 next-20160202]
[if your patch is applied to the wrong git tree, please drop us a note to help improving the system]
url: https://github.com/0day-ci/linux/commits/Deepak-M/drm-i915-bxt-Additional-MIPI-clock-divider-form-B0-stepping-onwards/20160203-131111
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-randconfig-x019-201605 (attached as .config)
reproduce:
# save the attached .config to linux build tree
make ARCH=x86_64
All warnings (new ones prefixed by >>):
drivers/gpu/drm/i915/intel_dsi_pll.c: In function 'bxt_enable_dsi_pll':
>> drivers/gpu/drm/i915/intel_dsi_pll.c:472:21: warning: unused variable 'dev' [-Wunused-variable]
struct drm_device *dev = encoder->base.dev;
^
vim +/dev +472 drivers/gpu/drm/i915/intel_dsi_pll.c
456 /* As per recommendation from hardware team,
457 * Prog PVD ratio =1 if dsi ratio <= 50
458 */
459 if (dsi_ratio <= 50) {
460 val &= ~BXT_DSI_PLL_PVD_RATIO_MASK;
461 val |= BXT_DSI_PLL_PVD_RATIO_1;
462 }
463
464 I915_WRITE(BXT_DSI_PLL_CTL, val);
465 POSTING_READ(BXT_DSI_PLL_CTL);
466
467 return true;
468 }
469
470 static void bxt_enable_dsi_pll(struct intel_encoder *encoder)
471 {
> 472 struct drm_device *dev = encoder->base.dev;
473 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
474 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
475 enum port port;
476 u32 val;
477
478 DRM_DEBUG_KMS("\n");
479
480 val = I915_READ(BXT_DSI_PLL_ENABLE);
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
[-- Attachment #2: .config.gz --]
[-- Type: application/octet-stream, Size: 30488 bytes --]
[-- Attachment #3: Type: text/plain, Size: 159 bytes --]
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^ permalink raw reply [flat|nested] 14+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915/bxt: Additional MIPI clock divider form B0 stepping onwards (rev2)
2016-02-03 10:43 [APL PO PATCH] drm/i915/bxt: Additional MIPI clock divider form B0 stepping onwards Deepak M
2016-02-03 5:21 ` kbuild test robot
@ 2016-02-03 9:47 ` Patchwork
2016-02-16 10:39 ` ✓ Fi.CI.BAT: success for drm/i915/bxt: Additional MIPI clock divider form B0 stepping onwards (rev3) Patchwork
2 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2016-02-03 9:47 UTC (permalink / raw)
To: Deepak M; +Cc: intel-gfx
== Summary ==
Series 3034v2 drm/i915/bxt: Additional MIPI clock divider form B0 stepping onwards
http://patchwork.freedesktop.org/api/1.0/series/3034/revisions/2/mbox/
Test drv_module_reload_basic:
pass -> INCOMPLETE (bdw-nuci7)
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-c:
incomplete -> PASS (hsw-gt2)
bdw-nuci7 total:45 pass:42 dwarn:0 dfail:0 fail:0 skip:2
bdw-ultra total:159 pass:147 dwarn:0 dfail:0 fail:0 skip:12
bsw-nuc-2 total:159 pass:131 dwarn:0 dfail:0 fail:0 skip:28
hsw-brixbox total:159 pass:146 dwarn:0 dfail:0 fail:0 skip:13
hsw-gt2 total:159 pass:149 dwarn:0 dfail:0 fail:0 skip:10
ilk-hp8440p total:159 pass:111 dwarn:0 dfail:0 fail:0 skip:48
ivb-t430s total:159 pass:145 dwarn:0 dfail:0 fail:0 skip:14
skl-i5k-2 total:159 pass:144 dwarn:1 dfail:0 fail:0 skip:14
snb-dellxps total:159 pass:137 dwarn:0 dfail:0 fail:0 skip:22
snb-x220t total:159 pass:137 dwarn:0 dfail:0 fail:1 skip:21
Results at /archive/results/CI_IGT_test/Patchwork_1348/
02932377a975a59ccd83095816d5b23183107d79 drm-intel-nightly: 2016y-02m-03d-01h-54m-27s UTC integration manifest
5c491e5c7b5bf896dbb9b7c0511839e7f6c63486 drm/i915/bxt: Additional MIPI clock divider form B0 stepping onwards
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^ permalink raw reply [flat|nested] 14+ messages in thread
* [APL PO PATCH] drm/i915/bxt: Additional MIPI clock divider form B0 stepping onwards
@ 2016-02-03 10:43 Deepak M
2016-02-03 5:21 ` kbuild test robot
` (2 more replies)
0 siblings, 3 replies; 14+ messages in thread
From: Deepak M @ 2016-02-03 10:43 UTC (permalink / raw)
To: intel-gfx; +Cc: Deepak M
The MIPI clock calculations for the addtional clock
are revised from B0 stepping onwards, the bit definitions
have changed compared to old stepping.
Signed-off-by: Deepak M <m.deepak@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 104 +++++++++++++++++------------------
drivers/gpu/drm/i915/intel_dsi_pll.c | 65 +++++++++++++++-------
2 files changed, 96 insertions(+), 73 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c0bd691..2568f35 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7638,6 +7638,57 @@ enum skl_disp_power_wells {
/* MIPI DSI registers */
+#define BXT_MIPI1_RX_LOWER_SHIFT 16
+#define BXT_MIPI2_RX_LOWER_SHIFT 0
+#define BXT_MIPI_RX_LOWER_SHIFT(port) \
+ _MIPI_PORT(port, BXT_MIPI1_RX_LOWER_SHIFT, \
+ BXT_MIPI2_RX_LOWER_SHIFT)
+#define BXT_MIPI1_RX_LOWER_DIVIDER_MASK (3 << 16)
+#define BXT_MIPI2_RX_LOWER_DIVIDER_MASK (3 << 0)
+#define BXT_MIPI_RX_LOWER_DIVIDER_MASK(port) \
+ (3 << BXT_MIPI_RX_LOWER_SHIFT(port))
+#define BXT_MIPI_RX_LOWER_DIVIDER(port, val) \
+ ((val & 3) << BXT_MIPI_RX_LOWER_SHIFT(port))
+
+#define BXT_MIPI1_8X_BY3_SHIFT 19
+#define BXT_MIPI2_8X_BY3_SHIFT 3
+#define BXT_MIPI_8X_BY3_SHIFT(port) \
+ _MIPI_PORT(port, BXT_MIPI1_8X_BY3_SHIFT, \
+ BXT_MIPI2_8X_BY3_SHIFT)
+#define BXT_MIPI1_8X_BY3_DIVIDER_MASK (3 << 19)
+#define BXT_MIPI2_8X_BY3_DIVIDER_MASK (3 << 3)
+#define BXT_MIPI_8X_BY3_DIVIDER_MASK(port) \
+ (3 << BXT_MIPI_8X_BY3_SHIFT(port))
+#define BXT_MIPI_8X_BY3_DIVIDER(port, val) \
+ ((val & 3) << BXT_MIPI_8X_BY3_SHIFT(port))
+
+#define BXT_MIPI1_RX_UPPER_SHIFT 21
+#define BXT_MIPI2_RX_UPPER_SHIFT 5
+#define BXT_MIPI_RX_UPPER_SHIFT(port) \
+ _MIPI_PORT(port, BXT_MIPI1_RX_UPPER_SHIFT, \
+ BXT_MIPI2_RX_UPPER_SHIFT)
+#define BXT_MIPI1_RX_UPPER_DIVIDER_MASK (3 << 21)
+#define BXT_MIPI2_RX_UPPER_DIVIDER_MASK (3 << 5)
+#define BXT_MIPI_RX_UPPER_DIVIDER_MASK(port) \
+ (3 << BXT_MIPI_RX_UPPER_SHIFT(port))
+#define BXT_MIPI_RX_UPPER_DIVIDER(port, val) \
+ ((val & 3) << BXT_MIPI_RX_UPPER_SHIFT(port))
+
+#define BXT_MIPI1_TX_SHIFT 26
+#define BXT_MIPI2_TX_SHIFT 10
+#define BXT_MIPI_TX_SHIFT(port) \
+ _MIPI_PORT(port, BXT_MIPI1_TX_SHIFT, \
+ BXT_MIPI2_TX_SHIFT)
+#define BXT_MIPI1_TX_DIVIDER_MASK (0x3F << 26)
+#define BXT_MIPI2_TX_DIVIDER_MASK (0x3F << 10)
+#define BXT_MIPI_TX_DIVIDER_MASK(port) \
+ (0x3F << BXT_MIPI_TX_SHIFT(port))
+#define BXT_MIPI_TX_DIVIDER(port, val) \
+ ((val & 0x3F) << BXT_MIPI_TX_SHIFT(port))
+
+#define RX_DIVIDER_BIT_1_2 0x3
+#define RX_DIVIDER_BIT_3_4 0xC
+
#define _MIPI_PORT(port, a, c) _PORT3(port, a, 0, c) /* ports A and C only */
#define _MMIO_MIPI(port, a, c) _MMIO(_MIPI_PORT(port, a, c))
@@ -7650,59 +7701,6 @@ enum skl_disp_power_wells {
#define BXT_MIPI_DIV_SHIFT(port) \
_MIPI_PORT(port, BXT_MIPI1_DIV_SHIFT, \
BXT_MIPI2_DIV_SHIFT)
-/* Var clock divider to generate TX source. Result must be < 39.5 M */
-#define BXT_MIPI1_ESCLK_VAR_DIV_MASK (0x3F << 26)
-#define BXT_MIPI2_ESCLK_VAR_DIV_MASK (0x3F << 10)
-#define BXT_MIPI_ESCLK_VAR_DIV_MASK(port) \
- _MIPI_PORT(port, BXT_MIPI1_ESCLK_VAR_DIV_MASK, \
- BXT_MIPI2_ESCLK_VAR_DIV_MASK)
-
-#define BXT_MIPI_ESCLK_VAR_DIV(port, val) \
- (val << BXT_MIPI_DIV_SHIFT(port))
-/* TX control divider to select actual TX clock output from (8x/var) */
-#define BXT_MIPI1_TX_ESCLK_SHIFT 21
-#define BXT_MIPI2_TX_ESCLK_SHIFT 5
-#define BXT_MIPI_TX_ESCLK_SHIFT(port) \
- _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_SHIFT, \
- BXT_MIPI2_TX_ESCLK_SHIFT)
-#define BXT_MIPI1_TX_ESCLK_FIXDIV_MASK (3 << 21)
-#define BXT_MIPI2_TX_ESCLK_FIXDIV_MASK (3 << 5)
-#define BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port) \
- _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_FIXDIV_MASK, \
- BXT_MIPI2_TX_ESCLK_FIXDIV_MASK)
-#define BXT_MIPI_TX_ESCLK_8XDIV_BY2(port) \
- (0x0 << BXT_MIPI_TX_ESCLK_SHIFT(port))
-#define BXT_MIPI_TX_ESCLK_8XDIV_BY4(port) \
- (0x1 << BXT_MIPI_TX_ESCLK_SHIFT(port))
-#define BXT_MIPI_TX_ESCLK_8XDIV_BY8(port) \
- (0x2 << BXT_MIPI_TX_ESCLK_SHIFT(port))
-/* RX control divider to select actual RX clock output from 8x*/
-#define BXT_MIPI1_RX_ESCLK_SHIFT 19
-#define BXT_MIPI2_RX_ESCLK_SHIFT 3
-#define BXT_MIPI_RX_ESCLK_SHIFT(port) \
- _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_SHIFT, \
- BXT_MIPI2_RX_ESCLK_SHIFT)
-#define BXT_MIPI1_RX_ESCLK_FIXDIV_MASK (3 << 19)
-#define BXT_MIPI2_RX_ESCLK_FIXDIV_MASK (3 << 3)
-#define BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port) \
- (3 << BXT_MIPI_RX_ESCLK_SHIFT(port))
-#define BXT_MIPI_RX_ESCLK_8X_BY2(port) \
- (1 << BXT_MIPI_RX_ESCLK_SHIFT(port))
-#define BXT_MIPI_RX_ESCLK_8X_BY3(port) \
- (2 << BXT_MIPI_RX_ESCLK_SHIFT(port))
-#define BXT_MIPI_RX_ESCLK_8X_BY4(port) \
- (3 << BXT_MIPI_RX_ESCLK_SHIFT(port))
-/* BXT-A WA: Always prog DPHY dividers to 00 */
-#define BXT_MIPI1_DPHY_DIV_SHIFT 16
-#define BXT_MIPI2_DPHY_DIV_SHIFT 0
-#define BXT_MIPI_DPHY_DIV_SHIFT(port) \
- _MIPI_PORT(port, BXT_MIPI1_DPHY_DIV_SHIFT, \
- BXT_MIPI2_DPHY_DIV_SHIFT)
-#define BXT_MIPI_1_DPHY_DIVIDER_MASK (3 << 16)
-#define BXT_MIPI_2_DPHY_DIVIDER_MASK (3 << 0)
-#define BXT_MIPI_DPHY_DIVIDER_MASK(port) \
- (3 << BXT_MIPI_DPHY_DIV_SHIFT(port))
-
/* BXT MIPI mode configure */
#define _BXT_MIPIA_TRANS_HACTIVE 0x6B0F8
#define _BXT_MIPIC_TRANS_HACTIVE 0x6B8F8
diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
index bb5e95a..6dfdcb6 100644
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -362,35 +362,59 @@ static void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
/* Program BXT Mipi clocks and dividers */
static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port)
{
- u32 tmp;
- u32 divider;
- u32 dsi_rate;
- u32 pll_ratio;
struct drm_i915_private *dev_priv = dev->dev_private;
+ u32 tmp;
+ u32 dsi_rate = 0;
+ u32 pll_ratio = 0;
+ u32 rx_div;
+ u32 tx_div;
+ u32 rx_div_upper;
+ u32 rx_div_lower;
+ u32 mipi_8by3_divider;
/* Clear old configurations */
tmp = I915_READ(BXT_MIPI_CLOCK_CTL);
- tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
- tmp &= ~(BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port));
- tmp &= ~(BXT_MIPI_ESCLK_VAR_DIV_MASK(port));
- tmp &= ~(BXT_MIPI_DPHY_DIVIDER_MASK(port));
+ tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port));
+ tmp &= ~(BXT_MIPI_RX_LOWER_DIVIDER_MASK(port));
+ tmp &= ~(BXT_MIPI_RX_UPPER_DIVIDER_MASK(port));
+ tmp &= ~(BXT_MIPI_TX_DIVIDER_MASK(port));
/* Get the current DSI rate(actual) */
pll_ratio = I915_READ(BXT_DSI_PLL_CTL) &
- BXT_DSI_PLL_RATIO_MASK;
+ BXT_DSI_PLL_RATIO_MASK;
+
+ /* To get 8X clock, divide ref_freq * pll ratio by 2 as per bspec */
dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2;
- /* Max possible output of clock is 39.5 MHz, program value -1 */
- divider = (dsi_rate / BXT_MAX_VAR_OUTPUT_KHZ) - 1;
- tmp |= BXT_MIPI_ESCLK_VAR_DIV(port, divider);
+ /*
+ * tx clock should be <= 20MHz and the div value must be
+ * subtracted by 1 as per bspec
+ */
+ tx_div = DIV_ROUND_UP(dsi_rate, 20000) - 1;
+ /*
+ * rx clock should be <= 150MHz and the div value must be
+ * subtracted by 1 as per bspec
+ */
+ rx_div = DIV_ROUND_UP(dsi_rate, 150000) - 1;
/*
- * Tx escape clock must be as close to 20MHz possible, but should
- * not exceed it. Hence select divide by 2
+ * rx divider value needs to be updated in the
+ * two differnt bit fields in the register hence splitting the
+ * rx divider value accordingly
*/
- tmp |= BXT_MIPI_TX_ESCLK_8XDIV_BY2(port);
+ rx_div_lower = rx_div & RX_DIVIDER_BIT_1_2;
+ rx_div_upper = (rx_div & RX_DIVIDER_BIT_3_4) >> 2;
- tmp |= BXT_MIPI_RX_ESCLK_8X_BY3(port);
+ /* As per bpsec program the 8/3X clock divider to the below value */
+ if (dev_priv->vbt.dsi.config->is_cmd_mode)
+ mipi_8by3_divider = 0x2;
+ else
+ mipi_8by3_divider = 0x3;
+
+ tmp |= BXT_MIPI_8X_BY3_DIVIDER(port, mipi_8by3_divider);
+ tmp |= BXT_MIPI_TX_DIVIDER(port, tx_div);
+ tmp |= BXT_MIPI_RX_LOWER_DIVIDER(port, rx_div_lower);
+ tmp |= BXT_MIPI_RX_UPPER_DIVIDER(port, rx_div_upper);
I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
}
@@ -445,6 +469,7 @@ static bool bxt_configure_dsi_pll(struct intel_encoder *encoder)
static void bxt_enable_dsi_pll(struct intel_encoder *encoder)
{
+ struct drm_device *dev = encoder->base.dev;
struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
enum port port;
@@ -512,10 +537,10 @@ static void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
/* Clear old configurations */
tmp = I915_READ(BXT_MIPI_CLOCK_CTL);
- tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
- tmp &= ~(BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port));
- tmp &= ~(BXT_MIPI_ESCLK_VAR_DIV_MASK(port));
- tmp &= ~(BXT_MIPI_DPHY_DIVIDER_MASK(port));
+ tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port));
+ tmp &= ~(BXT_MIPI_RX_LOWER_DIVIDER_MASK(port));
+ tmp &= ~(BXT_MIPI_RX_UPPER_DIVIDER_MASK(port));
+ tmp &= ~(BXT_MIPI_TX_DIVIDER_MASK(port));
I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
}
--
1.9.1
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^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH] drm/i915/bxt: Additional MIPI clock divider form B0 stepping onwards
2016-02-03 5:21 ` kbuild test robot
@ 2016-02-03 11:16 ` Deepak M
2016-02-04 12:59 ` Jani Nikula
0 siblings, 1 reply; 14+ messages in thread
From: Deepak M @ 2016-02-03 11:16 UTC (permalink / raw)
To: intel-gfx; +Cc: Deepak M
The MIPI clock calculations for the addtional clock
are revised from B0 stepping onwards, the bit definitions
have changed compared to old stepping.
v2: Fixing compilation warning.
Signed-off-by: Deepak M <m.deepak@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 104 +++++++++++++++++------------------
drivers/gpu/drm/i915/intel_dsi_pll.c | 64 ++++++++++++++-------
2 files changed, 95 insertions(+), 73 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c0bd691..2568f35 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7638,6 +7638,57 @@ enum skl_disp_power_wells {
/* MIPI DSI registers */
+#define BXT_MIPI1_RX_LOWER_SHIFT 16
+#define BXT_MIPI2_RX_LOWER_SHIFT 0
+#define BXT_MIPI_RX_LOWER_SHIFT(port) \
+ _MIPI_PORT(port, BXT_MIPI1_RX_LOWER_SHIFT, \
+ BXT_MIPI2_RX_LOWER_SHIFT)
+#define BXT_MIPI1_RX_LOWER_DIVIDER_MASK (3 << 16)
+#define BXT_MIPI2_RX_LOWER_DIVIDER_MASK (3 << 0)
+#define BXT_MIPI_RX_LOWER_DIVIDER_MASK(port) \
+ (3 << BXT_MIPI_RX_LOWER_SHIFT(port))
+#define BXT_MIPI_RX_LOWER_DIVIDER(port, val) \
+ ((val & 3) << BXT_MIPI_RX_LOWER_SHIFT(port))
+
+#define BXT_MIPI1_8X_BY3_SHIFT 19
+#define BXT_MIPI2_8X_BY3_SHIFT 3
+#define BXT_MIPI_8X_BY3_SHIFT(port) \
+ _MIPI_PORT(port, BXT_MIPI1_8X_BY3_SHIFT, \
+ BXT_MIPI2_8X_BY3_SHIFT)
+#define BXT_MIPI1_8X_BY3_DIVIDER_MASK (3 << 19)
+#define BXT_MIPI2_8X_BY3_DIVIDER_MASK (3 << 3)
+#define BXT_MIPI_8X_BY3_DIVIDER_MASK(port) \
+ (3 << BXT_MIPI_8X_BY3_SHIFT(port))
+#define BXT_MIPI_8X_BY3_DIVIDER(port, val) \
+ ((val & 3) << BXT_MIPI_8X_BY3_SHIFT(port))
+
+#define BXT_MIPI1_RX_UPPER_SHIFT 21
+#define BXT_MIPI2_RX_UPPER_SHIFT 5
+#define BXT_MIPI_RX_UPPER_SHIFT(port) \
+ _MIPI_PORT(port, BXT_MIPI1_RX_UPPER_SHIFT, \
+ BXT_MIPI2_RX_UPPER_SHIFT)
+#define BXT_MIPI1_RX_UPPER_DIVIDER_MASK (3 << 21)
+#define BXT_MIPI2_RX_UPPER_DIVIDER_MASK (3 << 5)
+#define BXT_MIPI_RX_UPPER_DIVIDER_MASK(port) \
+ (3 << BXT_MIPI_RX_UPPER_SHIFT(port))
+#define BXT_MIPI_RX_UPPER_DIVIDER(port, val) \
+ ((val & 3) << BXT_MIPI_RX_UPPER_SHIFT(port))
+
+#define BXT_MIPI1_TX_SHIFT 26
+#define BXT_MIPI2_TX_SHIFT 10
+#define BXT_MIPI_TX_SHIFT(port) \
+ _MIPI_PORT(port, BXT_MIPI1_TX_SHIFT, \
+ BXT_MIPI2_TX_SHIFT)
+#define BXT_MIPI1_TX_DIVIDER_MASK (0x3F << 26)
+#define BXT_MIPI2_TX_DIVIDER_MASK (0x3F << 10)
+#define BXT_MIPI_TX_DIVIDER_MASK(port) \
+ (0x3F << BXT_MIPI_TX_SHIFT(port))
+#define BXT_MIPI_TX_DIVIDER(port, val) \
+ ((val & 0x3F) << BXT_MIPI_TX_SHIFT(port))
+
+#define RX_DIVIDER_BIT_1_2 0x3
+#define RX_DIVIDER_BIT_3_4 0xC
+
#define _MIPI_PORT(port, a, c) _PORT3(port, a, 0, c) /* ports A and C only */
#define _MMIO_MIPI(port, a, c) _MMIO(_MIPI_PORT(port, a, c))
@@ -7650,59 +7701,6 @@ enum skl_disp_power_wells {
#define BXT_MIPI_DIV_SHIFT(port) \
_MIPI_PORT(port, BXT_MIPI1_DIV_SHIFT, \
BXT_MIPI2_DIV_SHIFT)
-/* Var clock divider to generate TX source. Result must be < 39.5 M */
-#define BXT_MIPI1_ESCLK_VAR_DIV_MASK (0x3F << 26)
-#define BXT_MIPI2_ESCLK_VAR_DIV_MASK (0x3F << 10)
-#define BXT_MIPI_ESCLK_VAR_DIV_MASK(port) \
- _MIPI_PORT(port, BXT_MIPI1_ESCLK_VAR_DIV_MASK, \
- BXT_MIPI2_ESCLK_VAR_DIV_MASK)
-
-#define BXT_MIPI_ESCLK_VAR_DIV(port, val) \
- (val << BXT_MIPI_DIV_SHIFT(port))
-/* TX control divider to select actual TX clock output from (8x/var) */
-#define BXT_MIPI1_TX_ESCLK_SHIFT 21
-#define BXT_MIPI2_TX_ESCLK_SHIFT 5
-#define BXT_MIPI_TX_ESCLK_SHIFT(port) \
- _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_SHIFT, \
- BXT_MIPI2_TX_ESCLK_SHIFT)
-#define BXT_MIPI1_TX_ESCLK_FIXDIV_MASK (3 << 21)
-#define BXT_MIPI2_TX_ESCLK_FIXDIV_MASK (3 << 5)
-#define BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port) \
- _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_FIXDIV_MASK, \
- BXT_MIPI2_TX_ESCLK_FIXDIV_MASK)
-#define BXT_MIPI_TX_ESCLK_8XDIV_BY2(port) \
- (0x0 << BXT_MIPI_TX_ESCLK_SHIFT(port))
-#define BXT_MIPI_TX_ESCLK_8XDIV_BY4(port) \
- (0x1 << BXT_MIPI_TX_ESCLK_SHIFT(port))
-#define BXT_MIPI_TX_ESCLK_8XDIV_BY8(port) \
- (0x2 << BXT_MIPI_TX_ESCLK_SHIFT(port))
-/* RX control divider to select actual RX clock output from 8x*/
-#define BXT_MIPI1_RX_ESCLK_SHIFT 19
-#define BXT_MIPI2_RX_ESCLK_SHIFT 3
-#define BXT_MIPI_RX_ESCLK_SHIFT(port) \
- _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_SHIFT, \
- BXT_MIPI2_RX_ESCLK_SHIFT)
-#define BXT_MIPI1_RX_ESCLK_FIXDIV_MASK (3 << 19)
-#define BXT_MIPI2_RX_ESCLK_FIXDIV_MASK (3 << 3)
-#define BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port) \
- (3 << BXT_MIPI_RX_ESCLK_SHIFT(port))
-#define BXT_MIPI_RX_ESCLK_8X_BY2(port) \
- (1 << BXT_MIPI_RX_ESCLK_SHIFT(port))
-#define BXT_MIPI_RX_ESCLK_8X_BY3(port) \
- (2 << BXT_MIPI_RX_ESCLK_SHIFT(port))
-#define BXT_MIPI_RX_ESCLK_8X_BY4(port) \
- (3 << BXT_MIPI_RX_ESCLK_SHIFT(port))
-/* BXT-A WA: Always prog DPHY dividers to 00 */
-#define BXT_MIPI1_DPHY_DIV_SHIFT 16
-#define BXT_MIPI2_DPHY_DIV_SHIFT 0
-#define BXT_MIPI_DPHY_DIV_SHIFT(port) \
- _MIPI_PORT(port, BXT_MIPI1_DPHY_DIV_SHIFT, \
- BXT_MIPI2_DPHY_DIV_SHIFT)
-#define BXT_MIPI_1_DPHY_DIVIDER_MASK (3 << 16)
-#define BXT_MIPI_2_DPHY_DIVIDER_MASK (3 << 0)
-#define BXT_MIPI_DPHY_DIVIDER_MASK(port) \
- (3 << BXT_MIPI_DPHY_DIV_SHIFT(port))
-
/* BXT MIPI mode configure */
#define _BXT_MIPIA_TRANS_HACTIVE 0x6B0F8
#define _BXT_MIPIC_TRANS_HACTIVE 0x6B8F8
diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
index bb5e95a..7435115 100644
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -362,35 +362,59 @@ static void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
/* Program BXT Mipi clocks and dividers */
static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port)
{
- u32 tmp;
- u32 divider;
- u32 dsi_rate;
- u32 pll_ratio;
struct drm_i915_private *dev_priv = dev->dev_private;
+ u32 tmp;
+ u32 dsi_rate = 0;
+ u32 pll_ratio = 0;
+ u32 rx_div;
+ u32 tx_div;
+ u32 rx_div_upper;
+ u32 rx_div_lower;
+ u32 mipi_8by3_divider;
/* Clear old configurations */
tmp = I915_READ(BXT_MIPI_CLOCK_CTL);
- tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
- tmp &= ~(BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port));
- tmp &= ~(BXT_MIPI_ESCLK_VAR_DIV_MASK(port));
- tmp &= ~(BXT_MIPI_DPHY_DIVIDER_MASK(port));
+ tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port));
+ tmp &= ~(BXT_MIPI_RX_LOWER_DIVIDER_MASK(port));
+ tmp &= ~(BXT_MIPI_RX_UPPER_DIVIDER_MASK(port));
+ tmp &= ~(BXT_MIPI_TX_DIVIDER_MASK(port));
/* Get the current DSI rate(actual) */
pll_ratio = I915_READ(BXT_DSI_PLL_CTL) &
- BXT_DSI_PLL_RATIO_MASK;
+ BXT_DSI_PLL_RATIO_MASK;
+
+ /* To get 8X clock, divide ref_freq * pll ratio by 2 as per bspec */
dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2;
- /* Max possible output of clock is 39.5 MHz, program value -1 */
- divider = (dsi_rate / BXT_MAX_VAR_OUTPUT_KHZ) - 1;
- tmp |= BXT_MIPI_ESCLK_VAR_DIV(port, divider);
+ /*
+ * tx clock should be <= 20MHz and the div value must be
+ * subtracted by 1 as per bspec
+ */
+ tx_div = DIV_ROUND_UP(dsi_rate, 20000) - 1;
+ /*
+ * rx clock should be <= 150MHz and the div value must be
+ * subtracted by 1 as per bspec
+ */
+ rx_div = DIV_ROUND_UP(dsi_rate, 150000) - 1;
/*
- * Tx escape clock must be as close to 20MHz possible, but should
- * not exceed it. Hence select divide by 2
+ * rx divider value needs to be updated in the
+ * two differnt bit fields in the register hence splitting the
+ * rx divider value accordingly
*/
- tmp |= BXT_MIPI_TX_ESCLK_8XDIV_BY2(port);
+ rx_div_lower = rx_div & RX_DIVIDER_BIT_1_2;
+ rx_div_upper = (rx_div & RX_DIVIDER_BIT_3_4) >> 2;
+
+ /* As per bpsec program the 8/3X clock divider to the below value */
+ if (dev_priv->vbt.dsi.config->is_cmd_mode)
+ mipi_8by3_divider = 0x2;
+ else
+ mipi_8by3_divider = 0x3;
- tmp |= BXT_MIPI_RX_ESCLK_8X_BY3(port);
+ tmp |= BXT_MIPI_8X_BY3_DIVIDER(port, mipi_8by3_divider);
+ tmp |= BXT_MIPI_TX_DIVIDER(port, tx_div);
+ tmp |= BXT_MIPI_RX_LOWER_DIVIDER(port, rx_div_lower);
+ tmp |= BXT_MIPI_RX_UPPER_DIVIDER(port, rx_div_upper);
I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
}
@@ -512,10 +536,10 @@ static void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
/* Clear old configurations */
tmp = I915_READ(BXT_MIPI_CLOCK_CTL);
- tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
- tmp &= ~(BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port));
- tmp &= ~(BXT_MIPI_ESCLK_VAR_DIV_MASK(port));
- tmp &= ~(BXT_MIPI_DPHY_DIVIDER_MASK(port));
+ tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port));
+ tmp &= ~(BXT_MIPI_RX_LOWER_DIVIDER_MASK(port));
+ tmp &= ~(BXT_MIPI_RX_UPPER_DIVIDER_MASK(port));
+ tmp &= ~(BXT_MIPI_TX_DIVIDER_MASK(port));
I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
}
--
1.9.1
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH] drm/i915/bxt: Additional MIPI clock divider form B0 stepping onwards
2016-02-03 11:16 ` [PATCH] " Deepak M
@ 2016-02-04 12:59 ` Jani Nikula
2016-02-04 13:05 ` Deepak, M
0 siblings, 1 reply; 14+ messages in thread
From: Jani Nikula @ 2016-02-04 12:59 UTC (permalink / raw)
To: intel-gfx; +Cc: Deepak M
On Wed, 03 Feb 2016, Deepak M <m.deepak@intel.com> wrote:
> The MIPI clock calculations for the addtional clock
> are revised from B0 stepping onwards, the bit definitions
> have changed compared to old stepping.
>
> v2: Fixing compilation warning.
Why did you move and rename everything when it was not needed?
BR,
Jani.
>
> Signed-off-by: Deepak M <m.deepak@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 104 +++++++++++++++++------------------
> drivers/gpu/drm/i915/intel_dsi_pll.c | 64 ++++++++++++++-------
> 2 files changed, 95 insertions(+), 73 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c0bd691..2568f35 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7638,6 +7638,57 @@ enum skl_disp_power_wells {
>
> /* MIPI DSI registers */
>
> +#define BXT_MIPI1_RX_LOWER_SHIFT 16
> +#define BXT_MIPI2_RX_LOWER_SHIFT 0
> +#define BXT_MIPI_RX_LOWER_SHIFT(port) \
> + _MIPI_PORT(port, BXT_MIPI1_RX_LOWER_SHIFT, \
> + BXT_MIPI2_RX_LOWER_SHIFT)
> +#define BXT_MIPI1_RX_LOWER_DIVIDER_MASK (3 << 16)
> +#define BXT_MIPI2_RX_LOWER_DIVIDER_MASK (3 << 0)
> +#define BXT_MIPI_RX_LOWER_DIVIDER_MASK(port) \
> + (3 << BXT_MIPI_RX_LOWER_SHIFT(port))
> +#define BXT_MIPI_RX_LOWER_DIVIDER(port, val) \
> + ((val & 3) << BXT_MIPI_RX_LOWER_SHIFT(port))
> +
> +#define BXT_MIPI1_8X_BY3_SHIFT 19
> +#define BXT_MIPI2_8X_BY3_SHIFT 3
> +#define BXT_MIPI_8X_BY3_SHIFT(port) \
> + _MIPI_PORT(port, BXT_MIPI1_8X_BY3_SHIFT, \
> + BXT_MIPI2_8X_BY3_SHIFT)
> +#define BXT_MIPI1_8X_BY3_DIVIDER_MASK (3 << 19)
> +#define BXT_MIPI2_8X_BY3_DIVIDER_MASK (3 << 3)
> +#define BXT_MIPI_8X_BY3_DIVIDER_MASK(port) \
> + (3 << BXT_MIPI_8X_BY3_SHIFT(port))
> +#define BXT_MIPI_8X_BY3_DIVIDER(port, val) \
> + ((val & 3) << BXT_MIPI_8X_BY3_SHIFT(port))
> +
> +#define BXT_MIPI1_RX_UPPER_SHIFT 21
> +#define BXT_MIPI2_RX_UPPER_SHIFT 5
> +#define BXT_MIPI_RX_UPPER_SHIFT(port) \
> + _MIPI_PORT(port, BXT_MIPI1_RX_UPPER_SHIFT, \
> + BXT_MIPI2_RX_UPPER_SHIFT)
> +#define BXT_MIPI1_RX_UPPER_DIVIDER_MASK (3 << 21)
> +#define BXT_MIPI2_RX_UPPER_DIVIDER_MASK (3 << 5)
> +#define BXT_MIPI_RX_UPPER_DIVIDER_MASK(port) \
> + (3 << BXT_MIPI_RX_UPPER_SHIFT(port))
> +#define BXT_MIPI_RX_UPPER_DIVIDER(port, val) \
> + ((val & 3) << BXT_MIPI_RX_UPPER_SHIFT(port))
> +
> +#define BXT_MIPI1_TX_SHIFT 26
> +#define BXT_MIPI2_TX_SHIFT 10
> +#define BXT_MIPI_TX_SHIFT(port) \
> + _MIPI_PORT(port, BXT_MIPI1_TX_SHIFT, \
> + BXT_MIPI2_TX_SHIFT)
> +#define BXT_MIPI1_TX_DIVIDER_MASK (0x3F << 26)
> +#define BXT_MIPI2_TX_DIVIDER_MASK (0x3F << 10)
> +#define BXT_MIPI_TX_DIVIDER_MASK(port) \
> + (0x3F << BXT_MIPI_TX_SHIFT(port))
> +#define BXT_MIPI_TX_DIVIDER(port, val) \
> + ((val & 0x3F) << BXT_MIPI_TX_SHIFT(port))
> +
> +#define RX_DIVIDER_BIT_1_2 0x3
> +#define RX_DIVIDER_BIT_3_4 0xC
> +
> #define _MIPI_PORT(port, a, c) _PORT3(port, a, 0, c) /* ports A and C only */
> #define _MMIO_MIPI(port, a, c) _MMIO(_MIPI_PORT(port, a, c))
>
> @@ -7650,59 +7701,6 @@ enum skl_disp_power_wells {
> #define BXT_MIPI_DIV_SHIFT(port) \
> _MIPI_PORT(port, BXT_MIPI1_DIV_SHIFT, \
> BXT_MIPI2_DIV_SHIFT)
> -/* Var clock divider to generate TX source. Result must be < 39.5 M */
> -#define BXT_MIPI1_ESCLK_VAR_DIV_MASK (0x3F << 26)
> -#define BXT_MIPI2_ESCLK_VAR_DIV_MASK (0x3F << 10)
> -#define BXT_MIPI_ESCLK_VAR_DIV_MASK(port) \
> - _MIPI_PORT(port, BXT_MIPI1_ESCLK_VAR_DIV_MASK, \
> - BXT_MIPI2_ESCLK_VAR_DIV_MASK)
> -
> -#define BXT_MIPI_ESCLK_VAR_DIV(port, val) \
> - (val << BXT_MIPI_DIV_SHIFT(port))
> -/* TX control divider to select actual TX clock output from (8x/var) */
> -#define BXT_MIPI1_TX_ESCLK_SHIFT 21
> -#define BXT_MIPI2_TX_ESCLK_SHIFT 5
> -#define BXT_MIPI_TX_ESCLK_SHIFT(port) \
> - _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_SHIFT, \
> - BXT_MIPI2_TX_ESCLK_SHIFT)
> -#define BXT_MIPI1_TX_ESCLK_FIXDIV_MASK (3 << 21)
> -#define BXT_MIPI2_TX_ESCLK_FIXDIV_MASK (3 << 5)
> -#define BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port) \
> - _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_FIXDIV_MASK, \
> - BXT_MIPI2_TX_ESCLK_FIXDIV_MASK)
> -#define BXT_MIPI_TX_ESCLK_8XDIV_BY2(port) \
> - (0x0 << BXT_MIPI_TX_ESCLK_SHIFT(port))
> -#define BXT_MIPI_TX_ESCLK_8XDIV_BY4(port) \
> - (0x1 << BXT_MIPI_TX_ESCLK_SHIFT(port))
> -#define BXT_MIPI_TX_ESCLK_8XDIV_BY8(port) \
> - (0x2 << BXT_MIPI_TX_ESCLK_SHIFT(port))
> -/* RX control divider to select actual RX clock output from 8x*/
> -#define BXT_MIPI1_RX_ESCLK_SHIFT 19
> -#define BXT_MIPI2_RX_ESCLK_SHIFT 3
> -#define BXT_MIPI_RX_ESCLK_SHIFT(port) \
> - _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_SHIFT, \
> - BXT_MIPI2_RX_ESCLK_SHIFT)
> -#define BXT_MIPI1_RX_ESCLK_FIXDIV_MASK (3 << 19)
> -#define BXT_MIPI2_RX_ESCLK_FIXDIV_MASK (3 << 3)
> -#define BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port) \
> - (3 << BXT_MIPI_RX_ESCLK_SHIFT(port))
> -#define BXT_MIPI_RX_ESCLK_8X_BY2(port) \
> - (1 << BXT_MIPI_RX_ESCLK_SHIFT(port))
> -#define BXT_MIPI_RX_ESCLK_8X_BY3(port) \
> - (2 << BXT_MIPI_RX_ESCLK_SHIFT(port))
> -#define BXT_MIPI_RX_ESCLK_8X_BY4(port) \
> - (3 << BXT_MIPI_RX_ESCLK_SHIFT(port))
> -/* BXT-A WA: Always prog DPHY dividers to 00 */
> -#define BXT_MIPI1_DPHY_DIV_SHIFT 16
> -#define BXT_MIPI2_DPHY_DIV_SHIFT 0
> -#define BXT_MIPI_DPHY_DIV_SHIFT(port) \
> - _MIPI_PORT(port, BXT_MIPI1_DPHY_DIV_SHIFT, \
> - BXT_MIPI2_DPHY_DIV_SHIFT)
> -#define BXT_MIPI_1_DPHY_DIVIDER_MASK (3 << 16)
> -#define BXT_MIPI_2_DPHY_DIVIDER_MASK (3 << 0)
> -#define BXT_MIPI_DPHY_DIVIDER_MASK(port) \
> - (3 << BXT_MIPI_DPHY_DIV_SHIFT(port))
> -
> /* BXT MIPI mode configure */
> #define _BXT_MIPIA_TRANS_HACTIVE 0x6B0F8
> #define _BXT_MIPIC_TRANS_HACTIVE 0x6B8F8
> diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
> index bb5e95a..7435115 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
> @@ -362,35 +362,59 @@ static void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
> /* Program BXT Mipi clocks and dividers */
> static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port)
> {
> - u32 tmp;
> - u32 divider;
> - u32 dsi_rate;
> - u32 pll_ratio;
> struct drm_i915_private *dev_priv = dev->dev_private;
> + u32 tmp;
> + u32 dsi_rate = 0;
> + u32 pll_ratio = 0;
> + u32 rx_div;
> + u32 tx_div;
> + u32 rx_div_upper;
> + u32 rx_div_lower;
> + u32 mipi_8by3_divider;
>
> /* Clear old configurations */
> tmp = I915_READ(BXT_MIPI_CLOCK_CTL);
> - tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
> - tmp &= ~(BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port));
> - tmp &= ~(BXT_MIPI_ESCLK_VAR_DIV_MASK(port));
> - tmp &= ~(BXT_MIPI_DPHY_DIVIDER_MASK(port));
> + tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port));
> + tmp &= ~(BXT_MIPI_RX_LOWER_DIVIDER_MASK(port));
> + tmp &= ~(BXT_MIPI_RX_UPPER_DIVIDER_MASK(port));
> + tmp &= ~(BXT_MIPI_TX_DIVIDER_MASK(port));
>
> /* Get the current DSI rate(actual) */
> pll_ratio = I915_READ(BXT_DSI_PLL_CTL) &
> - BXT_DSI_PLL_RATIO_MASK;
> + BXT_DSI_PLL_RATIO_MASK;
> +
> + /* To get 8X clock, divide ref_freq * pll ratio by 2 as per bspec */
> dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2;
>
> - /* Max possible output of clock is 39.5 MHz, program value -1 */
> - divider = (dsi_rate / BXT_MAX_VAR_OUTPUT_KHZ) - 1;
> - tmp |= BXT_MIPI_ESCLK_VAR_DIV(port, divider);
> + /*
> + * tx clock should be <= 20MHz and the div value must be
> + * subtracted by 1 as per bspec
> + */
> + tx_div = DIV_ROUND_UP(dsi_rate, 20000) - 1;
> + /*
> + * rx clock should be <= 150MHz and the div value must be
> + * subtracted by 1 as per bspec
> + */
> + rx_div = DIV_ROUND_UP(dsi_rate, 150000) - 1;
>
> /*
> - * Tx escape clock must be as close to 20MHz possible, but should
> - * not exceed it. Hence select divide by 2
> + * rx divider value needs to be updated in the
> + * two differnt bit fields in the register hence splitting the
> + * rx divider value accordingly
> */
> - tmp |= BXT_MIPI_TX_ESCLK_8XDIV_BY2(port);
> + rx_div_lower = rx_div & RX_DIVIDER_BIT_1_2;
> + rx_div_upper = (rx_div & RX_DIVIDER_BIT_3_4) >> 2;
> +
> + /* As per bpsec program the 8/3X clock divider to the below value */
> + if (dev_priv->vbt.dsi.config->is_cmd_mode)
> + mipi_8by3_divider = 0x2;
> + else
> + mipi_8by3_divider = 0x3;
>
> - tmp |= BXT_MIPI_RX_ESCLK_8X_BY3(port);
> + tmp |= BXT_MIPI_8X_BY3_DIVIDER(port, mipi_8by3_divider);
> + tmp |= BXT_MIPI_TX_DIVIDER(port, tx_div);
> + tmp |= BXT_MIPI_RX_LOWER_DIVIDER(port, rx_div_lower);
> + tmp |= BXT_MIPI_RX_UPPER_DIVIDER(port, rx_div_upper);
>
> I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
> }
> @@ -512,10 +536,10 @@ static void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
>
> /* Clear old configurations */
> tmp = I915_READ(BXT_MIPI_CLOCK_CTL);
> - tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
> - tmp &= ~(BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port));
> - tmp &= ~(BXT_MIPI_ESCLK_VAR_DIV_MASK(port));
> - tmp &= ~(BXT_MIPI_DPHY_DIVIDER_MASK(port));
> + tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port));
> + tmp &= ~(BXT_MIPI_RX_LOWER_DIVIDER_MASK(port));
> + tmp &= ~(BXT_MIPI_RX_UPPER_DIVIDER_MASK(port));
> + tmp &= ~(BXT_MIPI_TX_DIVIDER_MASK(port));
> I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
> I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
> }
--
Jani Nikula, Intel Open Source Technology Center
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Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH] drm/i915/bxt: Additional MIPI clock divider form B0 stepping onwards
2016-02-04 12:59 ` Jani Nikula
@ 2016-02-04 13:05 ` Deepak, M
2016-02-04 13:57 ` Jani Nikula
0 siblings, 1 reply; 14+ messages in thread
From: Deepak, M @ 2016-02-04 13:05 UTC (permalink / raw)
To: Jani Nikula, intel-gfx
> -----Original Message-----
> From: Jani Nikula [mailto:jani.nikula@linux.intel.com]
> Sent: Thursday, February 4, 2016 6:29 PM
> To: Deepak, M <m.deepak@intel.com>; intel-gfx@lists.freedesktop.org
> Cc: Deepak, M <m.deepak@intel.com>
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/bxt: Additional MIPI clock divider
> form B0 stepping onwards
>
> On Wed, 03 Feb 2016, Deepak M <m.deepak@intel.com> wrote:
> > The MIPI clock calculations for the addtional clock are revised from
> > B0 stepping onwards, the bit definitions have changed compared to old
> > stepping.
> >
> > v2: Fixing compilation warning.
>
> Why did you move and rename everything when it was not needed?
>
> BR,
> Jani.
>
[Deepak, M] I have deleted the old macro and added the new as per the new definitions. With the new bit fields nothing was matching as that of the old.
>
> >
> > Signed-off-by: Deepak M <m.deepak@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 104 +++++++++++++++++------------
> ------
> > drivers/gpu/drm/i915/intel_dsi_pll.c | 64 ++++++++++++++-------
> > 2 files changed, 95 insertions(+), 73 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h index c0bd691..2568f35 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -7638,6 +7638,57 @@ enum skl_disp_power_wells {
> >
> > /* MIPI DSI registers */
> >
> > +#define BXT_MIPI1_RX_LOWER_SHIFT 16
> > +#define BXT_MIPI2_RX_LOWER_SHIFT 0
> > +#define BXT_MIPI_RX_LOWER_SHIFT(port) \
> > + _MIPI_PORT(port, BXT_MIPI1_RX_LOWER_SHIFT, \
> > + BXT_MIPI2_RX_LOWER_SHIFT)
> > +#define BXT_MIPI1_RX_LOWER_DIVIDER_MASK (3 << 16)
> > +#define BXT_MIPI2_RX_LOWER_DIVIDER_MASK (3 << 0)
> > +#define BXT_MIPI_RX_LOWER_DIVIDER_MASK(port) \
> > + (3 << BXT_MIPI_RX_LOWER_SHIFT(port))
> > +#define BXT_MIPI_RX_LOWER_DIVIDER(port, val) \
> > + ((val & 3) << BXT_MIPI_RX_LOWER_SHIFT(port))
> > +
> > +#define BXT_MIPI1_8X_BY3_SHIFT 19
> > +#define BXT_MIPI2_8X_BY3_SHIFT 3
> > +#define BXT_MIPI_8X_BY3_SHIFT(port) \
> > + _MIPI_PORT(port, BXT_MIPI1_8X_BY3_SHIFT, \
> > + BXT_MIPI2_8X_BY3_SHIFT)
> > +#define BXT_MIPI1_8X_BY3_DIVIDER_MASK (3 << 19)
> > +#define BXT_MIPI2_8X_BY3_DIVIDER_MASK (3 << 3)
> > +#define BXT_MIPI_8X_BY3_DIVIDER_MASK(port) \
> > + (3 << BXT_MIPI_8X_BY3_SHIFT(port))
> > +#define BXT_MIPI_8X_BY3_DIVIDER(port, val) \
> > + ((val & 3) << BXT_MIPI_8X_BY3_SHIFT(port))
> > +
> > +#define BXT_MIPI1_RX_UPPER_SHIFT 21
> > +#define BXT_MIPI2_RX_UPPER_SHIFT 5
> > +#define BXT_MIPI_RX_UPPER_SHIFT(port) \
> > + _MIPI_PORT(port, BXT_MIPI1_RX_UPPER_SHIFT, \
> > + BXT_MIPI2_RX_UPPER_SHIFT)
> > +#define BXT_MIPI1_RX_UPPER_DIVIDER_MASK (3 << 21)
> > +#define BXT_MIPI2_RX_UPPER_DIVIDER_MASK (3 << 5)
> > +#define BXT_MIPI_RX_UPPER_DIVIDER_MASK(port) \
> > + (3 << BXT_MIPI_RX_UPPER_SHIFT(port))
> > +#define BXT_MIPI_RX_UPPER_DIVIDER(port, val) \
> > + ((val & 3) << BXT_MIPI_RX_UPPER_SHIFT(port))
> > +
> > +#define BXT_MIPI1_TX_SHIFT 26
> > +#define BXT_MIPI2_TX_SHIFT 10
> > +#define BXT_MIPI_TX_SHIFT(port) \
> > + _MIPI_PORT(port, BXT_MIPI1_TX_SHIFT, \
> > + BXT_MIPI2_TX_SHIFT)
> > +#define BXT_MIPI1_TX_DIVIDER_MASK (0x3F << 26)
> > +#define BXT_MIPI2_TX_DIVIDER_MASK (0x3F << 10)
> > +#define BXT_MIPI_TX_DIVIDER_MASK(port) \
> > + (0x3F << BXT_MIPI_TX_SHIFT(port))
> > +#define BXT_MIPI_TX_DIVIDER(port, val) \
> > + ((val & 0x3F) << BXT_MIPI_TX_SHIFT(port))
> > +
> > +#define RX_DIVIDER_BIT_1_2 0x3
> > +#define RX_DIVIDER_BIT_3_4 0xC
> > +
> > #define _MIPI_PORT(port, a, c) _PORT3(port, a, 0, c) /* ports A
> and C only */
> > #define _MMIO_MIPI(port, a, c) _MMIO(_MIPI_PORT(port, a, c))
> >
> > @@ -7650,59 +7701,6 @@ enum skl_disp_power_wells {
> > #define BXT_MIPI_DIV_SHIFT(port) \
> > _MIPI_PORT(port, BXT_MIPI1_DIV_SHIFT, \
> > BXT_MIPI2_DIV_SHIFT)
> > -/* Var clock divider to generate TX source. Result must be < 39.5 M */
> > -#define BXT_MIPI1_ESCLK_VAR_DIV_MASK (0x3F << 26)
> > -#define BXT_MIPI2_ESCLK_VAR_DIV_MASK (0x3F << 10)
> > -#define BXT_MIPI_ESCLK_VAR_DIV_MASK(port) \
> > - _MIPI_PORT(port,
> BXT_MIPI1_ESCLK_VAR_DIV_MASK, \
> > -
> BXT_MIPI2_ESCLK_VAR_DIV_MASK)
> > -
> > -#define BXT_MIPI_ESCLK_VAR_DIV(port, val) \
> > - (val << BXT_MIPI_DIV_SHIFT(port))
> > -/* TX control divider to select actual TX clock output from (8x/var) */
> > -#define BXT_MIPI1_TX_ESCLK_SHIFT 21
> > -#define BXT_MIPI2_TX_ESCLK_SHIFT 5
> > -#define BXT_MIPI_TX_ESCLK_SHIFT(port) \
> > - _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_SHIFT, \
> > - BXT_MIPI2_TX_ESCLK_SHIFT)
> > -#define BXT_MIPI1_TX_ESCLK_FIXDIV_MASK (3 << 21)
> > -#define BXT_MIPI2_TX_ESCLK_FIXDIV_MASK (3 << 5)
> > -#define BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port) \
> > - _MIPI_PORT(port,
> BXT_MIPI1_TX_ESCLK_FIXDIV_MASK, \
> > -
> BXT_MIPI2_TX_ESCLK_FIXDIV_MASK)
> > -#define BXT_MIPI_TX_ESCLK_8XDIV_BY2(port) \
> > - (0x0 << BXT_MIPI_TX_ESCLK_SHIFT(port))
> > -#define BXT_MIPI_TX_ESCLK_8XDIV_BY4(port) \
> > - (0x1 << BXT_MIPI_TX_ESCLK_SHIFT(port))
> > -#define BXT_MIPI_TX_ESCLK_8XDIV_BY8(port) \
> > - (0x2 << BXT_MIPI_TX_ESCLK_SHIFT(port))
> > -/* RX control divider to select actual RX clock output from 8x*/
> > -#define BXT_MIPI1_RX_ESCLK_SHIFT 19
> > -#define BXT_MIPI2_RX_ESCLK_SHIFT 3
> > -#define BXT_MIPI_RX_ESCLK_SHIFT(port) \
> > - _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_SHIFT, \
> > - BXT_MIPI2_RX_ESCLK_SHIFT)
> > -#define BXT_MIPI1_RX_ESCLK_FIXDIV_MASK (3 << 19)
> > -#define BXT_MIPI2_RX_ESCLK_FIXDIV_MASK (3 << 3)
> > -#define BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port) \
> > - (3 << BXT_MIPI_RX_ESCLK_SHIFT(port))
> > -#define BXT_MIPI_RX_ESCLK_8X_BY2(port) \
> > - (1 << BXT_MIPI_RX_ESCLK_SHIFT(port))
> > -#define BXT_MIPI_RX_ESCLK_8X_BY3(port) \
> > - (2 << BXT_MIPI_RX_ESCLK_SHIFT(port))
> > -#define BXT_MIPI_RX_ESCLK_8X_BY4(port) \
> > - (3 << BXT_MIPI_RX_ESCLK_SHIFT(port))
> > -/* BXT-A WA: Always prog DPHY dividers to 00 */
> > -#define BXT_MIPI1_DPHY_DIV_SHIFT 16
> > -#define BXT_MIPI2_DPHY_DIV_SHIFT 0
> > -#define BXT_MIPI_DPHY_DIV_SHIFT(port) \
> > - _MIPI_PORT(port, BXT_MIPI1_DPHY_DIV_SHIFT, \
> > - BXT_MIPI2_DPHY_DIV_SHIFT)
> > -#define BXT_MIPI_1_DPHY_DIVIDER_MASK (3 << 16)
> > -#define BXT_MIPI_2_DPHY_DIVIDER_MASK (3 << 0)
> > -#define BXT_MIPI_DPHY_DIVIDER_MASK(port) \
> > - (3 << BXT_MIPI_DPHY_DIV_SHIFT(port))
> > -
> > /* BXT MIPI mode configure */
> > #define _BXT_MIPIA_TRANS_HACTIVE 0x6B0F8
> > #define _BXT_MIPIC_TRANS_HACTIVE 0x6B8F8
> > diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c
> > b/drivers/gpu/drm/i915/intel_dsi_pll.c
> > index bb5e95a..7435115 100644
> > --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
> > +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
> > @@ -362,35 +362,59 @@ static void vlv_dsi_reset_clocks(struct
> > intel_encoder *encoder, enum port port)
> > /* Program BXT Mipi clocks and dividers */ static void
> > bxt_dsi_program_clocks(struct drm_device *dev, enum port port) {
> > - u32 tmp;
> > - u32 divider;
> > - u32 dsi_rate;
> > - u32 pll_ratio;
> > struct drm_i915_private *dev_priv = dev->dev_private;
> > + u32 tmp;
> > + u32 dsi_rate = 0;
> > + u32 pll_ratio = 0;
> > + u32 rx_div;
> > + u32 tx_div;
> > + u32 rx_div_upper;
> > + u32 rx_div_lower;
> > + u32 mipi_8by3_divider;
> >
> > /* Clear old configurations */
> > tmp = I915_READ(BXT_MIPI_CLOCK_CTL);
> > - tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
> > - tmp &= ~(BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port));
> > - tmp &= ~(BXT_MIPI_ESCLK_VAR_DIV_MASK(port));
> > - tmp &= ~(BXT_MIPI_DPHY_DIVIDER_MASK(port));
> > + tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port));
> > + tmp &= ~(BXT_MIPI_RX_LOWER_DIVIDER_MASK(port));
> > + tmp &= ~(BXT_MIPI_RX_UPPER_DIVIDER_MASK(port));
> > + tmp &= ~(BXT_MIPI_TX_DIVIDER_MASK(port));
> >
> > /* Get the current DSI rate(actual) */
> > pll_ratio = I915_READ(BXT_DSI_PLL_CTL) &
> > - BXT_DSI_PLL_RATIO_MASK;
> > + BXT_DSI_PLL_RATIO_MASK;
> > +
> > + /* To get 8X clock, divide ref_freq * pll ratio by 2 as per bspec */
> > dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2;
> >
> > - /* Max possible output of clock is 39.5 MHz, program value -1 */
> > - divider = (dsi_rate / BXT_MAX_VAR_OUTPUT_KHZ) - 1;
> > - tmp |= BXT_MIPI_ESCLK_VAR_DIV(port, divider);
> > + /*
> > + * tx clock should be <= 20MHz and the div value must be
> > + * subtracted by 1 as per bspec
> > + */
> > + tx_div = DIV_ROUND_UP(dsi_rate, 20000) - 1;
> > + /*
> > + * rx clock should be <= 150MHz and the div value must be
> > + * subtracted by 1 as per bspec
> > + */
> > + rx_div = DIV_ROUND_UP(dsi_rate, 150000) - 1;
> >
> > /*
> > - * Tx escape clock must be as close to 20MHz possible, but should
> > - * not exceed it. Hence select divide by 2
> > + * rx divider value needs to be updated in the
> > + * two differnt bit fields in the register hence splitting the
> > + * rx divider value accordingly
> > */
> > - tmp |= BXT_MIPI_TX_ESCLK_8XDIV_BY2(port);
> > + rx_div_lower = rx_div & RX_DIVIDER_BIT_1_2;
> > + rx_div_upper = (rx_div & RX_DIVIDER_BIT_3_4) >> 2;
> > +
> > + /* As per bpsec program the 8/3X clock divider to the below value */
> > + if (dev_priv->vbt.dsi.config->is_cmd_mode)
> > + mipi_8by3_divider = 0x2;
> > + else
> > + mipi_8by3_divider = 0x3;
> >
> > - tmp |= BXT_MIPI_RX_ESCLK_8X_BY3(port);
> > + tmp |= BXT_MIPI_8X_BY3_DIVIDER(port, mipi_8by3_divider);
> > + tmp |= BXT_MIPI_TX_DIVIDER(port, tx_div);
> > + tmp |= BXT_MIPI_RX_LOWER_DIVIDER(port, rx_div_lower);
> > + tmp |= BXT_MIPI_RX_UPPER_DIVIDER(port, rx_div_upper);
> >
> > I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp); } @@ -512,10 +536,10
> @@ static
> > void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port
> > port)
> >
> > /* Clear old configurations */
> > tmp = I915_READ(BXT_MIPI_CLOCK_CTL);
> > - tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
> > - tmp &= ~(BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port));
> > - tmp &= ~(BXT_MIPI_ESCLK_VAR_DIV_MASK(port));
> > - tmp &= ~(BXT_MIPI_DPHY_DIVIDER_MASK(port));
> > + tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port));
> > + tmp &= ~(BXT_MIPI_RX_LOWER_DIVIDER_MASK(port));
> > + tmp &= ~(BXT_MIPI_RX_UPPER_DIVIDER_MASK(port));
> > + tmp &= ~(BXT_MIPI_TX_DIVIDER_MASK(port));
> > I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
> > I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP); }
>
> --
> Jani Nikula, Intel Open Source Technology Center
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Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
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^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH] drm/i915/bxt: Additional MIPI clock divider form B0 stepping onwards
2016-02-04 13:05 ` Deepak, M
@ 2016-02-04 13:57 ` Jani Nikula
2016-02-04 15:12 ` Deepak, M
2016-02-15 17:13 ` Deepak M
0 siblings, 2 replies; 14+ messages in thread
From: Jani Nikula @ 2016-02-04 13:57 UTC (permalink / raw)
To: Deepak, M, intel-gfx
On Thu, 04 Feb 2016, "Deepak, M" <m.deepak@intel.com> wrote:
>> -----Original Message-----
>> From: Jani Nikula [mailto:jani.nikula@linux.intel.com]
>> Sent: Thursday, February 4, 2016 6:29 PM
>> To: Deepak, M <m.deepak@intel.com>; intel-gfx@lists.freedesktop.org
>> Cc: Deepak, M <m.deepak@intel.com>
>> Subject: Re: [Intel-gfx] [PATCH] drm/i915/bxt: Additional MIPI clock divider
>> form B0 stepping onwards
>>
>> On Wed, 03 Feb 2016, Deepak M <m.deepak@intel.com> wrote:
>> > The MIPI clock calculations for the addtional clock are revised from
>> > B0 stepping onwards, the bit definitions have changed compared to old
>> > stepping.
>> >
>> > v2: Fixing compilation warning.
>>
>> Why did you move and rename everything when it was not needed?
>>
>> BR,
>> Jani.
>>
> [Deepak, M] I have deleted the old macro and added the new as per the new definitions. With the new bit fields nothing was matching as that of the old.
It's not nothing. Plenty of masks and shifts matched, but you had
renamed the defines.
Besides, please don't move the definitions where they don't belong. We
also have the convention of specifying the bits from highest to lowest.
>>
>> >
>> > Signed-off-by: Deepak M <m.deepak@intel.com>
>> > ---
>> > drivers/gpu/drm/i915/i915_reg.h | 104 +++++++++++++++++------------
>> ------
>> > drivers/gpu/drm/i915/intel_dsi_pll.c | 64 ++++++++++++++-------
>> > 2 files changed, 95 insertions(+), 73 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
>> > b/drivers/gpu/drm/i915/i915_reg.h index c0bd691..2568f35 100644
>> > --- a/drivers/gpu/drm/i915/i915_reg.h
>> > +++ b/drivers/gpu/drm/i915/i915_reg.h
>> > @@ -7638,6 +7638,57 @@ enum skl_disp_power_wells {
>> >
>> > /* MIPI DSI registers */
>> >
>> > +#define BXT_MIPI1_RX_LOWER_SHIFT 16
>> > +#define BXT_MIPI2_RX_LOWER_SHIFT 0
>> > +#define BXT_MIPI_RX_LOWER_SHIFT(port) \
>> > + _MIPI_PORT(port, BXT_MIPI1_RX_LOWER_SHIFT, \
>> > + BXT_MIPI2_RX_LOWER_SHIFT)
>> > +#define BXT_MIPI1_RX_LOWER_DIVIDER_MASK (3 << 16)
>> > +#define BXT_MIPI2_RX_LOWER_DIVIDER_MASK (3 << 0)
>> > +#define BXT_MIPI_RX_LOWER_DIVIDER_MASK(port) \
>> > + (3 << BXT_MIPI_RX_LOWER_SHIFT(port))
>> > +#define BXT_MIPI_RX_LOWER_DIVIDER(port, val) \
>> > + ((val & 3) << BXT_MIPI_RX_LOWER_SHIFT(port))
>> > +
>> > +#define BXT_MIPI1_8X_BY3_SHIFT 19
>> > +#define BXT_MIPI2_8X_BY3_SHIFT 3
>> > +#define BXT_MIPI_8X_BY3_SHIFT(port) \
>> > + _MIPI_PORT(port, BXT_MIPI1_8X_BY3_SHIFT, \
>> > + BXT_MIPI2_8X_BY3_SHIFT)
>> > +#define BXT_MIPI1_8X_BY3_DIVIDER_MASK (3 << 19)
>> > +#define BXT_MIPI2_8X_BY3_DIVIDER_MASK (3 << 3)
>> > +#define BXT_MIPI_8X_BY3_DIVIDER_MASK(port) \
>> > + (3 << BXT_MIPI_8X_BY3_SHIFT(port))
>> > +#define BXT_MIPI_8X_BY3_DIVIDER(port, val) \
>> > + ((val & 3) << BXT_MIPI_8X_BY3_SHIFT(port))
>> > +
>> > +#define BXT_MIPI1_RX_UPPER_SHIFT 21
>> > +#define BXT_MIPI2_RX_UPPER_SHIFT 5
>> > +#define BXT_MIPI_RX_UPPER_SHIFT(port) \
>> > + _MIPI_PORT(port, BXT_MIPI1_RX_UPPER_SHIFT, \
>> > + BXT_MIPI2_RX_UPPER_SHIFT)
>> > +#define BXT_MIPI1_RX_UPPER_DIVIDER_MASK (3 << 21)
>> > +#define BXT_MIPI2_RX_UPPER_DIVIDER_MASK (3 << 5)
>> > +#define BXT_MIPI_RX_UPPER_DIVIDER_MASK(port) \
>> > + (3 << BXT_MIPI_RX_UPPER_SHIFT(port))
>> > +#define BXT_MIPI_RX_UPPER_DIVIDER(port, val) \
>> > + ((val & 3) << BXT_MIPI_RX_UPPER_SHIFT(port))
>> > +
>> > +#define BXT_MIPI1_TX_SHIFT 26
>> > +#define BXT_MIPI2_TX_SHIFT 10
>> > +#define BXT_MIPI_TX_SHIFT(port) \
>> > + _MIPI_PORT(port, BXT_MIPI1_TX_SHIFT, \
>> > + BXT_MIPI2_TX_SHIFT)
>> > +#define BXT_MIPI1_TX_DIVIDER_MASK (0x3F << 26)
>> > +#define BXT_MIPI2_TX_DIVIDER_MASK (0x3F << 10)
>> > +#define BXT_MIPI_TX_DIVIDER_MASK(port) \
>> > + (0x3F << BXT_MIPI_TX_SHIFT(port))
>> > +#define BXT_MIPI_TX_DIVIDER(port, val) \
>> > + ((val & 0x3F) << BXT_MIPI_TX_SHIFT(port))
>> > +
>> > +#define RX_DIVIDER_BIT_1_2 0x3
>> > +#define RX_DIVIDER_BIT_3_4 0xC
>> > +
>> > #define _MIPI_PORT(port, a, c) _PORT3(port, a, 0, c) /* ports A
>> and C only */
>> > #define _MMIO_MIPI(port, a, c) _MMIO(_MIPI_PORT(port, a, c))
>> >
>> > @@ -7650,59 +7701,6 @@ enum skl_disp_power_wells {
>> > #define BXT_MIPI_DIV_SHIFT(port) \
>> > _MIPI_PORT(port, BXT_MIPI1_DIV_SHIFT, \
>> > BXT_MIPI2_DIV_SHIFT)
>> > -/* Var clock divider to generate TX source. Result must be < 39.5 M */
>> > -#define BXT_MIPI1_ESCLK_VAR_DIV_MASK (0x3F << 26)
>> > -#define BXT_MIPI2_ESCLK_VAR_DIV_MASK (0x3F << 10)
>> > -#define BXT_MIPI_ESCLK_VAR_DIV_MASK(port) \
>> > - _MIPI_PORT(port,
>> BXT_MIPI1_ESCLK_VAR_DIV_MASK, \
>> > -
>> BXT_MIPI2_ESCLK_VAR_DIV_MASK)
>> > -
>> > -#define BXT_MIPI_ESCLK_VAR_DIV(port, val) \
>> > - (val << BXT_MIPI_DIV_SHIFT(port))
>> > -/* TX control divider to select actual TX clock output from (8x/var) */
>> > -#define BXT_MIPI1_TX_ESCLK_SHIFT 21
>> > -#define BXT_MIPI2_TX_ESCLK_SHIFT 5
>> > -#define BXT_MIPI_TX_ESCLK_SHIFT(port) \
>> > - _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_SHIFT, \
>> > - BXT_MIPI2_TX_ESCLK_SHIFT)
>> > -#define BXT_MIPI1_TX_ESCLK_FIXDIV_MASK (3 << 21)
>> > -#define BXT_MIPI2_TX_ESCLK_FIXDIV_MASK (3 << 5)
>> > -#define BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port) \
>> > - _MIPI_PORT(port,
>> BXT_MIPI1_TX_ESCLK_FIXDIV_MASK, \
>> > -
>> BXT_MIPI2_TX_ESCLK_FIXDIV_MASK)
>> > -#define BXT_MIPI_TX_ESCLK_8XDIV_BY2(port) \
>> > - (0x0 << BXT_MIPI_TX_ESCLK_SHIFT(port))
>> > -#define BXT_MIPI_TX_ESCLK_8XDIV_BY4(port) \
>> > - (0x1 << BXT_MIPI_TX_ESCLK_SHIFT(port))
>> > -#define BXT_MIPI_TX_ESCLK_8XDIV_BY8(port) \
>> > - (0x2 << BXT_MIPI_TX_ESCLK_SHIFT(port))
>> > -/* RX control divider to select actual RX clock output from 8x*/
>> > -#define BXT_MIPI1_RX_ESCLK_SHIFT 19
>> > -#define BXT_MIPI2_RX_ESCLK_SHIFT 3
>> > -#define BXT_MIPI_RX_ESCLK_SHIFT(port) \
>> > - _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_SHIFT, \
>> > - BXT_MIPI2_RX_ESCLK_SHIFT)
>> > -#define BXT_MIPI1_RX_ESCLK_FIXDIV_MASK (3 << 19)
>> > -#define BXT_MIPI2_RX_ESCLK_FIXDIV_MASK (3 << 3)
>> > -#define BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port) \
>> > - (3 << BXT_MIPI_RX_ESCLK_SHIFT(port))
>> > -#define BXT_MIPI_RX_ESCLK_8X_BY2(port) \
>> > - (1 << BXT_MIPI_RX_ESCLK_SHIFT(port))
>> > -#define BXT_MIPI_RX_ESCLK_8X_BY3(port) \
>> > - (2 << BXT_MIPI_RX_ESCLK_SHIFT(port))
>> > -#define BXT_MIPI_RX_ESCLK_8X_BY4(port) \
>> > - (3 << BXT_MIPI_RX_ESCLK_SHIFT(port))
>> > -/* BXT-A WA: Always prog DPHY dividers to 00 */
>> > -#define BXT_MIPI1_DPHY_DIV_SHIFT 16
>> > -#define BXT_MIPI2_DPHY_DIV_SHIFT 0
>> > -#define BXT_MIPI_DPHY_DIV_SHIFT(port) \
>> > - _MIPI_PORT(port, BXT_MIPI1_DPHY_DIV_SHIFT, \
>> > - BXT_MIPI2_DPHY_DIV_SHIFT)
>> > -#define BXT_MIPI_1_DPHY_DIVIDER_MASK (3 << 16)
>> > -#define BXT_MIPI_2_DPHY_DIVIDER_MASK (3 << 0)
>> > -#define BXT_MIPI_DPHY_DIVIDER_MASK(port) \
>> > - (3 << BXT_MIPI_DPHY_DIV_SHIFT(port))
>> > -
>> > /* BXT MIPI mode configure */
>> > #define _BXT_MIPIA_TRANS_HACTIVE 0x6B0F8
>> > #define _BXT_MIPIC_TRANS_HACTIVE 0x6B8F8
>> > diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c
>> > b/drivers/gpu/drm/i915/intel_dsi_pll.c
>> > index bb5e95a..7435115 100644
>> > --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
>> > +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
>> > @@ -362,35 +362,59 @@ static void vlv_dsi_reset_clocks(struct
>> > intel_encoder *encoder, enum port port)
>> > /* Program BXT Mipi clocks and dividers */ static void
>> > bxt_dsi_program_clocks(struct drm_device *dev, enum port port) {
>> > - u32 tmp;
>> > - u32 divider;
>> > - u32 dsi_rate;
>> > - u32 pll_ratio;
>> > struct drm_i915_private *dev_priv = dev->dev_private;
>> > + u32 tmp;
>> > + u32 dsi_rate = 0;
>> > + u32 pll_ratio = 0;
>> > + u32 rx_div;
>> > + u32 tx_div;
>> > + u32 rx_div_upper;
>> > + u32 rx_div_lower;
>> > + u32 mipi_8by3_divider;
>> >
>> > /* Clear old configurations */
>> > tmp = I915_READ(BXT_MIPI_CLOCK_CTL);
>> > - tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
>> > - tmp &= ~(BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port));
>> > - tmp &= ~(BXT_MIPI_ESCLK_VAR_DIV_MASK(port));
>> > - tmp &= ~(BXT_MIPI_DPHY_DIVIDER_MASK(port));
>> > + tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port));
>> > + tmp &= ~(BXT_MIPI_RX_LOWER_DIVIDER_MASK(port));
>> > + tmp &= ~(BXT_MIPI_RX_UPPER_DIVIDER_MASK(port));
>> > + tmp &= ~(BXT_MIPI_TX_DIVIDER_MASK(port));
>> >
>> > /* Get the current DSI rate(actual) */
>> > pll_ratio = I915_READ(BXT_DSI_PLL_CTL) &
>> > - BXT_DSI_PLL_RATIO_MASK;
>> > + BXT_DSI_PLL_RATIO_MASK;
>> > +
>> > + /* To get 8X clock, divide ref_freq * pll ratio by 2 as per bspec */
>> > dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2;
>> >
>> > - /* Max possible output of clock is 39.5 MHz, program value -1 */
>> > - divider = (dsi_rate / BXT_MAX_VAR_OUTPUT_KHZ) - 1;
>> > - tmp |= BXT_MIPI_ESCLK_VAR_DIV(port, divider);
>> > + /*
>> > + * tx clock should be <= 20MHz and the div value must be
>> > + * subtracted by 1 as per bspec
>> > + */
>> > + tx_div = DIV_ROUND_UP(dsi_rate, 20000) - 1;
>> > + /*
>> > + * rx clock should be <= 150MHz and the div value must be
>> > + * subtracted by 1 as per bspec
>> > + */
>> > + rx_div = DIV_ROUND_UP(dsi_rate, 150000) - 1;
>> >
>> > /*
>> > - * Tx escape clock must be as close to 20MHz possible, but should
>> > - * not exceed it. Hence select divide by 2
>> > + * rx divider value needs to be updated in the
>> > + * two differnt bit fields in the register hence splitting the
>> > + * rx divider value accordingly
>> > */
>> > - tmp |= BXT_MIPI_TX_ESCLK_8XDIV_BY2(port);
>> > + rx_div_lower = rx_div & RX_DIVIDER_BIT_1_2;
>> > + rx_div_upper = (rx_div & RX_DIVIDER_BIT_3_4) >> 2;
>> > +
>> > + /* As per bpsec program the 8/3X clock divider to the below value */
>> > + if (dev_priv->vbt.dsi.config->is_cmd_mode)
>> > + mipi_8by3_divider = 0x2;
>> > + else
>> > + mipi_8by3_divider = 0x3;
>> >
>> > - tmp |= BXT_MIPI_RX_ESCLK_8X_BY3(port);
>> > + tmp |= BXT_MIPI_8X_BY3_DIVIDER(port, mipi_8by3_divider);
>> > + tmp |= BXT_MIPI_TX_DIVIDER(port, tx_div);
>> > + tmp |= BXT_MIPI_RX_LOWER_DIVIDER(port, rx_div_lower);
>> > + tmp |= BXT_MIPI_RX_UPPER_DIVIDER(port, rx_div_upper);
>> >
>> > I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp); } @@ -512,10 +536,10
>> @@ static
>> > void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port
>> > port)
>> >
>> > /* Clear old configurations */
>> > tmp = I915_READ(BXT_MIPI_CLOCK_CTL);
>> > - tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
>> > - tmp &= ~(BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port));
>> > - tmp &= ~(BXT_MIPI_ESCLK_VAR_DIV_MASK(port));
>> > - tmp &= ~(BXT_MIPI_DPHY_DIVIDER_MASK(port));
>> > + tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port));
>> > + tmp &= ~(BXT_MIPI_RX_LOWER_DIVIDER_MASK(port));
>> > + tmp &= ~(BXT_MIPI_RX_UPPER_DIVIDER_MASK(port));
>> > + tmp &= ~(BXT_MIPI_TX_DIVIDER_MASK(port));
>> > I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
>> > I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP); }
>>
>> --
>> Jani Nikula, Intel Open Source Technology Center
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH] drm/i915/bxt: Additional MIPI clock divider form B0 stepping onwards
2016-02-04 13:57 ` Jani Nikula
@ 2016-02-04 15:12 ` Deepak, M
2016-02-15 17:13 ` Deepak M
1 sibling, 0 replies; 14+ messages in thread
From: Deepak, M @ 2016-02-04 15:12 UTC (permalink / raw)
To: Jani Nikula, intel-gfx
> -----Original Message-----
> From: Jani Nikula [mailto:jani.nikula@linux.intel.com]
> Sent: Thursday, February 4, 2016 7:28 PM
> To: Deepak, M <m.deepak@intel.com>; intel-gfx@lists.freedesktop.org
> Subject: RE: [Intel-gfx] [PATCH] drm/i915/bxt: Additional MIPI clock divider
> form B0 stepping onwards
>
> On Thu, 04 Feb 2016, "Deepak, M" <m.deepak@intel.com> wrote:
> >> -----Original Message-----
> >> From: Jani Nikula [mailto:jani.nikula@linux.intel.com]
> >> Sent: Thursday, February 4, 2016 6:29 PM
> >> To: Deepak, M <m.deepak@intel.com>; intel-gfx@lists.freedesktop.org
> >> Cc: Deepak, M <m.deepak@intel.com>
> >> Subject: Re: [Intel-gfx] [PATCH] drm/i915/bxt: Additional MIPI clock
> >> divider form B0 stepping onwards
> >>
> >> On Wed, 03 Feb 2016, Deepak M <m.deepak@intel.com> wrote:
> >> > The MIPI clock calculations for the addtional clock are revised
> >> > from
> >> > B0 stepping onwards, the bit definitions have changed compared to
> >> > old stepping.
> >> >
> >> > v2: Fixing compilation warning.
> >>
> >> Why did you move and rename everything when it was not needed?
> >>
> >> BR,
> >> Jani.
> >>
> > [Deepak, M] I have deleted the old macro and added the new as per the
> new definitions. With the new bit fields nothing was matching as that of the
> old.
>
> It's not nothing. Plenty of masks and shifts matched, but you had renamed
> the defines.
>
> Besides, please don't move the definitions where they don't belong. We also
> have the convention of specifying the bits from highest to lowest.
>
[Deepak, M] Okay, will fix the macro`s, are there any changes required in the function.
> >>
> >> >
> >> > Signed-off-by: Deepak M <m.deepak@intel.com>
> >> > ---
> >> > drivers/gpu/drm/i915/i915_reg.h | 104 +++++++++++++++++---------
> ---
> >> ------
> >> > drivers/gpu/drm/i915/intel_dsi_pll.c | 64 ++++++++++++++-------
> >> > 2 files changed, 95 insertions(+), 73 deletions(-)
> >> >
> >> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> >> > b/drivers/gpu/drm/i915/i915_reg.h index c0bd691..2568f35 100644
> >> > --- a/drivers/gpu/drm/i915/i915_reg.h
> >> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> >> > @@ -7638,6 +7638,57 @@ enum skl_disp_power_wells {
> >> >
> >> > /* MIPI DSI registers */
> >> >
> >> > +#define BXT_MIPI1_RX_LOWER_SHIFT 16
> >> > +#define BXT_MIPI2_RX_LOWER_SHIFT 0
> >> > +#define BXT_MIPI_RX_LOWER_SHIFT(port) \
> >> > + _MIPI_PORT(port, BXT_MIPI1_RX_LOWER_SHIFT, \
> >> > + BXT_MIPI2_RX_LOWER_SHIFT)
> >> > +#define BXT_MIPI1_RX_LOWER_DIVIDER_MASK (3 << 16)
> >> > +#define BXT_MIPI2_RX_LOWER_DIVIDER_MASK (3 << 0)
> >> > +#define BXT_MIPI_RX_LOWER_DIVIDER_MASK(port) \
> >> > + (3 << BXT_MIPI_RX_LOWER_SHIFT(port))
> >> > +#define BXT_MIPI_RX_LOWER_DIVIDER(port, val) \
> >> > + ((val & 3) << BXT_MIPI_RX_LOWER_SHIFT(port))
> >> > +
> >> > +#define BXT_MIPI1_8X_BY3_SHIFT 19
> >> > +#define BXT_MIPI2_8X_BY3_SHIFT 3
> >> > +#define BXT_MIPI_8X_BY3_SHIFT(port) \
> >> > + _MIPI_PORT(port, BXT_MIPI1_8X_BY3_SHIFT, \
> >> > + BXT_MIPI2_8X_BY3_SHIFT)
> >> > +#define BXT_MIPI1_8X_BY3_DIVIDER_MASK (3 << 19)
> >> > +#define BXT_MIPI2_8X_BY3_DIVIDER_MASK (3 << 3)
> >> > +#define BXT_MIPI_8X_BY3_DIVIDER_MASK(port) \
> >> > + (3 << BXT_MIPI_8X_BY3_SHIFT(port))
> >> > +#define BXT_MIPI_8X_BY3_DIVIDER(port, val) \
> >> > + ((val & 3) << BXT_MIPI_8X_BY3_SHIFT(port))
> >> > +
> >> > +#define BXT_MIPI1_RX_UPPER_SHIFT 21
> >> > +#define BXT_MIPI2_RX_UPPER_SHIFT 5
> >> > +#define BXT_MIPI_RX_UPPER_SHIFT(port) \
> >> > + _MIPI_PORT(port, BXT_MIPI1_RX_UPPER_SHIFT, \
> >> > + BXT_MIPI2_RX_UPPER_SHIFT)
> >> > +#define BXT_MIPI1_RX_UPPER_DIVIDER_MASK (3 << 21)
> >> > +#define BXT_MIPI2_RX_UPPER_DIVIDER_MASK (3 << 5)
> >> > +#define BXT_MIPI_RX_UPPER_DIVIDER_MASK(port) \
> >> > + (3 << BXT_MIPI_RX_UPPER_SHIFT(port))
> >> > +#define BXT_MIPI_RX_UPPER_DIVIDER(port, val) \
> >> > + ((val & 3) << BXT_MIPI_RX_UPPER_SHIFT(port))
> >> > +
> >> > +#define BXT_MIPI1_TX_SHIFT 26
> >> > +#define BXT_MIPI2_TX_SHIFT 10
> >> > +#define BXT_MIPI_TX_SHIFT(port) \
> >> > + _MIPI_PORT(port, BXT_MIPI1_TX_SHIFT, \
> >> > + BXT_MIPI2_TX_SHIFT)
> >> > +#define BXT_MIPI1_TX_DIVIDER_MASK (0x3F << 26)
> >> > +#define BXT_MIPI2_TX_DIVIDER_MASK (0x3F << 10)
> >> > +#define BXT_MIPI_TX_DIVIDER_MASK(port) \
> >> > + (0x3F << BXT_MIPI_TX_SHIFT(port))
> >> > +#define BXT_MIPI_TX_DIVIDER(port, val) \
> >> > + ((val & 0x3F) << BXT_MIPI_TX_SHIFT(port))
> >> > +
> >> > +#define RX_DIVIDER_BIT_1_2 0x3
> >> > +#define RX_DIVIDER_BIT_3_4 0xC
> >> > +
> >> > #define _MIPI_PORT(port, a, c) _PORT3(port, a, 0, c) /* ports A
> >> and C only */
> >> > #define _MMIO_MIPI(port, a, c) _MMIO(_MIPI_PORT(port, a, c))
> >> >
> >> > @@ -7650,59 +7701,6 @@ enum skl_disp_power_wells {
> >> > #define BXT_MIPI_DIV_SHIFT(port) \
> >> > _MIPI_PORT(port, BXT_MIPI1_DIV_SHIFT, \
> >> > BXT_MIPI2_DIV_SHIFT)
> >> > -/* Var clock divider to generate TX source. Result must be < 39.5 M */
> >> > -#define BXT_MIPI1_ESCLK_VAR_DIV_MASK (0x3F << 26)
> >> > -#define BXT_MIPI2_ESCLK_VAR_DIV_MASK (0x3F << 10)
> >> > -#define BXT_MIPI_ESCLK_VAR_DIV_MASK(port) \
> >> > - _MIPI_PORT(port,
> >> BXT_MIPI1_ESCLK_VAR_DIV_MASK, \
> >> > -
> >> BXT_MIPI2_ESCLK_VAR_DIV_MASK)
> >> > -
> >> > -#define BXT_MIPI_ESCLK_VAR_DIV(port, val) \
> >> > - (val << BXT_MIPI_DIV_SHIFT(port))
> >> > -/* TX control divider to select actual TX clock output from (8x/var) */
> >> > -#define BXT_MIPI1_TX_ESCLK_SHIFT 21
> >> > -#define BXT_MIPI2_TX_ESCLK_SHIFT 5
> >> > -#define BXT_MIPI_TX_ESCLK_SHIFT(port) \
> >> > - _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_SHIFT, \
> >> > - BXT_MIPI2_TX_ESCLK_SHIFT)
> >> > -#define BXT_MIPI1_TX_ESCLK_FIXDIV_MASK (3 << 21)
> >> > -#define BXT_MIPI2_TX_ESCLK_FIXDIV_MASK (3 << 5)
> >> > -#define BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port) \
> >> > - _MIPI_PORT(port,
> >> BXT_MIPI1_TX_ESCLK_FIXDIV_MASK, \
> >> > -
> >> BXT_MIPI2_TX_ESCLK_FIXDIV_MASK)
> >> > -#define BXT_MIPI_TX_ESCLK_8XDIV_BY2(port) \
> >> > - (0x0 << BXT_MIPI_TX_ESCLK_SHIFT(port))
> >> > -#define BXT_MIPI_TX_ESCLK_8XDIV_BY4(port) \
> >> > - (0x1 << BXT_MIPI_TX_ESCLK_SHIFT(port))
> >> > -#define BXT_MIPI_TX_ESCLK_8XDIV_BY8(port) \
> >> > - (0x2 << BXT_MIPI_TX_ESCLK_SHIFT(port))
> >> > -/* RX control divider to select actual RX clock output from 8x*/
> >> > -#define BXT_MIPI1_RX_ESCLK_SHIFT 19
> >> > -#define BXT_MIPI2_RX_ESCLK_SHIFT 3
> >> > -#define BXT_MIPI_RX_ESCLK_SHIFT(port) \
> >> > - _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_SHIFT, \
> >> > - BXT_MIPI2_RX_ESCLK_SHIFT)
> >> > -#define BXT_MIPI1_RX_ESCLK_FIXDIV_MASK (3 << 19)
> >> > -#define BXT_MIPI2_RX_ESCLK_FIXDIV_MASK (3 << 3)
> >> > -#define BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port) \
> >> > - (3 << BXT_MIPI_RX_ESCLK_SHIFT(port))
> >> > -#define BXT_MIPI_RX_ESCLK_8X_BY2(port) \
> >> > - (1 << BXT_MIPI_RX_ESCLK_SHIFT(port))
> >> > -#define BXT_MIPI_RX_ESCLK_8X_BY3(port) \
> >> > - (2 << BXT_MIPI_RX_ESCLK_SHIFT(port))
> >> > -#define BXT_MIPI_RX_ESCLK_8X_BY4(port) \
> >> > - (3 << BXT_MIPI_RX_ESCLK_SHIFT(port))
> >> > -/* BXT-A WA: Always prog DPHY dividers to 00 */
> >> > -#define BXT_MIPI1_DPHY_DIV_SHIFT 16
> >> > -#define BXT_MIPI2_DPHY_DIV_SHIFT 0
> >> > -#define BXT_MIPI_DPHY_DIV_SHIFT(port) \
> >> > - _MIPI_PORT(port, BXT_MIPI1_DPHY_DIV_SHIFT, \
> >> > - BXT_MIPI2_DPHY_DIV_SHIFT)
> >> > -#define BXT_MIPI_1_DPHY_DIVIDER_MASK (3 << 16)
> >> > -#define BXT_MIPI_2_DPHY_DIVIDER_MASK (3 << 0)
> >> > -#define BXT_MIPI_DPHY_DIVIDER_MASK(port) \
> >> > - (3 << BXT_MIPI_DPHY_DIV_SHIFT(port))
> >> > -
> >> > /* BXT MIPI mode configure */
> >> > #define _BXT_MIPIA_TRANS_HACTIVE 0x6B0F8
> >> > #define _BXT_MIPIC_TRANS_HACTIVE 0x6B8F8
> >> > diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c
> >> > b/drivers/gpu/drm/i915/intel_dsi_pll.c
> >> > index bb5e95a..7435115 100644
> >> > --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
> >> > +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
> >> > @@ -362,35 +362,59 @@ static void vlv_dsi_reset_clocks(struct
> >> > intel_encoder *encoder, enum port port)
> >> > /* Program BXT Mipi clocks and dividers */ static void
> >> > bxt_dsi_program_clocks(struct drm_device *dev, enum port port) {
> >> > - u32 tmp;
> >> > - u32 divider;
> >> > - u32 dsi_rate;
> >> > - u32 pll_ratio;
> >> > struct drm_i915_private *dev_priv = dev->dev_private;
> >> > + u32 tmp;
> >> > + u32 dsi_rate = 0;
> >> > + u32 pll_ratio = 0;
> >> > + u32 rx_div;
> >> > + u32 tx_div;
> >> > + u32 rx_div_upper;
> >> > + u32 rx_div_lower;
> >> > + u32 mipi_8by3_divider;
> >> >
> >> > /* Clear old configurations */
> >> > tmp = I915_READ(BXT_MIPI_CLOCK_CTL);
> >> > - tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
> >> > - tmp &= ~(BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port));
> >> > - tmp &= ~(BXT_MIPI_ESCLK_VAR_DIV_MASK(port));
> >> > - tmp &= ~(BXT_MIPI_DPHY_DIVIDER_MASK(port));
> >> > + tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port));
> >> > + tmp &= ~(BXT_MIPI_RX_LOWER_DIVIDER_MASK(port));
> >> > + tmp &= ~(BXT_MIPI_RX_UPPER_DIVIDER_MASK(port));
> >> > + tmp &= ~(BXT_MIPI_TX_DIVIDER_MASK(port));
> >> >
> >> > /* Get the current DSI rate(actual) */
> >> > pll_ratio = I915_READ(BXT_DSI_PLL_CTL) &
> >> > - BXT_DSI_PLL_RATIO_MASK;
> >> > + BXT_DSI_PLL_RATIO_MASK;
> >> > +
> >> > + /* To get 8X clock, divide ref_freq * pll ratio by 2 as per bspec
> >> > +*/
> >> > dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2;
> >> >
> >> > - /* Max possible output of clock is 39.5 MHz, program value -1 */
> >> > - divider = (dsi_rate / BXT_MAX_VAR_OUTPUT_KHZ) - 1;
> >> > - tmp |= BXT_MIPI_ESCLK_VAR_DIV(port, divider);
> >> > + /*
> >> > + * tx clock should be <= 20MHz and the div value must be
> >> > + * subtracted by 1 as per bspec
> >> > + */
> >> > + tx_div = DIV_ROUND_UP(dsi_rate, 20000) - 1;
> >> > + /*
> >> > + * rx clock should be <= 150MHz and the div value must be
> >> > + * subtracted by 1 as per bspec
> >> > + */
> >> > + rx_div = DIV_ROUND_UP(dsi_rate, 150000) - 1;
> >> >
> >> > /*
> >> > - * Tx escape clock must be as close to 20MHz possible, but should
> >> > - * not exceed it. Hence select divide by 2
> >> > + * rx divider value needs to be updated in the
> >> > + * two differnt bit fields in the register hence splitting the
> >> > + * rx divider value accordingly
> >> > */
> >> > - tmp |= BXT_MIPI_TX_ESCLK_8XDIV_BY2(port);
> >> > + rx_div_lower = rx_div & RX_DIVIDER_BIT_1_2;
> >> > + rx_div_upper = (rx_div & RX_DIVIDER_BIT_3_4) >> 2;
> >> > +
> >> > + /* As per bpsec program the 8/3X clock divider to the below value */
> >> > + if (dev_priv->vbt.dsi.config->is_cmd_mode)
> >> > + mipi_8by3_divider = 0x2;
> >> > + else
> >> > + mipi_8by3_divider = 0x3;
> >> >
> >> > - tmp |= BXT_MIPI_RX_ESCLK_8X_BY3(port);
> >> > + tmp |= BXT_MIPI_8X_BY3_DIVIDER(port, mipi_8by3_divider);
> >> > + tmp |= BXT_MIPI_TX_DIVIDER(port, tx_div);
> >> > + tmp |= BXT_MIPI_RX_LOWER_DIVIDER(port, rx_div_lower);
> >> > + tmp |= BXT_MIPI_RX_UPPER_DIVIDER(port, rx_div_upper);
> >> >
> >> > I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp); } @@ -512,10 +536,10
> >> @@ static
> >> > void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port
> >> > port)
> >> >
> >> > /* Clear old configurations */
> >> > tmp = I915_READ(BXT_MIPI_CLOCK_CTL);
> >> > - tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
> >> > - tmp &= ~(BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port));
> >> > - tmp &= ~(BXT_MIPI_ESCLK_VAR_DIV_MASK(port));
> >> > - tmp &= ~(BXT_MIPI_DPHY_DIVIDER_MASK(port));
> >> > + tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port));
> >> > + tmp &= ~(BXT_MIPI_RX_LOWER_DIVIDER_MASK(port));
> >> > + tmp &= ~(BXT_MIPI_RX_UPPER_DIVIDER_MASK(port));
> >> > + tmp &= ~(BXT_MIPI_TX_DIVIDER_MASK(port));
> >> > I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
> >> > I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP); }
> >>
> >> --
> >> Jani Nikula, Intel Open Source Technology Center
>
> --
> Jani Nikula, Intel Open Source Technology Center
_______________________________________________
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^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH] drm/i915/bxt: Additional MIPI clock divider form B0 stepping onwards
2016-02-04 13:57 ` Jani Nikula
2016-02-04 15:12 ` Deepak, M
@ 2016-02-15 17:13 ` Deepak M
2016-02-17 20:30 ` Jani Nikula
1 sibling, 1 reply; 14+ messages in thread
From: Deepak M @ 2016-02-15 17:13 UTC (permalink / raw)
To: intel-gfx; +Cc: Deepak M
The MIPI clock calculations for the addtional clock
are revised from B0 stepping onwards, the bit definitions
have changed compared to old stepping.
v2: Fixing compilation warning.
v3: Retained the old Macros (Jani)
Signed-off-by: Deepak M <m.deepak@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 96 +++++++++++++++++++-----------------
drivers/gpu/drm/i915/intel_dsi_pll.c | 56 ++++++++++++++-------
2 files changed, 89 insertions(+), 63 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 144586e..4e61b06 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7663,58 +7663,62 @@ enum skl_disp_power_wells {
#define BXT_MIPI_DIV_SHIFT(port) \
_MIPI_PORT(port, BXT_MIPI1_DIV_SHIFT, \
BXT_MIPI2_DIV_SHIFT)
-/* Var clock divider to generate TX source. Result must be < 39.5 M */
-#define BXT_MIPI1_ESCLK_VAR_DIV_MASK (0x3F << 26)
-#define BXT_MIPI2_ESCLK_VAR_DIV_MASK (0x3F << 10)
-#define BXT_MIPI_ESCLK_VAR_DIV_MASK(port) \
- _MIPI_PORT(port, BXT_MIPI1_ESCLK_VAR_DIV_MASK, \
- BXT_MIPI2_ESCLK_VAR_DIV_MASK)
-
-#define BXT_MIPI_ESCLK_VAR_DIV(port, val) \
- (val << BXT_MIPI_DIV_SHIFT(port))
+
/* TX control divider to select actual TX clock output from (8x/var) */
-#define BXT_MIPI1_TX_ESCLK_SHIFT 21
-#define BXT_MIPI2_TX_ESCLK_SHIFT 5
+#define BXT_MIPI1_TX_ESCLK_SHIFT 26
+#define BXT_MIPI2_TX_ESCLK_SHIFT 10
#define BXT_MIPI_TX_ESCLK_SHIFT(port) \
_MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_SHIFT, \
BXT_MIPI2_TX_ESCLK_SHIFT)
-#define BXT_MIPI1_TX_ESCLK_FIXDIV_MASK (3 << 21)
-#define BXT_MIPI2_TX_ESCLK_FIXDIV_MASK (3 << 5)
+#define BXT_MIPI1_TX_ESCLK_FIXDIV_MASK (0x3F << 26)
+#define BXT_MIPI2_TX_ESCLK_FIXDIV_MASK (0x3F << 10)
#define BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port) \
_MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_FIXDIV_MASK, \
- BXT_MIPI2_TX_ESCLK_FIXDIV_MASK)
-#define BXT_MIPI_TX_ESCLK_8XDIV_BY2(port) \
- (0x0 << BXT_MIPI_TX_ESCLK_SHIFT(port))
-#define BXT_MIPI_TX_ESCLK_8XDIV_BY4(port) \
- (0x1 << BXT_MIPI_TX_ESCLK_SHIFT(port))
-#define BXT_MIPI_TX_ESCLK_8XDIV_BY8(port) \
- (0x2 << BXT_MIPI_TX_ESCLK_SHIFT(port))
-/* RX control divider to select actual RX clock output from 8x*/
-#define BXT_MIPI1_RX_ESCLK_SHIFT 19
-#define BXT_MIPI2_RX_ESCLK_SHIFT 3
-#define BXT_MIPI_RX_ESCLK_SHIFT(port) \
- _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_SHIFT, \
- BXT_MIPI2_RX_ESCLK_SHIFT)
-#define BXT_MIPI1_RX_ESCLK_FIXDIV_MASK (3 << 19)
-#define BXT_MIPI2_RX_ESCLK_FIXDIV_MASK (3 << 3)
-#define BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port) \
- (3 << BXT_MIPI_RX_ESCLK_SHIFT(port))
-#define BXT_MIPI_RX_ESCLK_8X_BY2(port) \
- (1 << BXT_MIPI_RX_ESCLK_SHIFT(port))
-#define BXT_MIPI_RX_ESCLK_8X_BY3(port) \
- (2 << BXT_MIPI_RX_ESCLK_SHIFT(port))
-#define BXT_MIPI_RX_ESCLK_8X_BY4(port) \
- (3 << BXT_MIPI_RX_ESCLK_SHIFT(port))
-/* BXT-A WA: Always prog DPHY dividers to 00 */
-#define BXT_MIPI1_DPHY_DIV_SHIFT 16
-#define BXT_MIPI2_DPHY_DIV_SHIFT 0
-#define BXT_MIPI_DPHY_DIV_SHIFT(port) \
- _MIPI_PORT(port, BXT_MIPI1_DPHY_DIV_SHIFT, \
- BXT_MIPI2_DPHY_DIV_SHIFT)
-#define BXT_MIPI_1_DPHY_DIVIDER_MASK (3 << 16)
-#define BXT_MIPI_2_DPHY_DIVIDER_MASK (3 << 0)
-#define BXT_MIPI_DPHY_DIVIDER_MASK(port) \
- (3 << BXT_MIPI_DPHY_DIV_SHIFT(port))
+ BXT_MIPI2_TX_ESCLK_FIXDIV_MASK)
+#define BXT_MIPI_TX_ESCLK_DIVIDER(port, val) \
+ ((val & 0x3F) << BXT_MIPI_TX_ESCLK_SHIFT(port))
+/* RX upper control divider to select actual RX clock output from 8x*/
+#define BXT_MIPI1_RX_ESCLK_UPPER_SHIFT 21
+#define BXT_MIPI2_RX_ESCLK_UPPER_SHIFT 5
+#define BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port) \
+ _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_SHIFT, \
+ BXT_MIPI2_RX_ESCLK_UPPER_SHIFT)
+#define BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK (3 << 21)
+#define BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK (3 << 5)
+#define BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port) \
+ _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK,\
+ BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK)
+#define BXT_MIPI_RX_ESCLK_UPPER_DIVIDER(port, val) \
+ ((val & 3) << BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port))
+/* 8/3X divider to select the actual 8/3X clock output from 8x*/
+#define BXT_MIPI1_8X_BY3_SHIFT 19
+#define BXT_MIPI2_8X_BY3_SHIFT 3
+#define BXT_MIPI_8X_BY3_SHIFT(port) \
+ _MIPI_PORT(port, BXT_MIPI1_8X_BY3_SHIFT, \
+ BXT_MIPI2_8X_BY3_SHIFT)
+#define BXT_MIPI1_8X_BY3_DIVIDER_MASK (3 << 19)
+#define BXT_MIPI2_8X_BY3_DIVIDER_MASK (3 << 3)
+#define BXT_MIPI_8X_BY3_DIVIDER_MASK(port) \
+ _MIPI_PORT(port, BXT_MIPI1_8X_BY3_DIVIDER_MASK, \
+ BXT_MIPI2_8X_BY3_DIVIDER_MASK)
+#define BXT_MIPI_8X_BY3_DIVIDER(port, val) \
+ ((val & 3) << BXT_MIPI_8X_BY3_SHIFT(port))
+/* RX lower control divider to select actual RX clock output from 8x*/
+#define BXT_MIPI1_RX_ESCLK_LOWER_SHIFT 16
+#define BXT_MIPI2_RX_ESCLK_LOWER_SHIFT 0
+#define BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port) \
+ _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_SHIFT, \
+ BXT_MIPI2_RX_ESCLK_LOWER_SHIFT)
+#define BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK (3 << 16)
+#define BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK (3 << 0)
+#define BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port) \
+ _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK, \
+ BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK)
+#define BXT_MIPI_RX_ESCLK_LOWER_DIVIDER(port, val) \
+ ((val & 3) << BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port))
+
+#define RX_DIVIDER_BIT_1_2 0x3
+#define RX_DIVIDER_BIT_3_4 0xC
/* BXT MIPI mode configure */
#define _BXT_MIPIA_TRANS_HACTIVE 0x6B0F8
diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
index bb5e95a..02aeae5 100644
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -362,35 +362,57 @@ static void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
/* Program BXT Mipi clocks and dividers */
static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port)
{
- u32 tmp;
- u32 divider;
- u32 dsi_rate;
- u32 pll_ratio;
struct drm_i915_private *dev_priv = dev->dev_private;
+ u32 tmp;
+ u32 dsi_rate = 0;
+ u32 pll_ratio = 0;
+ u32 rx_div;
+ u32 tx_div;
+ u32 rx_div_upper;
+ u32 rx_div_lower;
+ u32 mipi_8by3_divider;
/* Clear old configurations */
tmp = I915_READ(BXT_MIPI_CLOCK_CTL);
tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
- tmp &= ~(BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port));
- tmp &= ~(BXT_MIPI_ESCLK_VAR_DIV_MASK(port));
- tmp &= ~(BXT_MIPI_DPHY_DIVIDER_MASK(port));
+ tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port));
+ tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port));
+ tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port));
/* Get the current DSI rate(actual) */
pll_ratio = I915_READ(BXT_DSI_PLL_CTL) &
BXT_DSI_PLL_RATIO_MASK;
dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2;
- /* Max possible output of clock is 39.5 MHz, program value -1 */
- divider = (dsi_rate / BXT_MAX_VAR_OUTPUT_KHZ) - 1;
- tmp |= BXT_MIPI_ESCLK_VAR_DIV(port, divider);
+ /*
+ * tx clock should be <= 20MHz and the div value must be
+ * subtracted by 1 as per bspec
+ */
+ tx_div = DIV_ROUND_UP(dsi_rate, 20000) - 1;
+ /*
+ * rx clock should be <= 150MHz and the div value must be
+ * subtracted by 1 as per bspec
+ */
+ rx_div = DIV_ROUND_UP(dsi_rate, 150000) - 1;
/*
- * Tx escape clock must be as close to 20MHz possible, but should
- * not exceed it. Hence select divide by 2
+ * rx divider value needs to be updated in the
+ * two differnt bit fields in the register hence splitting the
+ * rx divider value accordingly
*/
- tmp |= BXT_MIPI_TX_ESCLK_8XDIV_BY2(port);
+ rx_div_lower = rx_div & RX_DIVIDER_BIT_1_2;
+ rx_div_upper = (rx_div & RX_DIVIDER_BIT_3_4) >> 2;
+
+ /* As per bpsec program the 8/3X clock divider to the below value */
+ if (dev_priv->vbt.dsi.config->is_cmd_mode)
+ mipi_8by3_divider = 0x2;
+ else
+ mipi_8by3_divider = 0x3;
- tmp |= BXT_MIPI_RX_ESCLK_8X_BY3(port);
+ tmp |= BXT_MIPI_8X_BY3_DIVIDER(port, mipi_8by3_divider);
+ tmp |= BXT_MIPI_TX_ESCLK_DIVIDER(port, tx_div);
+ tmp |= BXT_MIPI_RX_ESCLK_LOWER_DIVIDER(port, rx_div_lower);
+ tmp |= BXT_MIPI_RX_ESCLK_UPPER_DIVIDER(port, rx_div_upper);
I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
}
@@ -513,9 +535,9 @@ static void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
/* Clear old configurations */
tmp = I915_READ(BXT_MIPI_CLOCK_CTL);
tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
- tmp &= ~(BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port));
- tmp &= ~(BXT_MIPI_ESCLK_VAR_DIV_MASK(port));
- tmp &= ~(BXT_MIPI_DPHY_DIVIDER_MASK(port));
+ tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port));
+ tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port));
+ tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port));
I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
}
--
1.9.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915/bxt: Additional MIPI clock divider form B0 stepping onwards (rev3)
2016-02-03 10:43 [APL PO PATCH] drm/i915/bxt: Additional MIPI clock divider form B0 stepping onwards Deepak M
2016-02-03 5:21 ` kbuild test robot
2016-02-03 9:47 ` ✓ Fi.CI.BAT: success for drm/i915/bxt: Additional MIPI clock divider form B0 stepping onwards (rev2) Patchwork
@ 2016-02-16 10:39 ` Patchwork
2 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2016-02-16 10:39 UTC (permalink / raw)
To: Deepak M; +Cc: intel-gfx
== Summary ==
Series 3034v3 drm/i915/bxt: Additional MIPI clock divider form B0 stepping onwards
http://patchwork.freedesktop.org/api/1.0/series/3034/revisions/3/mbox/
Test gem_ringfill:
Subgroup basic-default-hang:
incomplete -> PASS (snb-dellxps)
Test gem_sync:
Subgroup basic-bsd:
dmesg-fail -> PASS (ilk-hp8440p)
Test pm_rpm:
Subgroup basic-pci-d3-state:
dmesg-warn -> PASS (byt-nuc)
bdw-nuci7 total:162 pass:152 dwarn:0 dfail:0 fail:0 skip:10
bdw-ultra total:165 pass:152 dwarn:0 dfail:0 fail:0 skip:13
bsw-nuc-2 total:165 pass:135 dwarn:1 dfail:0 fail:0 skip:29
byt-nuc total:165 pass:141 dwarn:0 dfail:0 fail:0 skip:24
hsw-brixbox total:165 pass:151 dwarn:0 dfail:0 fail:0 skip:14
hsw-gt2 total:165 pass:154 dwarn:0 dfail:0 fail:1 skip:10
ilk-hp8440p total:165 pass:115 dwarn:1 dfail:0 fail:1 skip:48
ivb-t430s total:165 pass:150 dwarn:0 dfail:0 fail:1 skip:14
skl-i5k-2 total:165 pass:150 dwarn:0 dfail:0 fail:0 skip:15
snb-dellxps total:165 pass:142 dwarn:0 dfail:0 fail:1 skip:22
Results at /archive/results/CI_IGT_test/Patchwork_1406/
63cbdd1816fd78d404ed004b0f931c497625e0df drm-intel-nightly: 2016y-02m-16d-09h-41m-02s UTC integration manifest
a59fc8eb38dbb913b50d9be561e6d6a306e9853a drm/i915/bxt: Additional MIPI clock divider form B0 stepping onwards
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH] drm/i915/bxt: Additional MIPI clock divider form B0 stepping onwards
2016-02-15 17:13 ` Deepak M
@ 2016-02-17 20:30 ` Jani Nikula
2016-02-19 9:18 ` Jani Nikula
2016-02-26 16:49 ` Ramalingam C
0 siblings, 2 replies; 14+ messages in thread
From: Jani Nikula @ 2016-02-17 20:30 UTC (permalink / raw)
To: intel-gfx; +Cc: Deepak M
On Mon, 15 Feb 2016, Deepak M <m.deepak@intel.com> wrote:
> The MIPI clock calculations for the addtional clock
> are revised from B0 stepping onwards, the bit definitions
> have changed compared to old stepping.
>
> v2: Fixing compilation warning.
> v3: Retained the old Macros (Jani)
>
> Signed-off-by: Deepak M <m.deepak@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 96 +++++++++++++++++++-----------------
> drivers/gpu/drm/i915/intel_dsi_pll.c | 56 ++++++++++++++-------
> 2 files changed, 89 insertions(+), 63 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 144586e..4e61b06 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7663,58 +7663,62 @@ enum skl_disp_power_wells {
> #define BXT_MIPI_DIV_SHIFT(port) \
> _MIPI_PORT(port, BXT_MIPI1_DIV_SHIFT, \
> BXT_MIPI2_DIV_SHIFT)
> -/* Var clock divider to generate TX source. Result must be < 39.5 M */
> -#define BXT_MIPI1_ESCLK_VAR_DIV_MASK (0x3F << 26)
> -#define BXT_MIPI2_ESCLK_VAR_DIV_MASK (0x3F << 10)
> -#define BXT_MIPI_ESCLK_VAR_DIV_MASK(port) \
> - _MIPI_PORT(port, BXT_MIPI1_ESCLK_VAR_DIV_MASK, \
> - BXT_MIPI2_ESCLK_VAR_DIV_MASK)
> -
> -#define BXT_MIPI_ESCLK_VAR_DIV(port, val) \
> - (val << BXT_MIPI_DIV_SHIFT(port))
> +
> /* TX control divider to select actual TX clock output from (8x/var) */
> -#define BXT_MIPI1_TX_ESCLK_SHIFT 21
> -#define BXT_MIPI2_TX_ESCLK_SHIFT 5
> +#define BXT_MIPI1_TX_ESCLK_SHIFT 26
> +#define BXT_MIPI2_TX_ESCLK_SHIFT 10
> #define BXT_MIPI_TX_ESCLK_SHIFT(port) \
> _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_SHIFT, \
> BXT_MIPI2_TX_ESCLK_SHIFT)
> -#define BXT_MIPI1_TX_ESCLK_FIXDIV_MASK (3 << 21)
> -#define BXT_MIPI2_TX_ESCLK_FIXDIV_MASK (3 << 5)
> +#define BXT_MIPI1_TX_ESCLK_FIXDIV_MASK (0x3F << 26)
> +#define BXT_MIPI2_TX_ESCLK_FIXDIV_MASK (0x3F << 10)
> #define BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port) \
> _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_FIXDIV_MASK, \
> - BXT_MIPI2_TX_ESCLK_FIXDIV_MASK)
> -#define BXT_MIPI_TX_ESCLK_8XDIV_BY2(port) \
> - (0x0 << BXT_MIPI_TX_ESCLK_SHIFT(port))
> -#define BXT_MIPI_TX_ESCLK_8XDIV_BY4(port) \
> - (0x1 << BXT_MIPI_TX_ESCLK_SHIFT(port))
> -#define BXT_MIPI_TX_ESCLK_8XDIV_BY8(port) \
> - (0x2 << BXT_MIPI_TX_ESCLK_SHIFT(port))
> -/* RX control divider to select actual RX clock output from 8x*/
> -#define BXT_MIPI1_RX_ESCLK_SHIFT 19
> -#define BXT_MIPI2_RX_ESCLK_SHIFT 3
> -#define BXT_MIPI_RX_ESCLK_SHIFT(port) \
> - _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_SHIFT, \
> - BXT_MIPI2_RX_ESCLK_SHIFT)
> -#define BXT_MIPI1_RX_ESCLK_FIXDIV_MASK (3 << 19)
> -#define BXT_MIPI2_RX_ESCLK_FIXDIV_MASK (3 << 3)
> -#define BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port) \
> - (3 << BXT_MIPI_RX_ESCLK_SHIFT(port))
> -#define BXT_MIPI_RX_ESCLK_8X_BY2(port) \
> - (1 << BXT_MIPI_RX_ESCLK_SHIFT(port))
> -#define BXT_MIPI_RX_ESCLK_8X_BY3(port) \
> - (2 << BXT_MIPI_RX_ESCLK_SHIFT(port))
> -#define BXT_MIPI_RX_ESCLK_8X_BY4(port) \
> - (3 << BXT_MIPI_RX_ESCLK_SHIFT(port))
> -/* BXT-A WA: Always prog DPHY dividers to 00 */
> -#define BXT_MIPI1_DPHY_DIV_SHIFT 16
> -#define BXT_MIPI2_DPHY_DIV_SHIFT 0
> -#define BXT_MIPI_DPHY_DIV_SHIFT(port) \
> - _MIPI_PORT(port, BXT_MIPI1_DPHY_DIV_SHIFT, \
> - BXT_MIPI2_DPHY_DIV_SHIFT)
> -#define BXT_MIPI_1_DPHY_DIVIDER_MASK (3 << 16)
> -#define BXT_MIPI_2_DPHY_DIVIDER_MASK (3 << 0)
> -#define BXT_MIPI_DPHY_DIVIDER_MASK(port) \
> - (3 << BXT_MIPI_DPHY_DIV_SHIFT(port))
> + BXT_MIPI2_TX_ESCLK_FIXDIV_MASK)
> +#define BXT_MIPI_TX_ESCLK_DIVIDER(port, val) \
> + ((val & 0x3F) << BXT_MIPI_TX_ESCLK_SHIFT(port))
> +/* RX upper control divider to select actual RX clock output from 8x*/
> +#define BXT_MIPI1_RX_ESCLK_UPPER_SHIFT 21
> +#define BXT_MIPI2_RX_ESCLK_UPPER_SHIFT 5
> +#define BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port) \
> + _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_SHIFT, \
> + BXT_MIPI2_RX_ESCLK_UPPER_SHIFT)
> +#define BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK (3 << 21)
> +#define BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK (3 << 5)
> +#define BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port) \
> + _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK,\
> + BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK)
> +#define BXT_MIPI_RX_ESCLK_UPPER_DIVIDER(port, val) \
> + ((val & 3) << BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port))
> +/* 8/3X divider to select the actual 8/3X clock output from 8x*/
> +#define BXT_MIPI1_8X_BY3_SHIFT 19
> +#define BXT_MIPI2_8X_BY3_SHIFT 3
> +#define BXT_MIPI_8X_BY3_SHIFT(port) \
> + _MIPI_PORT(port, BXT_MIPI1_8X_BY3_SHIFT, \
> + BXT_MIPI2_8X_BY3_SHIFT)
> +#define BXT_MIPI1_8X_BY3_DIVIDER_MASK (3 << 19)
> +#define BXT_MIPI2_8X_BY3_DIVIDER_MASK (3 << 3)
> +#define BXT_MIPI_8X_BY3_DIVIDER_MASK(port) \
> + _MIPI_PORT(port, BXT_MIPI1_8X_BY3_DIVIDER_MASK, \
> + BXT_MIPI2_8X_BY3_DIVIDER_MASK)
> +#define BXT_MIPI_8X_BY3_DIVIDER(port, val) \
> + ((val & 3) << BXT_MIPI_8X_BY3_SHIFT(port))
> +/* RX lower control divider to select actual RX clock output from 8x*/
> +#define BXT_MIPI1_RX_ESCLK_LOWER_SHIFT 16
> +#define BXT_MIPI2_RX_ESCLK_LOWER_SHIFT 0
> +#define BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port) \
> + _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_SHIFT, \
> + BXT_MIPI2_RX_ESCLK_LOWER_SHIFT)
> +#define BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK (3 << 16)
> +#define BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK (3 << 0)
> +#define BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port) \
> + _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK, \
> + BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK)
> +#define BXT_MIPI_RX_ESCLK_LOWER_DIVIDER(port, val) \
> + ((val & 3) << BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port))
> +
> +#define RX_DIVIDER_BIT_1_2 0x3
> +#define RX_DIVIDER_BIT_3_4 0xC
>
> /* BXT MIPI mode configure */
> #define _BXT_MIPIA_TRANS_HACTIVE 0x6B0F8
> diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
> index bb5e95a..02aeae5 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
> @@ -362,35 +362,57 @@ static void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
> /* Program BXT Mipi clocks and dividers */
> static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port)
> {
> - u32 tmp;
> - u32 divider;
> - u32 dsi_rate;
> - u32 pll_ratio;
> struct drm_i915_private *dev_priv = dev->dev_private;
> + u32 tmp;
> + u32 dsi_rate = 0;
> + u32 pll_ratio = 0;
> + u32 rx_div;
> + u32 tx_div;
> + u32 rx_div_upper;
> + u32 rx_div_lower;
> + u32 mipi_8by3_divider;
>
> /* Clear old configurations */
> tmp = I915_READ(BXT_MIPI_CLOCK_CTL);
> tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
> - tmp &= ~(BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port));
> - tmp &= ~(BXT_MIPI_ESCLK_VAR_DIV_MASK(port));
> - tmp &= ~(BXT_MIPI_DPHY_DIVIDER_MASK(port));
> + tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port));
> + tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port));
> + tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port));
>
> /* Get the current DSI rate(actual) */
> pll_ratio = I915_READ(BXT_DSI_PLL_CTL) &
> BXT_DSI_PLL_RATIO_MASK;
> dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2;
>
> - /* Max possible output of clock is 39.5 MHz, program value -1 */
> - divider = (dsi_rate / BXT_MAX_VAR_OUTPUT_KHZ) - 1;
> - tmp |= BXT_MIPI_ESCLK_VAR_DIV(port, divider);
> + /*
> + * tx clock should be <= 20MHz and the div value must be
> + * subtracted by 1 as per bspec
> + */
> + tx_div = DIV_ROUND_UP(dsi_rate, 20000) - 1;
> + /*
> + * rx clock should be <= 150MHz and the div value must be
> + * subtracted by 1 as per bspec
> + */
> + rx_div = DIV_ROUND_UP(dsi_rate, 150000) - 1;
>
> /*
> - * Tx escape clock must be as close to 20MHz possible, but should
> - * not exceed it. Hence select divide by 2
> + * rx divider value needs to be updated in the
> + * two differnt bit fields in the register hence splitting the
> + * rx divider value accordingly
> */
> - tmp |= BXT_MIPI_TX_ESCLK_8XDIV_BY2(port);
> + rx_div_lower = rx_div & RX_DIVIDER_BIT_1_2;
> + rx_div_upper = (rx_div & RX_DIVIDER_BIT_3_4) >> 2;
> +
> + /* As per bpsec program the 8/3X clock divider to the below value */
> + if (dev_priv->vbt.dsi.config->is_cmd_mode)
> + mipi_8by3_divider = 0x2;
> + else
> + mipi_8by3_divider = 0x3;
>
> - tmp |= BXT_MIPI_RX_ESCLK_8X_BY3(port);
> + tmp |= BXT_MIPI_8X_BY3_DIVIDER(port, mipi_8by3_divider);
> + tmp |= BXT_MIPI_TX_ESCLK_DIVIDER(port, tx_div);
> + tmp |= BXT_MIPI_RX_ESCLK_LOWER_DIVIDER(port, rx_div_lower);
> + tmp |= BXT_MIPI_RX_ESCLK_UPPER_DIVIDER(port, rx_div_upper);
>
> I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
> }
> @@ -513,9 +535,9 @@ static void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
> /* Clear old configurations */
> tmp = I915_READ(BXT_MIPI_CLOCK_CTL);
> tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
> - tmp &= ~(BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port));
> - tmp &= ~(BXT_MIPI_ESCLK_VAR_DIV_MASK(port));
> - tmp &= ~(BXT_MIPI_DPHY_DIVIDER_MASK(port));
> + tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port));
> + tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port));
> + tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port));
> I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
> I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
> }
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH] drm/i915/bxt: Additional MIPI clock divider form B0 stepping onwards
2016-02-17 20:30 ` Jani Nikula
@ 2016-02-19 9:18 ` Jani Nikula
2016-02-26 16:49 ` Ramalingam C
1 sibling, 0 replies; 14+ messages in thread
From: Jani Nikula @ 2016-02-19 9:18 UTC (permalink / raw)
To: intel-gfx; +Cc: Deepak M
On Wed, 17 Feb 2016, Jani Nikula <jani.nikula@linux.intel.com> wrote:
> On Mon, 15 Feb 2016, Deepak M <m.deepak@intel.com> wrote:
>> The MIPI clock calculations for the addtional clock
>> are revised from B0 stepping onwards, the bit definitions
>> have changed compared to old stepping.
>>
>> v2: Fixing compilation warning.
>> v3: Retained the old Macros (Jani)
>>
>> Signed-off-by: Deepak M <m.deepak@intel.com>
>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
The problem here is that we have no Tested-by on B0+ hardware for this.
>
>
>> ---
>> drivers/gpu/drm/i915/i915_reg.h | 96 +++++++++++++++++++-----------------
>> drivers/gpu/drm/i915/intel_dsi_pll.c | 56 ++++++++++++++-------
>> 2 files changed, 89 insertions(+), 63 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 144586e..4e61b06 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -7663,58 +7663,62 @@ enum skl_disp_power_wells {
>> #define BXT_MIPI_DIV_SHIFT(port) \
>> _MIPI_PORT(port, BXT_MIPI1_DIV_SHIFT, \
>> BXT_MIPI2_DIV_SHIFT)
>> -/* Var clock divider to generate TX source. Result must be < 39.5 M */
>> -#define BXT_MIPI1_ESCLK_VAR_DIV_MASK (0x3F << 26)
>> -#define BXT_MIPI2_ESCLK_VAR_DIV_MASK (0x3F << 10)
>> -#define BXT_MIPI_ESCLK_VAR_DIV_MASK(port) \
>> - _MIPI_PORT(port, BXT_MIPI1_ESCLK_VAR_DIV_MASK, \
>> - BXT_MIPI2_ESCLK_VAR_DIV_MASK)
>> -
>> -#define BXT_MIPI_ESCLK_VAR_DIV(port, val) \
>> - (val << BXT_MIPI_DIV_SHIFT(port))
>> +
>> /* TX control divider to select actual TX clock output from (8x/var) */
>> -#define BXT_MIPI1_TX_ESCLK_SHIFT 21
>> -#define BXT_MIPI2_TX_ESCLK_SHIFT 5
>> +#define BXT_MIPI1_TX_ESCLK_SHIFT 26
>> +#define BXT_MIPI2_TX_ESCLK_SHIFT 10
>> #define BXT_MIPI_TX_ESCLK_SHIFT(port) \
>> _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_SHIFT, \
>> BXT_MIPI2_TX_ESCLK_SHIFT)
>> -#define BXT_MIPI1_TX_ESCLK_FIXDIV_MASK (3 << 21)
>> -#define BXT_MIPI2_TX_ESCLK_FIXDIV_MASK (3 << 5)
>> +#define BXT_MIPI1_TX_ESCLK_FIXDIV_MASK (0x3F << 26)
>> +#define BXT_MIPI2_TX_ESCLK_FIXDIV_MASK (0x3F << 10)
>> #define BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port) \
>> _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_FIXDIV_MASK, \
>> - BXT_MIPI2_TX_ESCLK_FIXDIV_MASK)
>> -#define BXT_MIPI_TX_ESCLK_8XDIV_BY2(port) \
>> - (0x0 << BXT_MIPI_TX_ESCLK_SHIFT(port))
>> -#define BXT_MIPI_TX_ESCLK_8XDIV_BY4(port) \
>> - (0x1 << BXT_MIPI_TX_ESCLK_SHIFT(port))
>> -#define BXT_MIPI_TX_ESCLK_8XDIV_BY8(port) \
>> - (0x2 << BXT_MIPI_TX_ESCLK_SHIFT(port))
>> -/* RX control divider to select actual RX clock output from 8x*/
>> -#define BXT_MIPI1_RX_ESCLK_SHIFT 19
>> -#define BXT_MIPI2_RX_ESCLK_SHIFT 3
>> -#define BXT_MIPI_RX_ESCLK_SHIFT(port) \
>> - _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_SHIFT, \
>> - BXT_MIPI2_RX_ESCLK_SHIFT)
>> -#define BXT_MIPI1_RX_ESCLK_FIXDIV_MASK (3 << 19)
>> -#define BXT_MIPI2_RX_ESCLK_FIXDIV_MASK (3 << 3)
>> -#define BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port) \
>> - (3 << BXT_MIPI_RX_ESCLK_SHIFT(port))
>> -#define BXT_MIPI_RX_ESCLK_8X_BY2(port) \
>> - (1 << BXT_MIPI_RX_ESCLK_SHIFT(port))
>> -#define BXT_MIPI_RX_ESCLK_8X_BY3(port) \
>> - (2 << BXT_MIPI_RX_ESCLK_SHIFT(port))
>> -#define BXT_MIPI_RX_ESCLK_8X_BY4(port) \
>> - (3 << BXT_MIPI_RX_ESCLK_SHIFT(port))
>> -/* BXT-A WA: Always prog DPHY dividers to 00 */
>> -#define BXT_MIPI1_DPHY_DIV_SHIFT 16
>> -#define BXT_MIPI2_DPHY_DIV_SHIFT 0
>> -#define BXT_MIPI_DPHY_DIV_SHIFT(port) \
>> - _MIPI_PORT(port, BXT_MIPI1_DPHY_DIV_SHIFT, \
>> - BXT_MIPI2_DPHY_DIV_SHIFT)
>> -#define BXT_MIPI_1_DPHY_DIVIDER_MASK (3 << 16)
>> -#define BXT_MIPI_2_DPHY_DIVIDER_MASK (3 << 0)
>> -#define BXT_MIPI_DPHY_DIVIDER_MASK(port) \
>> - (3 << BXT_MIPI_DPHY_DIV_SHIFT(port))
>> + BXT_MIPI2_TX_ESCLK_FIXDIV_MASK)
>> +#define BXT_MIPI_TX_ESCLK_DIVIDER(port, val) \
>> + ((val & 0x3F) << BXT_MIPI_TX_ESCLK_SHIFT(port))
>> +/* RX upper control divider to select actual RX clock output from 8x*/
>> +#define BXT_MIPI1_RX_ESCLK_UPPER_SHIFT 21
>> +#define BXT_MIPI2_RX_ESCLK_UPPER_SHIFT 5
>> +#define BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port) \
>> + _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_SHIFT, \
>> + BXT_MIPI2_RX_ESCLK_UPPER_SHIFT)
>> +#define BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK (3 << 21)
>> +#define BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK (3 << 5)
>> +#define BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port) \
>> + _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK,\
>> + BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK)
>> +#define BXT_MIPI_RX_ESCLK_UPPER_DIVIDER(port, val) \
>> + ((val & 3) << BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port))
>> +/* 8/3X divider to select the actual 8/3X clock output from 8x*/
>> +#define BXT_MIPI1_8X_BY3_SHIFT 19
>> +#define BXT_MIPI2_8X_BY3_SHIFT 3
>> +#define BXT_MIPI_8X_BY3_SHIFT(port) \
>> + _MIPI_PORT(port, BXT_MIPI1_8X_BY3_SHIFT, \
>> + BXT_MIPI2_8X_BY3_SHIFT)
>> +#define BXT_MIPI1_8X_BY3_DIVIDER_MASK (3 << 19)
>> +#define BXT_MIPI2_8X_BY3_DIVIDER_MASK (3 << 3)
>> +#define BXT_MIPI_8X_BY3_DIVIDER_MASK(port) \
>> + _MIPI_PORT(port, BXT_MIPI1_8X_BY3_DIVIDER_MASK, \
>> + BXT_MIPI2_8X_BY3_DIVIDER_MASK)
>> +#define BXT_MIPI_8X_BY3_DIVIDER(port, val) \
>> + ((val & 3) << BXT_MIPI_8X_BY3_SHIFT(port))
>> +/* RX lower control divider to select actual RX clock output from 8x*/
>> +#define BXT_MIPI1_RX_ESCLK_LOWER_SHIFT 16
>> +#define BXT_MIPI2_RX_ESCLK_LOWER_SHIFT 0
>> +#define BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port) \
>> + _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_SHIFT, \
>> + BXT_MIPI2_RX_ESCLK_LOWER_SHIFT)
>> +#define BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK (3 << 16)
>> +#define BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK (3 << 0)
>> +#define BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port) \
>> + _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK, \
>> + BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK)
>> +#define BXT_MIPI_RX_ESCLK_LOWER_DIVIDER(port, val) \
>> + ((val & 3) << BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port))
>> +
>> +#define RX_DIVIDER_BIT_1_2 0x3
>> +#define RX_DIVIDER_BIT_3_4 0xC
>>
>> /* BXT MIPI mode configure */
>> #define _BXT_MIPIA_TRANS_HACTIVE 0x6B0F8
>> diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
>> index bb5e95a..02aeae5 100644
>> --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
>> +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
>> @@ -362,35 +362,57 @@ static void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
>> /* Program BXT Mipi clocks and dividers */
>> static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port)
>> {
>> - u32 tmp;
>> - u32 divider;
>> - u32 dsi_rate;
>> - u32 pll_ratio;
>> struct drm_i915_private *dev_priv = dev->dev_private;
>> + u32 tmp;
>> + u32 dsi_rate = 0;
>> + u32 pll_ratio = 0;
>> + u32 rx_div;
>> + u32 tx_div;
>> + u32 rx_div_upper;
>> + u32 rx_div_lower;
>> + u32 mipi_8by3_divider;
>>
>> /* Clear old configurations */
>> tmp = I915_READ(BXT_MIPI_CLOCK_CTL);
>> tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
>> - tmp &= ~(BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port));
>> - tmp &= ~(BXT_MIPI_ESCLK_VAR_DIV_MASK(port));
>> - tmp &= ~(BXT_MIPI_DPHY_DIVIDER_MASK(port));
>> + tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port));
>> + tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port));
>> + tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port));
>>
>> /* Get the current DSI rate(actual) */
>> pll_ratio = I915_READ(BXT_DSI_PLL_CTL) &
>> BXT_DSI_PLL_RATIO_MASK;
>> dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2;
>>
>> - /* Max possible output of clock is 39.5 MHz, program value -1 */
>> - divider = (dsi_rate / BXT_MAX_VAR_OUTPUT_KHZ) - 1;
>> - tmp |= BXT_MIPI_ESCLK_VAR_DIV(port, divider);
>> + /*
>> + * tx clock should be <= 20MHz and the div value must be
>> + * subtracted by 1 as per bspec
>> + */
>> + tx_div = DIV_ROUND_UP(dsi_rate, 20000) - 1;
>> + /*
>> + * rx clock should be <= 150MHz and the div value must be
>> + * subtracted by 1 as per bspec
>> + */
>> + rx_div = DIV_ROUND_UP(dsi_rate, 150000) - 1;
>>
>> /*
>> - * Tx escape clock must be as close to 20MHz possible, but should
>> - * not exceed it. Hence select divide by 2
>> + * rx divider value needs to be updated in the
>> + * two differnt bit fields in the register hence splitting the
>> + * rx divider value accordingly
>> */
>> - tmp |= BXT_MIPI_TX_ESCLK_8XDIV_BY2(port);
>> + rx_div_lower = rx_div & RX_DIVIDER_BIT_1_2;
>> + rx_div_upper = (rx_div & RX_DIVIDER_BIT_3_4) >> 2;
>> +
>> + /* As per bpsec program the 8/3X clock divider to the below value */
>> + if (dev_priv->vbt.dsi.config->is_cmd_mode)
>> + mipi_8by3_divider = 0x2;
>> + else
>> + mipi_8by3_divider = 0x3;
>>
>> - tmp |= BXT_MIPI_RX_ESCLK_8X_BY3(port);
>> + tmp |= BXT_MIPI_8X_BY3_DIVIDER(port, mipi_8by3_divider);
>> + tmp |= BXT_MIPI_TX_ESCLK_DIVIDER(port, tx_div);
>> + tmp |= BXT_MIPI_RX_ESCLK_LOWER_DIVIDER(port, rx_div_lower);
>> + tmp |= BXT_MIPI_RX_ESCLK_UPPER_DIVIDER(port, rx_div_upper);
>>
>> I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
>> }
>> @@ -513,9 +535,9 @@ static void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
>> /* Clear old configurations */
>> tmp = I915_READ(BXT_MIPI_CLOCK_CTL);
>> tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
>> - tmp &= ~(BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port));
>> - tmp &= ~(BXT_MIPI_ESCLK_VAR_DIV_MASK(port));
>> - tmp &= ~(BXT_MIPI_DPHY_DIVIDER_MASK(port));
>> + tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port));
>> + tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port));
>> + tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port));
>> I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
>> I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
>> }
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH] drm/i915/bxt: Additional MIPI clock divider form B0 stepping onwards
2016-02-17 20:30 ` Jani Nikula
2016-02-19 9:18 ` Jani Nikula
@ 2016-02-26 16:49 ` Ramalingam C
2016-03-03 13:06 ` Jani Nikula
1 sibling, 1 reply; 14+ messages in thread
From: Ramalingam C @ 2016-02-26 16:49 UTC (permalink / raw)
To: Jani Nikula, Deepak M, intel-gfx
On Thursday 18 February 2016 02:00 AM, Jani Nikula wrote:
> On Mon, 15 Feb 2016, Deepak M <m.deepak@intel.com> wrote:
>> The MIPI clock calculations for the addtional clock
>> are revised from B0 stepping onwards, the bit definitions
>> have changed compared to old stepping.
>>
>> v2: Fixing compilation warning.
>> v3: Retained the old Macros (Jani)
>>
>> Signed-off-by: Deepak M <m.deepak@intel.com>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Tested-by: Ramalingam C <ramalingam.c@intel.com>
Tested it on BXT-T with Tianma panel.
>
>
>> ---
>> drivers/gpu/drm/i915/i915_reg.h | 96 +++++++++++++++++++-----------------
>> drivers/gpu/drm/i915/intel_dsi_pll.c | 56 ++++++++++++++-------
>> 2 files changed, 89 insertions(+), 63 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 144586e..4e61b06 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -7663,58 +7663,62 @@ enum skl_disp_power_wells {
>> #define BXT_MIPI_DIV_SHIFT(port) \
>> _MIPI_PORT(port, BXT_MIPI1_DIV_SHIFT, \
>> BXT_MIPI2_DIV_SHIFT)
>> -/* Var clock divider to generate TX source. Result must be < 39.5 M */
>> -#define BXT_MIPI1_ESCLK_VAR_DIV_MASK (0x3F << 26)
>> -#define BXT_MIPI2_ESCLK_VAR_DIV_MASK (0x3F << 10)
>> -#define BXT_MIPI_ESCLK_VAR_DIV_MASK(port) \
>> - _MIPI_PORT(port, BXT_MIPI1_ESCLK_VAR_DIV_MASK, \
>> - BXT_MIPI2_ESCLK_VAR_DIV_MASK)
>> -
>> -#define BXT_MIPI_ESCLK_VAR_DIV(port, val) \
>> - (val << BXT_MIPI_DIV_SHIFT(port))
>> +
>> /* TX control divider to select actual TX clock output from (8x/var) */
>> -#define BXT_MIPI1_TX_ESCLK_SHIFT 21
>> -#define BXT_MIPI2_TX_ESCLK_SHIFT 5
>> +#define BXT_MIPI1_TX_ESCLK_SHIFT 26
>> +#define BXT_MIPI2_TX_ESCLK_SHIFT 10
>> #define BXT_MIPI_TX_ESCLK_SHIFT(port) \
>> _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_SHIFT, \
>> BXT_MIPI2_TX_ESCLK_SHIFT)
>> -#define BXT_MIPI1_TX_ESCLK_FIXDIV_MASK (3 << 21)
>> -#define BXT_MIPI2_TX_ESCLK_FIXDIV_MASK (3 << 5)
>> +#define BXT_MIPI1_TX_ESCLK_FIXDIV_MASK (0x3F << 26)
>> +#define BXT_MIPI2_TX_ESCLK_FIXDIV_MASK (0x3F << 10)
>> #define BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port) \
>> _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_FIXDIV_MASK, \
>> - BXT_MIPI2_TX_ESCLK_FIXDIV_MASK)
>> -#define BXT_MIPI_TX_ESCLK_8XDIV_BY2(port) \
>> - (0x0 << BXT_MIPI_TX_ESCLK_SHIFT(port))
>> -#define BXT_MIPI_TX_ESCLK_8XDIV_BY4(port) \
>> - (0x1 << BXT_MIPI_TX_ESCLK_SHIFT(port))
>> -#define BXT_MIPI_TX_ESCLK_8XDIV_BY8(port) \
>> - (0x2 << BXT_MIPI_TX_ESCLK_SHIFT(port))
>> -/* RX control divider to select actual RX clock output from 8x*/
>> -#define BXT_MIPI1_RX_ESCLK_SHIFT 19
>> -#define BXT_MIPI2_RX_ESCLK_SHIFT 3
>> -#define BXT_MIPI_RX_ESCLK_SHIFT(port) \
>> - _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_SHIFT, \
>> - BXT_MIPI2_RX_ESCLK_SHIFT)
>> -#define BXT_MIPI1_RX_ESCLK_FIXDIV_MASK (3 << 19)
>> -#define BXT_MIPI2_RX_ESCLK_FIXDIV_MASK (3 << 3)
>> -#define BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port) \
>> - (3 << BXT_MIPI_RX_ESCLK_SHIFT(port))
>> -#define BXT_MIPI_RX_ESCLK_8X_BY2(port) \
>> - (1 << BXT_MIPI_RX_ESCLK_SHIFT(port))
>> -#define BXT_MIPI_RX_ESCLK_8X_BY3(port) \
>> - (2 << BXT_MIPI_RX_ESCLK_SHIFT(port))
>> -#define BXT_MIPI_RX_ESCLK_8X_BY4(port) \
>> - (3 << BXT_MIPI_RX_ESCLK_SHIFT(port))
>> -/* BXT-A WA: Always prog DPHY dividers to 00 */
>> -#define BXT_MIPI1_DPHY_DIV_SHIFT 16
>> -#define BXT_MIPI2_DPHY_DIV_SHIFT 0
>> -#define BXT_MIPI_DPHY_DIV_SHIFT(port) \
>> - _MIPI_PORT(port, BXT_MIPI1_DPHY_DIV_SHIFT, \
>> - BXT_MIPI2_DPHY_DIV_SHIFT)
>> -#define BXT_MIPI_1_DPHY_DIVIDER_MASK (3 << 16)
>> -#define BXT_MIPI_2_DPHY_DIVIDER_MASK (3 << 0)
>> -#define BXT_MIPI_DPHY_DIVIDER_MASK(port) \
>> - (3 << BXT_MIPI_DPHY_DIV_SHIFT(port))
>> + BXT_MIPI2_TX_ESCLK_FIXDIV_MASK)
>> +#define BXT_MIPI_TX_ESCLK_DIVIDER(port, val) \
>> + ((val & 0x3F) << BXT_MIPI_TX_ESCLK_SHIFT(port))
>> +/* RX upper control divider to select actual RX clock output from 8x*/
>> +#define BXT_MIPI1_RX_ESCLK_UPPER_SHIFT 21
>> +#define BXT_MIPI2_RX_ESCLK_UPPER_SHIFT 5
>> +#define BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port) \
>> + _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_SHIFT, \
>> + BXT_MIPI2_RX_ESCLK_UPPER_SHIFT)
>> +#define BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK (3 << 21)
>> +#define BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK (3 << 5)
>> +#define BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port) \
>> + _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK,\
>> + BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK)
>> +#define BXT_MIPI_RX_ESCLK_UPPER_DIVIDER(port, val) \
>> + ((val & 3) << BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port))
>> +/* 8/3X divider to select the actual 8/3X clock output from 8x*/
>> +#define BXT_MIPI1_8X_BY3_SHIFT 19
>> +#define BXT_MIPI2_8X_BY3_SHIFT 3
>> +#define BXT_MIPI_8X_BY3_SHIFT(port) \
>> + _MIPI_PORT(port, BXT_MIPI1_8X_BY3_SHIFT, \
>> + BXT_MIPI2_8X_BY3_SHIFT)
>> +#define BXT_MIPI1_8X_BY3_DIVIDER_MASK (3 << 19)
>> +#define BXT_MIPI2_8X_BY3_DIVIDER_MASK (3 << 3)
>> +#define BXT_MIPI_8X_BY3_DIVIDER_MASK(port) \
>> + _MIPI_PORT(port, BXT_MIPI1_8X_BY3_DIVIDER_MASK, \
>> + BXT_MIPI2_8X_BY3_DIVIDER_MASK)
>> +#define BXT_MIPI_8X_BY3_DIVIDER(port, val) \
>> + ((val & 3) << BXT_MIPI_8X_BY3_SHIFT(port))
>> +/* RX lower control divider to select actual RX clock output from 8x*/
>> +#define BXT_MIPI1_RX_ESCLK_LOWER_SHIFT 16
>> +#define BXT_MIPI2_RX_ESCLK_LOWER_SHIFT 0
>> +#define BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port) \
>> + _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_SHIFT, \
>> + BXT_MIPI2_RX_ESCLK_LOWER_SHIFT)
>> +#define BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK (3 << 16)
>> +#define BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK (3 << 0)
>> +#define BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port) \
>> + _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK, \
>> + BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK)
>> +#define BXT_MIPI_RX_ESCLK_LOWER_DIVIDER(port, val) \
>> + ((val & 3) << BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port))
>> +
>> +#define RX_DIVIDER_BIT_1_2 0x3
>> +#define RX_DIVIDER_BIT_3_4 0xC
>>
>> /* BXT MIPI mode configure */
>> #define _BXT_MIPIA_TRANS_HACTIVE 0x6B0F8
>> diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
>> index bb5e95a..02aeae5 100644
>> --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
>> +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
>> @@ -362,35 +362,57 @@ static void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
>> /* Program BXT Mipi clocks and dividers */
>> static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port)
>> {
>> - u32 tmp;
>> - u32 divider;
>> - u32 dsi_rate;
>> - u32 pll_ratio;
>> struct drm_i915_private *dev_priv = dev->dev_private;
>> + u32 tmp;
>> + u32 dsi_rate = 0;
>> + u32 pll_ratio = 0;
>> + u32 rx_div;
>> + u32 tx_div;
>> + u32 rx_div_upper;
>> + u32 rx_div_lower;
>> + u32 mipi_8by3_divider;
>>
>> /* Clear old configurations */
>> tmp = I915_READ(BXT_MIPI_CLOCK_CTL);
>> tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
>> - tmp &= ~(BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port));
>> - tmp &= ~(BXT_MIPI_ESCLK_VAR_DIV_MASK(port));
>> - tmp &= ~(BXT_MIPI_DPHY_DIVIDER_MASK(port));
>> + tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port));
>> + tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port));
>> + tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port));
>>
>> /* Get the current DSI rate(actual) */
>> pll_ratio = I915_READ(BXT_DSI_PLL_CTL) &
>> BXT_DSI_PLL_RATIO_MASK;
>> dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2;
>>
>> - /* Max possible output of clock is 39.5 MHz, program value -1 */
>> - divider = (dsi_rate / BXT_MAX_VAR_OUTPUT_KHZ) - 1;
>> - tmp |= BXT_MIPI_ESCLK_VAR_DIV(port, divider);
>> + /*
>> + * tx clock should be <= 20MHz and the div value must be
>> + * subtracted by 1 as per bspec
>> + */
>> + tx_div = DIV_ROUND_UP(dsi_rate, 20000) - 1;
>> + /*
>> + * rx clock should be <= 150MHz and the div value must be
>> + * subtracted by 1 as per bspec
>> + */
>> + rx_div = DIV_ROUND_UP(dsi_rate, 150000) - 1;
>>
>> /*
>> - * Tx escape clock must be as close to 20MHz possible, but should
>> - * not exceed it. Hence select divide by 2
>> + * rx divider value needs to be updated in the
>> + * two differnt bit fields in the register hence splitting the
>> + * rx divider value accordingly
>> */
>> - tmp |= BXT_MIPI_TX_ESCLK_8XDIV_BY2(port);
>> + rx_div_lower = rx_div & RX_DIVIDER_BIT_1_2;
>> + rx_div_upper = (rx_div & RX_DIVIDER_BIT_3_4) >> 2;
>> +
>> + /* As per bpsec program the 8/3X clock divider to the below value */
>> + if (dev_priv->vbt.dsi.config->is_cmd_mode)
>> + mipi_8by3_divider = 0x2;
>> + else
>> + mipi_8by3_divider = 0x3;
>>
>> - tmp |= BXT_MIPI_RX_ESCLK_8X_BY3(port);
>> + tmp |= BXT_MIPI_8X_BY3_DIVIDER(port, mipi_8by3_divider);
>> + tmp |= BXT_MIPI_TX_ESCLK_DIVIDER(port, tx_div);
>> + tmp |= BXT_MIPI_RX_ESCLK_LOWER_DIVIDER(port, rx_div_lower);
>> + tmp |= BXT_MIPI_RX_ESCLK_UPPER_DIVIDER(port, rx_div_upper);
>>
>> I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
>> }
>> @@ -513,9 +535,9 @@ static void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
>> /* Clear old configurations */
>> tmp = I915_READ(BXT_MIPI_CLOCK_CTL);
>> tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
>> - tmp &= ~(BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port));
>> - tmp &= ~(BXT_MIPI_ESCLK_VAR_DIV_MASK(port));
>> - tmp &= ~(BXT_MIPI_DPHY_DIVIDER_MASK(port));
>> + tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port));
>> + tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port));
>> + tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port));
>> I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
>> I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
>> }
--
Thanks,
--Ram
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
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^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH] drm/i915/bxt: Additional MIPI clock divider form B0 stepping onwards
2016-02-26 16:49 ` Ramalingam C
@ 2016-03-03 13:06 ` Jani Nikula
0 siblings, 0 replies; 14+ messages in thread
From: Jani Nikula @ 2016-03-03 13:06 UTC (permalink / raw)
To: Ramalingam C, Deepak M, intel-gfx
On Fri, 26 Feb 2016, Ramalingam C <ramalingam.c@intel.com> wrote:
> On Thursday 18 February 2016 02:00 AM, Jani Nikula wrote:
>> On Mon, 15 Feb 2016, Deepak M <m.deepak@intel.com> wrote:
>>> The MIPI clock calculations for the addtional clock
>>> are revised from B0 stepping onwards, the bit definitions
>>> have changed compared to old stepping.
>>>
>>> v2: Fixing compilation warning.
>>> v3: Retained the old Macros (Jani)
>>>
>>> Signed-off-by: Deepak M <m.deepak@intel.com>
>> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> Tested-by: Ramalingam C <ramalingam.c@intel.com>
>
> Tested it on BXT-T with Tianma panel.
Pushed to drm-intel-next-queued, thanks for the patch and testing.
BR,
Jani.
>>
>>
>>> ---
>>> drivers/gpu/drm/i915/i915_reg.h | 96 +++++++++++++++++++-----------------
>>> drivers/gpu/drm/i915/intel_dsi_pll.c | 56 ++++++++++++++-------
>>> 2 files changed, 89 insertions(+), 63 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>>> index 144586e..4e61b06 100644
>>> --- a/drivers/gpu/drm/i915/i915_reg.h
>>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>>> @@ -7663,58 +7663,62 @@ enum skl_disp_power_wells {
>>> #define BXT_MIPI_DIV_SHIFT(port) \
>>> _MIPI_PORT(port, BXT_MIPI1_DIV_SHIFT, \
>>> BXT_MIPI2_DIV_SHIFT)
>>> -/* Var clock divider to generate TX source. Result must be < 39.5 M */
>>> -#define BXT_MIPI1_ESCLK_VAR_DIV_MASK (0x3F << 26)
>>> -#define BXT_MIPI2_ESCLK_VAR_DIV_MASK (0x3F << 10)
>>> -#define BXT_MIPI_ESCLK_VAR_DIV_MASK(port) \
>>> - _MIPI_PORT(port, BXT_MIPI1_ESCLK_VAR_DIV_MASK, \
>>> - BXT_MIPI2_ESCLK_VAR_DIV_MASK)
>>> -
>>> -#define BXT_MIPI_ESCLK_VAR_DIV(port, val) \
>>> - (val << BXT_MIPI_DIV_SHIFT(port))
>>> +
>>> /* TX control divider to select actual TX clock output from (8x/var) */
>>> -#define BXT_MIPI1_TX_ESCLK_SHIFT 21
>>> -#define BXT_MIPI2_TX_ESCLK_SHIFT 5
>>> +#define BXT_MIPI1_TX_ESCLK_SHIFT 26
>>> +#define BXT_MIPI2_TX_ESCLK_SHIFT 10
>>> #define BXT_MIPI_TX_ESCLK_SHIFT(port) \
>>> _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_SHIFT, \
>>> BXT_MIPI2_TX_ESCLK_SHIFT)
>>> -#define BXT_MIPI1_TX_ESCLK_FIXDIV_MASK (3 << 21)
>>> -#define BXT_MIPI2_TX_ESCLK_FIXDIV_MASK (3 << 5)
>>> +#define BXT_MIPI1_TX_ESCLK_FIXDIV_MASK (0x3F << 26)
>>> +#define BXT_MIPI2_TX_ESCLK_FIXDIV_MASK (0x3F << 10)
>>> #define BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port) \
>>> _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_FIXDIV_MASK, \
>>> - BXT_MIPI2_TX_ESCLK_FIXDIV_MASK)
>>> -#define BXT_MIPI_TX_ESCLK_8XDIV_BY2(port) \
>>> - (0x0 << BXT_MIPI_TX_ESCLK_SHIFT(port))
>>> -#define BXT_MIPI_TX_ESCLK_8XDIV_BY4(port) \
>>> - (0x1 << BXT_MIPI_TX_ESCLK_SHIFT(port))
>>> -#define BXT_MIPI_TX_ESCLK_8XDIV_BY8(port) \
>>> - (0x2 << BXT_MIPI_TX_ESCLK_SHIFT(port))
>>> -/* RX control divider to select actual RX clock output from 8x*/
>>> -#define BXT_MIPI1_RX_ESCLK_SHIFT 19
>>> -#define BXT_MIPI2_RX_ESCLK_SHIFT 3
>>> -#define BXT_MIPI_RX_ESCLK_SHIFT(port) \
>>> - _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_SHIFT, \
>>> - BXT_MIPI2_RX_ESCLK_SHIFT)
>>> -#define BXT_MIPI1_RX_ESCLK_FIXDIV_MASK (3 << 19)
>>> -#define BXT_MIPI2_RX_ESCLK_FIXDIV_MASK (3 << 3)
>>> -#define BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port) \
>>> - (3 << BXT_MIPI_RX_ESCLK_SHIFT(port))
>>> -#define BXT_MIPI_RX_ESCLK_8X_BY2(port) \
>>> - (1 << BXT_MIPI_RX_ESCLK_SHIFT(port))
>>> -#define BXT_MIPI_RX_ESCLK_8X_BY3(port) \
>>> - (2 << BXT_MIPI_RX_ESCLK_SHIFT(port))
>>> -#define BXT_MIPI_RX_ESCLK_8X_BY4(port) \
>>> - (3 << BXT_MIPI_RX_ESCLK_SHIFT(port))
>>> -/* BXT-A WA: Always prog DPHY dividers to 00 */
>>> -#define BXT_MIPI1_DPHY_DIV_SHIFT 16
>>> -#define BXT_MIPI2_DPHY_DIV_SHIFT 0
>>> -#define BXT_MIPI_DPHY_DIV_SHIFT(port) \
>>> - _MIPI_PORT(port, BXT_MIPI1_DPHY_DIV_SHIFT, \
>>> - BXT_MIPI2_DPHY_DIV_SHIFT)
>>> -#define BXT_MIPI_1_DPHY_DIVIDER_MASK (3 << 16)
>>> -#define BXT_MIPI_2_DPHY_DIVIDER_MASK (3 << 0)
>>> -#define BXT_MIPI_DPHY_DIVIDER_MASK(port) \
>>> - (3 << BXT_MIPI_DPHY_DIV_SHIFT(port))
>>> + BXT_MIPI2_TX_ESCLK_FIXDIV_MASK)
>>> +#define BXT_MIPI_TX_ESCLK_DIVIDER(port, val) \
>>> + ((val & 0x3F) << BXT_MIPI_TX_ESCLK_SHIFT(port))
>>> +/* RX upper control divider to select actual RX clock output from 8x*/
>>> +#define BXT_MIPI1_RX_ESCLK_UPPER_SHIFT 21
>>> +#define BXT_MIPI2_RX_ESCLK_UPPER_SHIFT 5
>>> +#define BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port) \
>>> + _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_SHIFT, \
>>> + BXT_MIPI2_RX_ESCLK_UPPER_SHIFT)
>>> +#define BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK (3 << 21)
>>> +#define BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK (3 << 5)
>>> +#define BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port) \
>>> + _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK,\
>>> + BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK)
>>> +#define BXT_MIPI_RX_ESCLK_UPPER_DIVIDER(port, val) \
>>> + ((val & 3) << BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port))
>>> +/* 8/3X divider to select the actual 8/3X clock output from 8x*/
>>> +#define BXT_MIPI1_8X_BY3_SHIFT 19
>>> +#define BXT_MIPI2_8X_BY3_SHIFT 3
>>> +#define BXT_MIPI_8X_BY3_SHIFT(port) \
>>> + _MIPI_PORT(port, BXT_MIPI1_8X_BY3_SHIFT, \
>>> + BXT_MIPI2_8X_BY3_SHIFT)
>>> +#define BXT_MIPI1_8X_BY3_DIVIDER_MASK (3 << 19)
>>> +#define BXT_MIPI2_8X_BY3_DIVIDER_MASK (3 << 3)
>>> +#define BXT_MIPI_8X_BY3_DIVIDER_MASK(port) \
>>> + _MIPI_PORT(port, BXT_MIPI1_8X_BY3_DIVIDER_MASK, \
>>> + BXT_MIPI2_8X_BY3_DIVIDER_MASK)
>>> +#define BXT_MIPI_8X_BY3_DIVIDER(port, val) \
>>> + ((val & 3) << BXT_MIPI_8X_BY3_SHIFT(port))
>>> +/* RX lower control divider to select actual RX clock output from 8x*/
>>> +#define BXT_MIPI1_RX_ESCLK_LOWER_SHIFT 16
>>> +#define BXT_MIPI2_RX_ESCLK_LOWER_SHIFT 0
>>> +#define BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port) \
>>> + _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_SHIFT, \
>>> + BXT_MIPI2_RX_ESCLK_LOWER_SHIFT)
>>> +#define BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK (3 << 16)
>>> +#define BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK (3 << 0)
>>> +#define BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port) \
>>> + _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK, \
>>> + BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK)
>>> +#define BXT_MIPI_RX_ESCLK_LOWER_DIVIDER(port, val) \
>>> + ((val & 3) << BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port))
>>> +
>>> +#define RX_DIVIDER_BIT_1_2 0x3
>>> +#define RX_DIVIDER_BIT_3_4 0xC
>>>
>>> /* BXT MIPI mode configure */
>>> #define _BXT_MIPIA_TRANS_HACTIVE 0x6B0F8
>>> diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
>>> index bb5e95a..02aeae5 100644
>>> --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
>>> +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
>>> @@ -362,35 +362,57 @@ static void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
>>> /* Program BXT Mipi clocks and dividers */
>>> static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port)
>>> {
>>> - u32 tmp;
>>> - u32 divider;
>>> - u32 dsi_rate;
>>> - u32 pll_ratio;
>>> struct drm_i915_private *dev_priv = dev->dev_private;
>>> + u32 tmp;
>>> + u32 dsi_rate = 0;
>>> + u32 pll_ratio = 0;
>>> + u32 rx_div;
>>> + u32 tx_div;
>>> + u32 rx_div_upper;
>>> + u32 rx_div_lower;
>>> + u32 mipi_8by3_divider;
>>>
>>> /* Clear old configurations */
>>> tmp = I915_READ(BXT_MIPI_CLOCK_CTL);
>>> tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
>>> - tmp &= ~(BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port));
>>> - tmp &= ~(BXT_MIPI_ESCLK_VAR_DIV_MASK(port));
>>> - tmp &= ~(BXT_MIPI_DPHY_DIVIDER_MASK(port));
>>> + tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port));
>>> + tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port));
>>> + tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port));
>>>
>>> /* Get the current DSI rate(actual) */
>>> pll_ratio = I915_READ(BXT_DSI_PLL_CTL) &
>>> BXT_DSI_PLL_RATIO_MASK;
>>> dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2;
>>>
>>> - /* Max possible output of clock is 39.5 MHz, program value -1 */
>>> - divider = (dsi_rate / BXT_MAX_VAR_OUTPUT_KHZ) - 1;
>>> - tmp |= BXT_MIPI_ESCLK_VAR_DIV(port, divider);
>>> + /*
>>> + * tx clock should be <= 20MHz and the div value must be
>>> + * subtracted by 1 as per bspec
>>> + */
>>> + tx_div = DIV_ROUND_UP(dsi_rate, 20000) - 1;
>>> + /*
>>> + * rx clock should be <= 150MHz and the div value must be
>>> + * subtracted by 1 as per bspec
>>> + */
>>> + rx_div = DIV_ROUND_UP(dsi_rate, 150000) - 1;
>>>
>>> /*
>>> - * Tx escape clock must be as close to 20MHz possible, but should
>>> - * not exceed it. Hence select divide by 2
>>> + * rx divider value needs to be updated in the
>>> + * two differnt bit fields in the register hence splitting the
>>> + * rx divider value accordingly
>>> */
>>> - tmp |= BXT_MIPI_TX_ESCLK_8XDIV_BY2(port);
>>> + rx_div_lower = rx_div & RX_DIVIDER_BIT_1_2;
>>> + rx_div_upper = (rx_div & RX_DIVIDER_BIT_3_4) >> 2;
>>> +
>>> + /* As per bpsec program the 8/3X clock divider to the below value */
>>> + if (dev_priv->vbt.dsi.config->is_cmd_mode)
>>> + mipi_8by3_divider = 0x2;
>>> + else
>>> + mipi_8by3_divider = 0x3;
>>>
>>> - tmp |= BXT_MIPI_RX_ESCLK_8X_BY3(port);
>>> + tmp |= BXT_MIPI_8X_BY3_DIVIDER(port, mipi_8by3_divider);
>>> + tmp |= BXT_MIPI_TX_ESCLK_DIVIDER(port, tx_div);
>>> + tmp |= BXT_MIPI_RX_ESCLK_LOWER_DIVIDER(port, rx_div_lower);
>>> + tmp |= BXT_MIPI_RX_ESCLK_UPPER_DIVIDER(port, rx_div_upper);
>>>
>>> I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
>>> }
>>> @@ -513,9 +535,9 @@ static void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
>>> /* Clear old configurations */
>>> tmp = I915_READ(BXT_MIPI_CLOCK_CTL);
>>> tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
>>> - tmp &= ~(BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port));
>>> - tmp &= ~(BXT_MIPI_ESCLK_VAR_DIV_MASK(port));
>>> - tmp &= ~(BXT_MIPI_DPHY_DIVIDER_MASK(port));
>>> + tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port));
>>> + tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port));
>>> + tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port));
>>> I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
>>> I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
>>> }
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
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Intel-gfx@lists.freedesktop.org
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^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2016-03-03 13:06 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-02-03 10:43 [APL PO PATCH] drm/i915/bxt: Additional MIPI clock divider form B0 stepping onwards Deepak M
2016-02-03 5:21 ` kbuild test robot
2016-02-03 11:16 ` [PATCH] " Deepak M
2016-02-04 12:59 ` Jani Nikula
2016-02-04 13:05 ` Deepak, M
2016-02-04 13:57 ` Jani Nikula
2016-02-04 15:12 ` Deepak, M
2016-02-15 17:13 ` Deepak M
2016-02-17 20:30 ` Jani Nikula
2016-02-19 9:18 ` Jani Nikula
2016-02-26 16:49 ` Ramalingam C
2016-03-03 13:06 ` Jani Nikula
2016-02-03 9:47 ` ✓ Fi.CI.BAT: success for drm/i915/bxt: Additional MIPI clock divider form B0 stepping onwards (rev2) Patchwork
2016-02-16 10:39 ` ✓ Fi.CI.BAT: success for drm/i915/bxt: Additional MIPI clock divider form B0 stepping onwards (rev3) Patchwork
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