From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755613AbcBCLcX (ORCPT ); Wed, 3 Feb 2016 06:32:23 -0500 Received: from mailapp01.imgtec.com ([195.59.15.196]:45782 "EHLO mailapp01.imgtec.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753336AbcBCLcU (ORCPT ); Wed, 3 Feb 2016 06:32:20 -0500 From: Paul Burton To: , Ralf Baechle CC: Paul Burton , =?UTF-8?q?S=C3=B6ren=20Brinkmann?= , Michal Simek , "Jiang Liu" , Lorenzo Pieralisi , Grygorii Strashko , Russell Joyce , Bjorn Helgaas , , , Thomas Gleixner , "Jingoo Han" , Subject: [PATCH v2 05/15] PCI: xilinx: Unify INTx & MSI interrupt FIFO decode Date: Wed, 3 Feb 2016 11:30:35 +0000 Message-ID: <1454499045-5020-6-git-send-email-paul.burton@imgtec.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1454499045-5020-1-git-send-email-paul.burton@imgtec.com> References: <1454499045-5020-1-git-send-email-paul.burton@imgtec.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.100.200.105] Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org When decoding either an INTx or MSI interrupt, the driver has no way to know which it will pull out of the interrupt FIFO. If both were pending then this would lead to either the interrupt being handled incorrectly (MSI interrupt treated as INTx) or not at all (INTx interrupt dropped by MSI path). Unify the reading of the interrupt FIFO & act according to the type of interrupt actually read. Signed-off-by: Paul Burton Fixes: 8961def56845 ("PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver") --- Changes in v2: - Add Fixes tag. drivers/pci/host/pcie-xilinx.c | 47 +++++++++++++----------------------------- 1 file changed, 14 insertions(+), 33 deletions(-) diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c index 1490bd1..afdfb09 100644 --- a/drivers/pci/host/pcie-xilinx.c +++ b/drivers/pci/host/pcie-xilinx.c @@ -397,7 +397,7 @@ static const struct irq_domain_ops intx_domain_ops = { static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data) { struct xilinx_pcie_port *port = (struct xilinx_pcie_port *)data; - u32 val, mask, status, msi_data; + u32 val, mask, status; /* Read interrupt decode and mask registers */ val = pcie_read(port, XILINX_PCIE_REG_IDR); @@ -437,8 +437,8 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data) xilinx_pcie_clear_err_interrupts(port); } - if (status & XILINX_PCIE_INTR_INTX) { - /* INTx interrupt received */ + if (status & (XILINX_PCIE_INTR_INTX | XILINX_PCIE_INTR_MSI)) { + /* Interrupt received */ val = pcie_read(port, XILINX_PCIE_REG_RPIFR1); /* Check whether interrupt valid */ @@ -447,41 +447,22 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data) return IRQ_HANDLED; } - if (!(val & XILINX_PCIE_RPIFR1_MSI_INTR)) { - /* Clear interrupt FIFO register 1 */ - pcie_write(port, XILINX_PCIE_RPIFR1_ALL_MASK, - XILINX_PCIE_REG_RPIFR1); - - /* Handle INTx Interrupt */ + if (val & XILINX_PCIE_RPIFR1_MSI_INTR) { + irq = pcie_read(port, XILINX_PCIE_REG_RPIFR2) & + XILINX_PCIE_RPIFR2_MSG_DATA; + } else { val = ((val & XILINX_PCIE_RPIFR1_INTR_MASK) >> XILINX_PCIE_RPIFR1_INTR_SHIFT) + 1; - generic_handle_irq(irq_find_mapping(port->irq_domain, - val)); + irq = irq_find_mapping(port->irq_domain, val); } - } - if (status & XILINX_PCIE_INTR_MSI) { - /* MSI Interrupt */ - val = pcie_read(port, XILINX_PCIE_REG_RPIFR1); + /* Clear interrupt FIFO register 1 */ + pcie_write(port, XILINX_PCIE_RPIFR1_ALL_MASK, + XILINX_PCIE_REG_RPIFR1); - if (!(val & XILINX_PCIE_RPIFR1_INTR_VALID)) { - dev_warn(port->dev, "RP Intr FIFO1 read error\n"); - return IRQ_HANDLED; - } - - if (val & XILINX_PCIE_RPIFR1_MSI_INTR) { - msi_data = pcie_read(port, XILINX_PCIE_REG_RPIFR2) & - XILINX_PCIE_RPIFR2_MSG_DATA; - - /* Clear interrupt FIFO register 1 */ - pcie_write(port, XILINX_PCIE_RPIFR1_ALL_MASK, - XILINX_PCIE_REG_RPIFR1); - - if (IS_ENABLED(CONFIG_PCI_MSI)) { - /* Handle MSI Interrupt */ - generic_handle_irq(msi_data); - } - } + if (IS_ENABLED(CONFIG_PCI_MSI) || + !(val & XILINX_PCIE_RPIFR1_MSI_INTR)) + generic_handle_irq(irq); } if (status & XILINX_PCIE_INTR_SLV_UNSUPP) -- 2.7.0 From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailapp01.imgtec.com ([195.59.15.196]:52105 "EHLO mailapp01.imgtec.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S27012172AbcBCLcYb311M (ORCPT ); Wed, 3 Feb 2016 12:32:24 +0100 From: Paul Burton Subject: [PATCH v2 05/15] PCI: xilinx: Unify INTx & MSI interrupt FIFO decode Date: Wed, 3 Feb 2016 11:30:35 +0000 Message-ID: <1454499045-5020-6-git-send-email-paul.burton@imgtec.com> In-Reply-To: <1454499045-5020-1-git-send-email-paul.burton@imgtec.com> References: <1454499045-5020-1-git-send-email-paul.burton@imgtec.com> MIME-Version: 1.0 Content-Type: text/plain Return-Path: Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-subscribe: List-owner: List-post: List-archive: To: linux-mips@linux-mips.org, Ralf Baechle Cc: Paul Burton , =?UTF-8?q?S=C3=B6ren=20Brinkmann?= , Michal Simek , Jiang Liu , Lorenzo Pieralisi , Grygorii Strashko , Russell Joyce , Bjorn Helgaas , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Thomas Gleixner , Jingoo Han , linux-arm-kernel@lists.infradead.org Message-ID: <20160203113035.W7hzyPwCQn5NHwjFggLTxCDNdV8LzOhSJQHAWRC1kH4@z> When decoding either an INTx or MSI interrupt, the driver has no way to know which it will pull out of the interrupt FIFO. If both were pending then this would lead to either the interrupt being handled incorrectly (MSI interrupt treated as INTx) or not at all (INTx interrupt dropped by MSI path). Unify the reading of the interrupt FIFO & act according to the type of interrupt actually read. Signed-off-by: Paul Burton Fixes: 8961def56845 ("PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver") --- Changes in v2: - Add Fixes tag. drivers/pci/host/pcie-xilinx.c | 47 +++++++++++++----------------------------- 1 file changed, 14 insertions(+), 33 deletions(-) diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c index 1490bd1..afdfb09 100644 --- a/drivers/pci/host/pcie-xilinx.c +++ b/drivers/pci/host/pcie-xilinx.c @@ -397,7 +397,7 @@ static const struct irq_domain_ops intx_domain_ops = { static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data) { struct xilinx_pcie_port *port = (struct xilinx_pcie_port *)data; - u32 val, mask, status, msi_data; + u32 val, mask, status; /* Read interrupt decode and mask registers */ val = pcie_read(port, XILINX_PCIE_REG_IDR); @@ -437,8 +437,8 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data) xilinx_pcie_clear_err_interrupts(port); } - if (status & XILINX_PCIE_INTR_INTX) { - /* INTx interrupt received */ + if (status & (XILINX_PCIE_INTR_INTX | XILINX_PCIE_INTR_MSI)) { + /* Interrupt received */ val = pcie_read(port, XILINX_PCIE_REG_RPIFR1); /* Check whether interrupt valid */ @@ -447,41 +447,22 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data) return IRQ_HANDLED; } - if (!(val & XILINX_PCIE_RPIFR1_MSI_INTR)) { - /* Clear interrupt FIFO register 1 */ - pcie_write(port, XILINX_PCIE_RPIFR1_ALL_MASK, - XILINX_PCIE_REG_RPIFR1); - - /* Handle INTx Interrupt */ + if (val & XILINX_PCIE_RPIFR1_MSI_INTR) { + irq = pcie_read(port, XILINX_PCIE_REG_RPIFR2) & + XILINX_PCIE_RPIFR2_MSG_DATA; + } else { val = ((val & XILINX_PCIE_RPIFR1_INTR_MASK) >> XILINX_PCIE_RPIFR1_INTR_SHIFT) + 1; - generic_handle_irq(irq_find_mapping(port->irq_domain, - val)); + irq = irq_find_mapping(port->irq_domain, val); } - } - if (status & XILINX_PCIE_INTR_MSI) { - /* MSI Interrupt */ - val = pcie_read(port, XILINX_PCIE_REG_RPIFR1); + /* Clear interrupt FIFO register 1 */ + pcie_write(port, XILINX_PCIE_RPIFR1_ALL_MASK, + XILINX_PCIE_REG_RPIFR1); - if (!(val & XILINX_PCIE_RPIFR1_INTR_VALID)) { - dev_warn(port->dev, "RP Intr FIFO1 read error\n"); - return IRQ_HANDLED; - } - - if (val & XILINX_PCIE_RPIFR1_MSI_INTR) { - msi_data = pcie_read(port, XILINX_PCIE_REG_RPIFR2) & - XILINX_PCIE_RPIFR2_MSG_DATA; - - /* Clear interrupt FIFO register 1 */ - pcie_write(port, XILINX_PCIE_RPIFR1_ALL_MASK, - XILINX_PCIE_REG_RPIFR1); - - if (IS_ENABLED(CONFIG_PCI_MSI)) { - /* Handle MSI Interrupt */ - generic_handle_irq(msi_data); - } - } + if (IS_ENABLED(CONFIG_PCI_MSI) || + !(val & XILINX_PCIE_RPIFR1_MSI_INTR)) + generic_handle_irq(irq); } if (status & XILINX_PCIE_INTR_SLV_UNSUPP) -- 2.7.0 From mboxrd@z Thu Jan 1 00:00:00 1970 From: paul.burton@imgtec.com (Paul Burton) Date: Wed, 3 Feb 2016 11:30:35 +0000 Subject: [PATCH v2 05/15] PCI: xilinx: Unify INTx & MSI interrupt FIFO decode In-Reply-To: <1454499045-5020-1-git-send-email-paul.burton@imgtec.com> References: <1454499045-5020-1-git-send-email-paul.burton@imgtec.com> Message-ID: <1454499045-5020-6-git-send-email-paul.burton@imgtec.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org When decoding either an INTx or MSI interrupt, the driver has no way to know which it will pull out of the interrupt FIFO. If both were pending then this would lead to either the interrupt being handled incorrectly (MSI interrupt treated as INTx) or not at all (INTx interrupt dropped by MSI path). Unify the reading of the interrupt FIFO & act according to the type of interrupt actually read. Signed-off-by: Paul Burton Fixes: 8961def56845 ("PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver") --- Changes in v2: - Add Fixes tag. drivers/pci/host/pcie-xilinx.c | 47 +++++++++++++----------------------------- 1 file changed, 14 insertions(+), 33 deletions(-) diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c index 1490bd1..afdfb09 100644 --- a/drivers/pci/host/pcie-xilinx.c +++ b/drivers/pci/host/pcie-xilinx.c @@ -397,7 +397,7 @@ static const struct irq_domain_ops intx_domain_ops = { static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data) { struct xilinx_pcie_port *port = (struct xilinx_pcie_port *)data; - u32 val, mask, status, msi_data; + u32 val, mask, status; /* Read interrupt decode and mask registers */ val = pcie_read(port, XILINX_PCIE_REG_IDR); @@ -437,8 +437,8 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data) xilinx_pcie_clear_err_interrupts(port); } - if (status & XILINX_PCIE_INTR_INTX) { - /* INTx interrupt received */ + if (status & (XILINX_PCIE_INTR_INTX | XILINX_PCIE_INTR_MSI)) { + /* Interrupt received */ val = pcie_read(port, XILINX_PCIE_REG_RPIFR1); /* Check whether interrupt valid */ @@ -447,41 +447,22 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data) return IRQ_HANDLED; } - if (!(val & XILINX_PCIE_RPIFR1_MSI_INTR)) { - /* Clear interrupt FIFO register 1 */ - pcie_write(port, XILINX_PCIE_RPIFR1_ALL_MASK, - XILINX_PCIE_REG_RPIFR1); - - /* Handle INTx Interrupt */ + if (val & XILINX_PCIE_RPIFR1_MSI_INTR) { + irq = pcie_read(port, XILINX_PCIE_REG_RPIFR2) & + XILINX_PCIE_RPIFR2_MSG_DATA; + } else { val = ((val & XILINX_PCIE_RPIFR1_INTR_MASK) >> XILINX_PCIE_RPIFR1_INTR_SHIFT) + 1; - generic_handle_irq(irq_find_mapping(port->irq_domain, - val)); + irq = irq_find_mapping(port->irq_domain, val); } - } - if (status & XILINX_PCIE_INTR_MSI) { - /* MSI Interrupt */ - val = pcie_read(port, XILINX_PCIE_REG_RPIFR1); + /* Clear interrupt FIFO register 1 */ + pcie_write(port, XILINX_PCIE_RPIFR1_ALL_MASK, + XILINX_PCIE_REG_RPIFR1); - if (!(val & XILINX_PCIE_RPIFR1_INTR_VALID)) { - dev_warn(port->dev, "RP Intr FIFO1 read error\n"); - return IRQ_HANDLED; - } - - if (val & XILINX_PCIE_RPIFR1_MSI_INTR) { - msi_data = pcie_read(port, XILINX_PCIE_REG_RPIFR2) & - XILINX_PCIE_RPIFR2_MSG_DATA; - - /* Clear interrupt FIFO register 1 */ - pcie_write(port, XILINX_PCIE_RPIFR1_ALL_MASK, - XILINX_PCIE_REG_RPIFR1); - - if (IS_ENABLED(CONFIG_PCI_MSI)) { - /* Handle MSI Interrupt */ - generic_handle_irq(msi_data); - } - } + if (IS_ENABLED(CONFIG_PCI_MSI) || + !(val & XILINX_PCIE_RPIFR1_MSI_INTR)) + generic_handle_irq(irq); } if (status & XILINX_PCIE_INTR_SLV_UNSUPP) -- 2.7.0