[U-Boot] (no subject)

[U-Boot] (no subject)

[Peter Robinson]

Hi All,

Here's a couple of patches to help building on gcc-6. We're rebasing Fedora to gcc-6 for Fedora 24 so this was the first build I've attempted with it. It doesn't fix all problems as I also see an issue that the generated/generic-asm-offsets.h isn't generated early enough in the build process but I couldn't quite work out how to move the generation of that earlier in the process. Full logs of that at the link below.

Cheers,
Peter

https://kojipkgs.fedoraproject.org//work/tasks/1747/12801747/build.log

[U-Boot] [PATCH 1/3] Copy gcc5 over to compiler-gcc6.h as a beginning of support

[Peter Robinson]

Add initial support for gcc6 by taking a copy of compiler-gcc5.h

Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
---
 include/linux/compiler-gcc6.h | 65 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 65 insertions(+)
 create mode 100644 include/linux/compiler-gcc6.h

diff --git a/include/linux/compiler-gcc6.h b/include/linux/compiler-gcc6.h
new file mode 100644
index 0000000..622117b
--- /dev/null
+++ b/include/linux/compiler-gcc6.h
@@ -0,0 +1,65 @@
+#ifndef __LINUX_COMPILER_H
+#error "Please don't include <linux/compiler-gcc6.h> directly, include <linux/compiler.h> instead."
+#endif
+
+#define __used				__attribute__((__used__))
+#define __must_check			__attribute__((warn_unused_result))
+#define __compiler_offsetof(a, b)	__builtin_offsetof(a, b)
+
+/* Mark functions as cold. gcc will assume any path leading to a call
+   to them will be unlikely.  This means a lot of manual unlikely()s
+   are unnecessary now for any paths leading to the usual suspects
+   like BUG(), printk(), panic() etc. [but let's keep them for now for
+   older compilers]
+
+   Early snapshots of gcc 4.3 don't support this and we can't detect this
+   in the preprocessor, but we can live with this because they're unreleased.
+   Maketime probing would be overkill here.
+
+   gcc also has a __attribute__((__hot__)) to move hot functions into
+   a special section, but I don't see any sense in this right now in
+   the kernel context */
+#define __cold			__attribute__((__cold__))
+
+#define __UNIQUE_ID(prefix) __PASTE(__PASTE(__UNIQUE_ID_, prefix), __COUNTER__)
+
+#ifndef __CHECKER__
+# define __compiletime_warning(message) __attribute__((warning(message)))
+# define __compiletime_error(message) __attribute__((error(message)))
+#endif /* __CHECKER__ */
+
+/*
+ * Mark a position in code as unreachable.  This can be used to
+ * suppress control flow warnings after asm blocks that transfer
+ * control elsewhere.
+ *
+ * Early snapshots of gcc 4.5 don't support this and we can't detect
+ * this in the preprocessor, but we can live with this because they're
+ * unreleased.  Really, we need to have autoconf for the kernel.
+ */
+#define unreachable() __builtin_unreachable()
+
+/* Mark a function definition as prohibited from being cloned. */
+#define __noclone	__attribute__((__noclone__))
+
+/*
+ * Tell the optimizer that something else uses this function or variable.
+ */
+#define __visible __attribute__((externally_visible))
+
+/*
+ * GCC 'asm goto' miscompiles certain code sequences:
+ *
+ *   http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58670
+ *
+ * Work it around via a compiler barrier quirk suggested by Jakub Jelinek.
+ *
+ * (asm goto is automatically volatile - the naming reflects this.)
+ */
+#define asm_volatile_goto(x...)	do { asm goto(x); asm (""); } while (0)
+
+#ifdef CONFIG_ARCH_USE_BUILTIN_BSWAP
+#define __HAVE_BUILTIN_BSWAP32__
+#define __HAVE_BUILTIN_BSWAP64__
+#define __HAVE_BUILTIN_BSWAP16__
+#endif /* CONFIG_ARCH_USE_BUILTIN_BSWAP */
-- 
2.5.0

[U-Boot] [PATCH 2/3] common: env_flags: include common.h even for HOST_CC

[Peter Robinson]

When compiling with gcc 6 we get the following error due to ARRAY_SIZE being
defined elsewhere.

common/env_flags.c:155: undefined reference to `ARRAY_SIZE'

Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
---
 common/env_flags.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/common/env_flags.c b/common/env_flags.c
index 9c3aed1..696adef 100644
--- a/common/env_flags.c
+++ b/common/env_flags.c
@@ -7,6 +7,7 @@
 
 #include <linux/string.h>
 #include <linux/ctype.h>
+#include <common.h>
 
 #ifdef USE_HOSTCC /* Eliminate "ANSI does not permit..." warnings */
 #include <stdint.h>
@@ -16,7 +17,6 @@
 #include <env_flags.h>
 #define getenv fw_getenv
 #else
-#include <common.h>
 #include <environment.h>
 #endif
 
-- 
2.5.0

[U-Boot] your mail

[Tom Rini]

On Wed, Feb 03, 2016 at 12:42:49PM +0000, Peter Robinson wrote:
> 
> Hi All,
> 
> Here's a couple of patches to help building on gcc-6. We're rebasing Fedora to gcc-6 for Fedora 24 so this was the first build I've attempted with it. It doesn't fix all problems as I also see an issue that the generated/generic-asm-offsets.h isn't generated early enough in the build process but I couldn't quite work out how to move the generation of that earlier in the process. Full logs of that at the link below.
> 
> Cheers,
> Peter
> 
> https://kojipkgs.fedoraproject.org//work/tasks/1747/12801747/build.log

Oh fun, I saw some gcc-6 packages in debian/unstable but not a way to
make them be "$arch-gcc" and not "$arch-gcc-6".  At least with respect
to this error, do you see it in the kernel too?  If not, maybe there's a
semi recent patch we need?

-- 
Tom
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[U-Boot] your mail

[Peter Robinson]

>> Here's a couple of patches to help building on gcc-6. We're rebasing Fedora to gcc-6 for Fedora 24 so this was the first build I've attempted with it. It doesn't fix all problems as I also see an issue that the generated/generic-asm-offsets.h isn't generated early enough in the build process but I couldn't quite work out how to move the generation of that earlier in the process. Full logs of that at the link below.
>>
>> Cheers,
>> Peter
>>
>> https://kojipkgs.fedoraproject.org//work/tasks/1747/12801747/build.log
>
> Oh fun, I saw some gcc-6 packages in debian/unstable but not a way to
> make them be "$arch-gcc" and not "$arch-gcc-6".  At least with respect
> to this error, do you see it in the kernel too?  If not, maybe there's a
> semi recent patch we need?

I'm not sure if there was issues with the kernel, there could have
been since it landed as was fixed before I noticed or maybe the kernel
was tested by the toolchains team, I'll see if I can find out.

Peter

[U-Boot] [PATCH 2/3] common: env_flags: include common.h even for HOST_CC

[Albert ARIBAUD]

Hello Peter,

On Wed,  3 Feb 2016 12:42:51 +0000, Peter Robinson
<pbrobinson@gmail.com> wrote:
> When compiling with gcc 6 we get the following error due to ARRAY_SIZE being
> defined elsewhere.
> 
> common/env_flags.c:155: undefined reference to `ARRAY_SIZE'
> 
> Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
> ---
>  common/env_flags.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/common/env_flags.c b/common/env_flags.c
> index 9c3aed1..696adef 100644
> --- a/common/env_flags.c
> +++ b/common/env_flags.c
> @@ -7,6 +7,7 @@
>  
>  #include <linux/string.h>
>  #include <linux/ctype.h>
> +#include <common.h>
>  
>  #ifdef USE_HOSTCC /* Eliminate "ANSI does not permit..." warnings */
>  #include <stdint.h>
> @@ -16,7 +17,6 @@
>  #include <env_flags.h>
>  #define getenv fw_getenv
>  #else
> -#include <common.h>
>  #include <environment.h>
>  #endif

How come this happens only with gcc-6? Previous compilers surely did not
'guess' the proper value of ARRAY_SIZE, right?

> -- 
> 2.5.0
> 
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot

Amicalement,
-- 
Albert.

[U-Boot] [PATCH 2/3] common: env_flags: include common.h even for HOST_CC

[Peter Robinson]

Hi Albert,

On Wed, Feb 3, 2016 at 1:41 PM, Albert ARIBAUD
<albert.u.boot@aribaud.net> wrote:
> Hello Peter,
>
> On Wed,  3 Feb 2016 12:42:51 +0000, Peter Robinson
> <pbrobinson@gmail.com> wrote:
>> When compiling with gcc 6 we get the following error due to ARRAY_SIZE being
>> defined elsewhere.
>>
>> common/env_flags.c:155: undefined reference to `ARRAY_SIZE'
>>
>> Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
>> ---
>>  common/env_flags.c | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/common/env_flags.c b/common/env_flags.c
>> index 9c3aed1..696adef 100644
>> --- a/common/env_flags.c
>> +++ b/common/env_flags.c
>> @@ -7,6 +7,7 @@
>>
>>  #include <linux/string.h>
>>  #include <linux/ctype.h>
>> +#include <common.h>
>>
>>  #ifdef USE_HOSTCC /* Eliminate "ANSI does not permit..." warnings */
>>  #include <stdint.h>
>> @@ -16,7 +17,6 @@
>>  #include <env_flags.h>
>>  #define getenv fw_getenv
>>  #else
>> -#include <common.h>
>>  #include <environment.h>
>>  #endif
>
> How come this happens only with gcc-6? Previous compilers surely did not
> 'guess' the proper value of ARRAY_SIZE, right?

So testing this RC on on Fedora 23 with gcc 5.3.1 I see the same
failure, I didn't see it with 2016.01 when using 5.3.1 so I'm not sure
what's changed there

Peter

[U-Boot] [PATCH 2/3] common: env_flags: include common.h even for HOST_CC

[Albert ARIBAUD]

Hello Peter,

On Wed, 3 Feb 2016 16:11:38 +0000, Peter Robinson
<pbrobinson@gmail.com> wrote:
> Hi Albert,
> 
> On Wed, Feb 3, 2016 at 1:41 PM, Albert ARIBAUD
> <albert.u.boot@aribaud.net> wrote:
> > Hello Peter,
> >
> > On Wed,  3 Feb 2016 12:42:51 +0000, Peter Robinson
> > <pbrobinson@gmail.com> wrote:
> >> When compiling with gcc 6 we get the following error due to ARRAY_SIZE being
> >> defined elsewhere.
> >>
> >> common/env_flags.c:155: undefined reference to `ARRAY_SIZE'
> >>
> >> Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
> >> ---
> >>  common/env_flags.c | 2 +-
> >>  1 file changed, 1 insertion(+), 1 deletion(-)
> >>
> >> diff --git a/common/env_flags.c b/common/env_flags.c
> >> index 9c3aed1..696adef 100644
> >> --- a/common/env_flags.c
> >> +++ b/common/env_flags.c
> >> @@ -7,6 +7,7 @@
> >>
> >>  #include <linux/string.h>
> >>  #include <linux/ctype.h>
> >> +#include <common.h>
> >>
> >>  #ifdef USE_HOSTCC /* Eliminate "ANSI does not permit..." warnings */
> >>  #include <stdint.h>
> >> @@ -16,7 +17,6 @@
> >>  #include <env_flags.h>
> >>  #define getenv fw_getenv
> >>  #else
> >> -#include <common.h>
> >>  #include <environment.h>
> >>  #endif
> >
> > How come this happens only with gcc-6? Previous compilers surely did not
> > 'guess' the proper value of ARRAY_SIZE, right?
> 
> So testing this RC on on Fedora 23 with gcc 5.3.1 I see the same
> failure, I didn't see it with 2016.01 when using 5.3.1 so I'm not sure
> what's changed there

OK, so maybe unrelated to gcc 6. Could you git bisect?

> Peter

Amicalement,
-- 
Albert.

[U-Boot] [PATCH 2/3] common: env_flags: include common.h even for HOST_CC

[Tom Rini]

On Wed, Feb 03, 2016 at 06:53:11PM +0100, Albert ARIBAUD wrote:
> Hello Peter,
> 
> On Wed, 3 Feb 2016 16:11:38 +0000, Peter Robinson
> <pbrobinson@gmail.com> wrote:
> > Hi Albert,
> > 
> > On Wed, Feb 3, 2016 at 1:41 PM, Albert ARIBAUD
> > <albert.u.boot@aribaud.net> wrote:
> > > Hello Peter,
> > >
> > > On Wed,  3 Feb 2016 12:42:51 +0000, Peter Robinson
> > > <pbrobinson@gmail.com> wrote:
> > >> When compiling with gcc 6 we get the following error due to ARRAY_SIZE being
> > >> defined elsewhere.
> > >>
> > >> common/env_flags.c:155: undefined reference to `ARRAY_SIZE'
> > >>
> > >> Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
> > >> ---
> > >>  common/env_flags.c | 2 +-
> > >>  1 file changed, 1 insertion(+), 1 deletion(-)
> > >>
> > >> diff --git a/common/env_flags.c b/common/env_flags.c
> > >> index 9c3aed1..696adef 100644
> > >> --- a/common/env_flags.c
> > >> +++ b/common/env_flags.c
> > >> @@ -7,6 +7,7 @@
> > >>
> > >>  #include <linux/string.h>
> > >>  #include <linux/ctype.h>
> > >> +#include <common.h>
> > >>
> > >>  #ifdef USE_HOSTCC /* Eliminate "ANSI does not permit..." warnings */
> > >>  #include <stdint.h>
> > >> @@ -16,7 +17,6 @@
> > >>  #include <env_flags.h>
> > >>  #define getenv fw_getenv
> > >>  #else
> > >> -#include <common.h>
> > >>  #include <environment.h>
> > >>  #endif
> > >
> > > How come this happens only with gcc-6? Previous compilers surely did not
> > > 'guess' the proper value of ARRAY_SIZE, right?
> > 
> > So testing this RC on on Fedora 23 with gcc 5.3.1 I see the same
> > failure, I didn't see it with 2016.01 when using 5.3.1 so I'm not sure
> > what's changed there
> 
> OK, so maybe unrelated to gcc 6. Could you git bisect?

Please, gcc 5.3.x is one of my regular tests now.  But I don't do a
tools only build (tossing that on my TODO list..).

-- 
Tom
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[U-Boot] [PATCH 2/3] common: env_flags: include common.h even for HOST_CC

[Tom Rini]

On Wed, Feb 03, 2016 at 12:42:51PM +0000, Peter Robinson wrote:

> When compiling with gcc 6 we get the following error due to ARRAY_SIZE being
> defined elsewhere.
> 
> common/env_flags.c:155: undefined reference to `ARRAY_SIZE'
> 
> Signed-off-by: Peter Robinson <pbrobinson@gmail.com>

I'm going to take http://patchwork.ozlabs.org/patch/582527/ to fix this
instead as I don't want to say that common.h must work in the case of
USE_HOSTCC==true (I'm surprised it did, in fact).  Thanks!

-- 
Tom
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[U-Boot] [PATCH 2/3] common: env_flags: include common.h even for HOST_CC

[Peter Robinson]

>> When compiling with gcc 6 we get the following error due to ARRAY_SIZE being
>> defined elsewhere.
>>
>> common/env_flags.c:155: undefined reference to `ARRAY_SIZE'
>>
>> Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
>
> I'm going to take http://patchwork.ozlabs.org/patch/582527/ to fix this
> instead as I don't want to say that common.h must work in the case of
> USE_HOSTCC==true (I'm surprised it did, in fact).  Thanks!

What ever was pulled into RC2 works for me but I still needed my gcc6 patch.

Peter

[U-Boot] [PATCH 2/3] common: env_flags: include common.h even for HOST_CC

[Tom Rini]

On Tue, Feb 16, 2016 at 11:19:43AM +0000, Peter Robinson wrote:
> >> When compiling with gcc 6 we get the following error due to ARRAY_SIZE being
> >> defined elsewhere.
> >>
> >> common/env_flags.c:155: undefined reference to `ARRAY_SIZE'
> >>
> >> Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
> >
> > I'm going to take http://patchwork.ozlabs.org/patch/582527/ to fix this
> > instead as I don't want to say that common.h must work in the case of
> > USE_HOSTCC==true (I'm surprised it did, in fact).  Thanks!
> 
> What ever was pulled into RC2 works for me but I still needed my gcc6 patch.

Somewhere along the lines, Linux stopped having compiler-gccN.h and just
has compiler-gcc.h and compiler-clang.h.  Would you feel up to making a
pass at migrating those changes or should I?  Thanks!

-- 
Tom
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[U-Boot] (no subject)

[Fabio Estevam]

Hi Thomas,

On Thu, Aug 29, 2019 at 12:12 PM Thomas Schaefer
<Thomas.Schaefer@kontron.com> wrote:

> does this mean that these dts files are directly imported from linux tree without
> modification?

Yes, this is our goal.

> I have cloned https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git . Is
> this the right repository to use for the patch?

Yes, you can generate your patch against this tree.

> I found you and Shawn Guo in the imx maintainers list (among others). Should I send the
> patch directly to you, and also to linux-arm-kernel at lists.infradead.org list?

Please send it via git send-email to all i.MX kernel folks and the
linux-arm-kernel list.

Thanks

[U-Boot] (no subject)

[Thomas Schaefer]

Hi Fabio,

> Hi Thomas,
> 
> On Thu, Aug 29, 2019 at 10:40 AM Thomas Schaefer <thomas.schaefer@kontron.com> wrote:
> 
> >  arch/arm/dts/imx7d.dtsi | 2 +-
> >  arch/arm/dts/imx7s.dtsi | 4 ++--
> >  2 files changed, 3 insertions(+), 3 deletions(-)
> >
> > diff --git a/arch/arm/dts/imx7d.dtsi b/arch/arm/dts/imx7d.dtsi index 
> > 30b058934b..2c33aa876f 100644
> > --- a/arch/arm/dts/imx7d.dtsi
> > +++ b/arch/arm/dts/imx7d.dtsi
> > @@ -101,7 +101,7 @@
> >  &aips3 {
> >         usbotg2: usb at 30b20000 {
> >                 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
> > -               reg = <0x30b20000 0x200>;
> > +               reg = <0x30b20000 0x10000>;
> 
> Yes, I have just checked the reference manual and 0x10000 size is correct.
> 
> Could you please send a patch to fix it in the kernel dts?
> 
> Then, after it gets fixed in the kernel we can simply import it to U-Boot.
> 
> Thanks

does this mean that these dts files are directly imported from linux tree without
modification?

I have cloned https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git . Is
this the right repository to use for the patch?

I found you and Shawn Guo in the imx maintainers list (among others). Should I send the
patch directly to you, and also to linux-arm-kernel at lists.infradead.org list?

Best regards,
Thomas

[U-Boot] (no subject)

[Fabio Estevam]

Hi Thomas,

On Thu, Aug 29, 2019 at 10:40 AM Thomas Schaefer
<thomas.schaefer@kontron.com> wrote:

>  arch/arm/dts/imx7d.dtsi | 2 +-
>  arch/arm/dts/imx7s.dtsi | 4 ++--
>  2 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/dts/imx7d.dtsi b/arch/arm/dts/imx7d.dtsi
> index 30b058934b..2c33aa876f 100644
> --- a/arch/arm/dts/imx7d.dtsi
> +++ b/arch/arm/dts/imx7d.dtsi
> @@ -101,7 +101,7 @@
>  &aips3 {
>         usbotg2: usb at 30b20000 {
>                 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
> -               reg = <0x30b20000 0x200>;
> +               reg = <0x30b20000 0x10000>;

Yes, I have just checked the reference manual and 0x10000 size is correct.

Could you please send a patch to fix it in the kernel dts?

Then, after it gets fixed in the kernel we can simply import it to U-Boot.

Thanks

[U-Boot] (no subject)

[Thomas Schaefer]

Hi all,

I want to introduce a small patch that fixes v 2019.07 bootloader crash during
USB scan on our i.MX7 based custom board (see explanation in the patch comment).

Could you please review and add to next u-boot release?

Best regards,
Thomas

[U-Boot] (no subject)

[Thomas Chou]

On 7/1/19 9:20 PM, Tom Rini wrote:
> On Sun, Jun 30, 2019 at 10:06:35AM +0800, Thomas Chou wrote:
> 
>>
>> Add gcc-8.1.0 support to buildman toolchain.
>>
>> The old gcc-7.3.0 has shared libraries issues on Ubuntu 18.04LTS and
>> 19.04.
> 
> Can you not resolve those shared library issues via one of the toolchain
> PPAs ?
> 

I switched to Fedora 30, which does not have such shared libraries 
issues. Fedora has more cross compiler supported, with gcc-9. I am 
trying them, and will feedback later.

Cheers,
Thomas

[U-Boot] (no subject)

[Thomas Chou]

Hi Tom,

On 7/1/19 9:19 PM, Tom Rini wrote:
> On Sun, Jun 30, 2019 at 06:31:10PM +0800, Bin Meng wrote:
> Unfortunately the kernel.org gcc-8.1 toolchain just isn't usable for us
> due to a number of later-fixed regressions.  We need to use gcc-8.3, I
> think, for something that should work again everywhere.  And when I last
> looked (mid-May, from my WIP branch) while I could get gcc-8.3 for ARM I
> couldn't find one for x86.  The Bootlin toolchains are only 8.2 and
> that's not new enough to have the problem Bin notes as a regression
> fixed.
> 

Agree. We shall wait until they are ready.

Cheers,
Thomas

[U-Boot] (no subject)

[Thomas Chou]

Hi Bin,

On 6/30/19 6:31 PM, Bin Meng wrote:
> On Sun, Jun 30, 2019 at 10:07 AM Thomas Chou <thomas@wytron.com.tw> wrote:
>>         x86:  +   efi-x86_app
>> +{standard input}: Assembler messages:
>> +{standard input}:21695: Error: junk at end of line, first unrecognized character is `@'
>> +{standard input}:21740: Error: junk at end of line, first unrecognized character is `@'
>> +{standard input}:21695: Error: can't resolve `end.7382' {.u_boot_list_2_fit_loadable_3 section} - `start.7379' {.u_boot_list_2_fit_loadable_1 section}
>> +{standard input}:21740: Error: can't resolve `end.7382' {.u_boot_list_2_fit_loadable_3 section} - `start.7379' {.u_boot_list_2_fit_loadable_1 section}
>> +make[2]: *** [scripts/Makefile.build:279: common/image.o] Error 1
>> +make[1]: *** [Makefile:1594: common] Error 2
>> +make: *** [Makefile:148: sub-make] Error 2
> 
> For the x86 failure, it is a known regression issue of GCC 8.
> 
> Regards,
> Bin
> 

Good to know. Thanks.

Thomas

[U-Boot] (no subject)

[Tom Rini]

On Sun, Jun 30, 2019 at 10:06:35AM +0800, Thomas Chou wrote:

> 
> Add gcc-8.1.0 support to buildman toolchain.
> 
> The old gcc-7.3.0 has shared libraries issues on Ubuntu 18.04LTS and
> 19.04.

Can you not resolve those shared library issues via one of the toolchain
PPAs ?

-- 
Tom
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[U-Boot] (no subject)

[Tom Rini]

On Sun, Jun 30, 2019 at 06:31:10PM +0800, Bin Meng wrote:
> On Sun, Jun 30, 2019 at 10:07 AM Thomas Chou <thomas@wytron.com.tw> wrote:
> >
> >
> > Add gcc-8.1.0 support to buildman toolchain.
> >
> > The old gcc-7.3.0 has shared libraries issues on Ubuntu 18.04LTS and
> > 19.04.
> >
> > Though both 7.3.0 and 8.1.0 have arc and nds32 compilers, the following
> > errors were generated on Ubuntu 19.04.
> >
> >        arc:  +   iot_devkit
> > +arc-linux-ld.bfd: error: examples/standalone/hello_world: unable to merge CPU base attributes ARC7xx with ARCEM.
> > +
> > +arc-linux-ld.bfd: failed to merge target specific data of file /home/thomas/.buildman-toolchains/gcc-8.1.0-nolibc/arc-linux/bin/../lib/gcc/arc-linux/8.1.0/libgcc.a(_millicodethunk_st.o)
> > +arc-linux-ld.bfd: failed to merge target specific data of file /home/thomas/.buildman-toolchains/gcc-8.1.0-nolibc/arc-linux/bin/../lib/gcc/arc-linux/8.1.0/libgcc.a(_millicodethunk_ret.o)
> > +make[3]: *** [examples/standalone/Makefile:62: examples/standalone/hello_world] Error 1
> > +make[2]: *** [scripts/Makefile.build:432: examples/standalone] Error 2
> > +make[1]: *** [Makefile:1594: examples] Error 2
> > +make: *** [Makefile:148: sub-make] Error 2
> >
> >
> >      nds32:  +   adp-ae3xx
> > +nds32le-elf-gcc: error: unrecognized command line option '-mno-ext-fpu-dp'
> > +nds32le-elf-gcc: error: unrecognized command line option '-mfloat-abi=soft'
> > +make[2]: *** [scripts/Makefile.autoconf:77: u-boot.cfg] Error 1
> > +make[1]: *** No rule to make target 'include/config/auto.conf', needed by 'include/config/uboot.release'.  Stop.
> > +make: *** [Makefile:148: sub-make] Error 2
> >
> >      nds32:  +   adp-ag101p
> > +nds32le-elf-gcc: error: unrecognized command line option '-mno-ext-fpu-dp'
> > +nds32le-elf-gcc: error: unrecognized command line option '-mfloat-abi=soft'
> > +make[2]: *** [scripts/Makefile.autoconf:77: u-boot.cfg] Error 1
> > +make[1]: *** No rule to make target 'include/config/auto.conf', needed by 'include/config/uboot.release'.  Stop.
> > +make: *** [Makefile:148: sub-make] Error 2
> >
> >        x86:  +   efi-x86_app
> > +{standard input}: Assembler messages:
> > +{standard input}:21695: Error: junk at end of line, first unrecognized character is `@'
> > +{standard input}:21740: Error: junk at end of line, first unrecognized character is `@'
> > +{standard input}:21695: Error: can't resolve `end.7382' {.u_boot_list_2_fit_loadable_3 section} - `start.7379' {.u_boot_list_2_fit_loadable_1 section}
> > +{standard input}:21740: Error: can't resolve `end.7382' {.u_boot_list_2_fit_loadable_3 section} - `start.7379' {.u_boot_list_2_fit_loadable_1 section}
> > +make[2]: *** [scripts/Makefile.build:279: common/image.o] Error 1
> > +make[1]: *** [Makefile:1594: common] Error 2
> > +make: *** [Makefile:148: sub-make] Error 2
> 
> For the x86 failure, it is a known regression issue of GCC 8.

Unfortunately the kernel.org gcc-8.1 toolchain just isn't usable for us
due to a number of later-fixed regressions.  We need to use gcc-8.3, I
think, for something that should work again everywhere.  And when I last
looked (mid-May, from my WIP branch) while I could get gcc-8.3 for ARM I
couldn't find one for x86.  The Bootlin toolchains are only 8.2 and
that's not new enough to have the problem Bin notes as a regression
fixed.

-- 
Tom
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[U-Boot] (no subject)

[Bin Meng]

On Sun, Jun 30, 2019 at 10:07 AM Thomas Chou <thomas@wytron.com.tw> wrote:
>
>
> Add gcc-8.1.0 support to buildman toolchain.
>
> The old gcc-7.3.0 has shared libraries issues on Ubuntu 18.04LTS and
> 19.04.
>
> Though both 7.3.0 and 8.1.0 have arc and nds32 compilers, the following
> errors were generated on Ubuntu 19.04.
>
>        arc:  +   iot_devkit
> +arc-linux-ld.bfd: error: examples/standalone/hello_world: unable to merge CPU base attributes ARC7xx with ARCEM.
> +
> +arc-linux-ld.bfd: failed to merge target specific data of file /home/thomas/.buildman-toolchains/gcc-8.1.0-nolibc/arc-linux/bin/../lib/gcc/arc-linux/8.1.0/libgcc.a(_millicodethunk_st.o)
> +arc-linux-ld.bfd: failed to merge target specific data of file /home/thomas/.buildman-toolchains/gcc-8.1.0-nolibc/arc-linux/bin/../lib/gcc/arc-linux/8.1.0/libgcc.a(_millicodethunk_ret.o)
> +make[3]: *** [examples/standalone/Makefile:62: examples/standalone/hello_world] Error 1
> +make[2]: *** [scripts/Makefile.build:432: examples/standalone] Error 2
> +make[1]: *** [Makefile:1594: examples] Error 2
> +make: *** [Makefile:148: sub-make] Error 2
>
>
>      nds32:  +   adp-ae3xx
> +nds32le-elf-gcc: error: unrecognized command line option '-mno-ext-fpu-dp'
> +nds32le-elf-gcc: error: unrecognized command line option '-mfloat-abi=soft'
> +make[2]: *** [scripts/Makefile.autoconf:77: u-boot.cfg] Error 1
> +make[1]: *** No rule to make target 'include/config/auto.conf', needed by 'include/config/uboot.release'.  Stop.
> +make: *** [Makefile:148: sub-make] Error 2
>
>      nds32:  +   adp-ag101p
> +nds32le-elf-gcc: error: unrecognized command line option '-mno-ext-fpu-dp'
> +nds32le-elf-gcc: error: unrecognized command line option '-mfloat-abi=soft'
> +make[2]: *** [scripts/Makefile.autoconf:77: u-boot.cfg] Error 1
> +make[1]: *** No rule to make target 'include/config/auto.conf', needed by 'include/config/uboot.release'.  Stop.
> +make: *** [Makefile:148: sub-make] Error 2
>
>        x86:  +   efi-x86_app
> +{standard input}: Assembler messages:
> +{standard input}:21695: Error: junk at end of line, first unrecognized character is `@'
> +{standard input}:21740: Error: junk at end of line, first unrecognized character is `@'
> +{standard input}:21695: Error: can't resolve `end.7382' {.u_boot_list_2_fit_loadable_3 section} - `start.7379' {.u_boot_list_2_fit_loadable_1 section}
> +{standard input}:21740: Error: can't resolve `end.7382' {.u_boot_list_2_fit_loadable_3 section} - `start.7379' {.u_boot_list_2_fit_loadable_1 section}
> +make[2]: *** [scripts/Makefile.build:279: common/image.o] Error 1
> +make[1]: *** [Makefile:1594: common] Error 2
> +make: *** [Makefile:148: sub-make] Error 2

For the x86 failure, it is a known regression issue of GCC 8.

Regards,
Bin

[U-Boot] (no subject)

[Thomas Chou]

Add gcc-8.1.0 support to buildman toolchain.

The old gcc-7.3.0 has shared libraries issues on Ubuntu 18.04LTS and
19.04.

Though both 7.3.0 and 8.1.0 have arc and nds32 compilers, the following
errors were generated on Ubuntu 19.04.

       arc:  +   iot_devkit                                       
+arc-linux-ld.bfd: error: examples/standalone/hello_world: unable to merge CPU base attributes ARC7xx with ARCEM.
+
+arc-linux-ld.bfd: failed to merge target specific data of file /home/thomas/.buildman-toolchains/gcc-8.1.0-nolibc/arc-linux/bin/../lib/gcc/arc-linux/8.1.0/libgcc.a(_millicodethunk_st.o)
+arc-linux-ld.bfd: failed to merge target specific data of file /home/thomas/.buildman-toolchains/gcc-8.1.0-nolibc/arc-linux/bin/../lib/gcc/arc-linux/8.1.0/libgcc.a(_millicodethunk_ret.o)
+make[3]: *** [examples/standalone/Makefile:62: examples/standalone/hello_world] Error 1
+make[2]: *** [scripts/Makefile.build:432: examples/standalone] Error 2
+make[1]: *** [Makefile:1594: examples] Error 2
+make: *** [Makefile:148: sub-make] Error 2


     nds32:  +   adp-ae3xx                                     
+nds32le-elf-gcc: error: unrecognized command line option '-mno-ext-fpu-dp'
+nds32le-elf-gcc: error: unrecognized command line option '-mfloat-abi=soft'
+make[2]: *** [scripts/Makefile.autoconf:77: u-boot.cfg] Error 1
+make[1]: *** No rule to make target 'include/config/auto.conf', needed by 'include/config/uboot.release'.  Stop.
+make: *** [Makefile:148: sub-make] Error 2

     nds32:  +   adp-ag101p                       
+nds32le-elf-gcc: error: unrecognized command line option '-mno-ext-fpu-dp'
+nds32le-elf-gcc: error: unrecognized command line option '-mfloat-abi=soft'
+make[2]: *** [scripts/Makefile.autoconf:77: u-boot.cfg] Error 1
+make[1]: *** No rule to make target 'include/config/auto.conf', needed by 'include/config/uboot.release'.  Stop.
+make: *** [Makefile:148: sub-make] Error 2

       x86:  +   efi-x86_app                       
+{standard input}: Assembler messages:
+{standard input}:21695: Error: junk at end of line, first unrecognized character is `@'
+{standard input}:21740: Error: junk at end of line, first unrecognized character is `@'
+{standard input}:21695: Error: can't resolve `end.7382' {.u_boot_list_2_fit_loadable_3 section} - `start.7379' {.u_boot_list_2_fit_loadable_1 section}
+{standard input}:21740: Error: can't resolve `end.7382' {.u_boot_list_2_fit_loadable_3 section} - `start.7379' {.u_boot_list_2_fit_loadable_1 section}
+make[2]: *** [scripts/Makefile.build:279: common/image.o] Error 1
+make[1]: *** [Makefile:1594: common] Error 2
+make: *** [Makefile:148: sub-make] Error 2

[U-Boot] (no subject)

[Adam Ford]

[U-Boot] (no subject)

[Stefano Babic]

Hi Parthiban,

I missed this one, thanks for remind. I will just push to u-boot-imx and
then merge yours.

Regards,
Stefano

On 26/04/19 10:02, Parthiban Nallathambi wrote:
> Ping on this patch.
> 
> Thanks,
> Parthiban N
> 
> On 4/10/19 4:35 PM, Parthiban Nallathambi wrote:
>> Extend PHYTEC phyBOARD-i.MX6UL for phyCORE-i.MX6UL SoM (PCL063)
>> with eMMC on SoM.
>>
>> CPU:   Freescale i.MX6ULL rev1.0 792 MHz (running at 396 MHz)
>> CPU:   Industrial temperature grade (-40C to 105C) at 38C
>> Reset cause: POR
>> Model: Phytec phyBOARD-i.MX6ULL-Segin SBC
>> Board: PHYTEC phyCORE-i.MX6ULL
>> DRAM:  256 MiB
>> MMC:   FSL_SDHC: 0, FSL_SDHC: 1
>> In:    serial at 02020000
>> Out:   serial at 02020000
>> Err:   serial at 02020000
>> Net:   FEC0
>>
>> Working:
>>   - Eth0
>>   - i2C
>>   - MMC/SD
>>   - eMMC
>>   - UART (1 & 5)
>>   - USB (host & otg)
>>
>> Signed-off-by: Parthiban Nallathambi <parthitce@gmail.com>
>> ---
>>
>> Notes:
>>      Changes in v2:
>>      - disabled gpmi and usdhc by default in pcl063-common.dtsi. Board
>>      dts enables it based on the flash storage which is present.
>>      - added CONFIG_SYS_FSL_USDHC_NUM in pcl063.h
>>
>>   arch/arm/dts/Makefile                         |   1 +
>>   arch/arm/dts/imx6ul-phycore-segin.dts         |   7 +-
>>   arch/arm/dts/imx6ull-phycore-segin.dts        |  70 +++++++++++
>>   ...{imx6ul-pcl063.dtsi => pcl063-common.dtsi} |  33 ++++-
>>   arch/arm/mach-imx/mx6/Kconfig                 |  12 ++
>>   board/phytec/pcl063/Kconfig                   |  13 ++
>>   board/phytec/pcl063/MAINTAINERS               |   6 +-
>>   board/phytec/pcl063/pcl063.c                  |   5 +-
>>   board/phytec/pcl063/spl.c                     |  76 +++++++++++-
>>   configs/phycore_pcl063_ull_defconfig          |  54 ++++++++
>>   include/configs/pcl063.h                      |   2 +
>>   include/configs/pcl063_ull.h                  | 117 ++++++++++++++++++
>>   12 files changed, 384 insertions(+), 12 deletions(-)
>>   create mode 100644 arch/arm/dts/imx6ull-phycore-segin.dts
>>   rename arch/arm/dts/{imx6ul-pcl063.dtsi => pcl063-common.dtsi} (83%)
>>   create mode 100644 configs/phycore_pcl063_ull_defconfig
>>   create mode 100644 include/configs/pcl063_ull.h
>>
>> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
>> index 930b7e03db..8459acb344 100644
>> --- a/arch/arm/dts/Makefile
>> +++ b/arch/arm/dts/Makefile
>> @@ -539,6 +539,7 @@ dtb-$(CONFIG_MX6UL) += \
>>   dtb-$(CONFIG_MX6ULL) += \
>>       imx6ull-14x14-evk.dtb \
>>       imx6ull-colibri.dtb \
>> +    imx6ull-phycore-segin.dtb
>>     dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \
>>       imx7d-sdb-qspi.dtb \
>> diff --git a/arch/arm/dts/imx6ul-phycore-segin.dts
>> b/arch/arm/dts/imx6ul-phycore-segin.dts
>> index a46012e2b4..7d68bf8430 100644
>> --- a/arch/arm/dts/imx6ul-phycore-segin.dts
>> +++ b/arch/arm/dts/imx6ul-phycore-segin.dts
>> @@ -16,7 +16,8 @@
>>     /dts-v1/;
>>   -#include "imx6ul-pcl063.dtsi"
>> +#include "imx6ul.dtsi"
>> +#include "pcl063-common.dtsi"
>>     / {
>>       model = "Phytec phyBOARD-i.MX6UL-Segin SBC";
>> @@ -24,6 +25,10 @@
>>                "fsl,imx6ul";
>>   };
>>   +&gpmi {
>> +    status = "okay";
>> +};
>> +
>>   &i2c1 {
>>       i2c_rtc: rtc at 68 {
>>           compatible = "microcrystal,rv4162";
>> diff --git a/arch/arm/dts/imx6ull-phycore-segin.dts
>> b/arch/arm/dts/imx6ull-phycore-segin.dts
>> new file mode 100644
>> index 0000000000..6df3ad2e4a
>> --- /dev/null
>> +++ b/arch/arm/dts/imx6ull-phycore-segin.dts
>> @@ -0,0 +1,70 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * Copyright (C) 2019 Parthiban Nallathambi <parthitce@gmail.com>
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include "imx6ull.dtsi"
>> +#include "pcl063-common.dtsi"
>> +
>> +/ {
>> +    model = "Phytec phyBOARD-i.MX6ULL-Segin SBC";
>> +    compatible = "phytec,phyboard-imx6ull-segin",
>> "phytec,imx6ull-pcl063",
>> +             "fsl,imx6ull";
>> +};
>> +
>> +&i2c1 {
>> +    i2c_rtc: rtc at 68 {
>> +        compatible = "microcrystal,rv4162";
>> +        reg = <0x68>;
>> +        status = "okay";
>> +    };
>> +};
>> +
>> +&uart5 {
>> +    pinctrl-names = "default";
>> +    pinctrl-0 = <&pinctrl_uart5>;
>> +    uart-has-rtscts;
>> +    status = "okay";
>> +};
>> +
>> +&usdhc2 {
>> +    status = "okay";
>> +};
>> +
>> +&usbotg1 {
>> +    pinctrl-names = "default";
>> +    pinctrl-0 = <&pinctrl_usb_otg1_id>;
>> +    dr_mode = "otg";
>> +    srp-disable;
>> +    hnp-disable;
>> +    adp-disable;
>> +    status = "okay";
>> +};
>> +
>> +&usbotg2 {
>> +    dr_mode = "host";
>> +    disable-over-current;
>> +    status = "okay";
>> +};
>> +
>> +&iomuxc {
>> +    pinctrl-names = "default";
>> +
>> +    pinctrl_uart5: uart5grp {
>> +        fsl,pins = <
>> +            MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX    0x1b0b1
>> +            MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX    0x1b0b1
>> +            MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS    0x1b0b1
>> +            MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS    0x1b0b1
>> +        >;
>> +    };
>> +
>> +    pinctrl_usb_otg1_id: usbotg1idgrp {
>> +        fsl,pins = <
>> +            MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID    0x17059
>> +        >;
>> +    };
>> +
>> +};
>> diff --git a/arch/arm/dts/imx6ul-pcl063.dtsi
>> b/arch/arm/dts/pcl063-common.dtsi
>> similarity index 83%
>> rename from arch/arm/dts/imx6ul-pcl063.dtsi
>> rename to arch/arm/dts/pcl063-common.dtsi
>> index 24a6a47983..2b14b2dc5f 100644
>> --- a/arch/arm/dts/imx6ul-pcl063.dtsi
>> +++ b/arch/arm/dts/pcl063-common.dtsi
>> @@ -7,10 +7,6 @@
>>    * Author: Christian Hemp <c.hemp@phytec.de>
>>    */
>>   -/dts-v1/;
>> -
>> -#include "imx6ul.dtsi"
>> -
>>   / {
>>       model = "Phytec phyCORE-i.MX6 Ultra Lite SOM";
>>       compatible = "phytec,imx6ul-pcl063", "fsl,imx6ul";
>> @@ -47,7 +43,7 @@
>>       pinctrl-0 = <&pinctrl_gpmi_nand>;
>>       nand-on-flash-bbt;
>>       fsl,no-blockmark-swap;
>> -    status = "okay";
>> +    status = "disabled";
>>         #address-cells = <1>;
>>       #size-cells = <1>;
>> @@ -99,6 +95,18 @@
>>       status = "okay";
>>   };
>>   +&usdhc2 {
>> +    u-boot,dm-spl;
>> +    u-boot,dm-pre-reloc;
>> +    pinctrl-names = "default";
>> +    pinctrl-0 = <&pinctrl_usdhc2>;
>> +    bus-width = <8>;
>> +    no-1-8-v;
>> +    non-removable;
>> +    keep-power-in-suspend;
>> +    status = "disabled";
>> +};
>> +
>>   &iomuxc {
>>       pinctrl-names = "default";
>>   @@ -170,4 +178,19 @@
>>             >;
>>       };
>> +
>> +    pinctrl_usdhc2: usdhc2grp {
>> +        fsl,pins = <
>> +            MX6UL_PAD_NAND_WE_B__USDHC2_CMD        0x170f9
>> +            MX6UL_PAD_NAND_RE_B__USDHC2_CLK        0x100f9
>> +            MX6UL_PAD_NAND_DATA00__USDHC2_DATA0    0x170f9
>> +            MX6UL_PAD_NAND_DATA01__USDHC2_DATA1    0x170f9
>> +            MX6UL_PAD_NAND_DATA02__USDHC2_DATA2    0x170f9
>> +            MX6UL_PAD_NAND_DATA03__USDHC2_DATA3    0x170f9
>> +            MX6UL_PAD_NAND_DATA04__USDHC2_DATA4    0x170f9
>> +            MX6UL_PAD_NAND_DATA05__USDHC2_DATA5    0x170f9
>> +            MX6UL_PAD_NAND_DATA06__USDHC2_DATA6    0x170f9
>> +            MX6UL_PAD_NAND_DATA07__USDHC2_DATA7    0x170f9
>> +        >;
>> +    };
>>   };
>> diff --git a/arch/arm/mach-imx/mx6/Kconfig
>> b/arch/arm/mach-imx/mx6/Kconfig
>> index e782859b1e..5e2f08e500 100644
>> --- a/arch/arm/mach-imx/mx6/Kconfig
>> +++ b/arch/arm/mach-imx/mx6/Kconfig
>> @@ -443,6 +443,18 @@ config TARGET_PCL063
>>       select DM_THERMAL
>>       select SUPPORT_SPL
>>   +config TARGET_PCL063_ULL
>> +    bool "PHYTEC PCL063 (phyCORE-i.MX6ULL)"
>> +    select MX6ULL
>> +    select DM
>> +    select DM_ETH
>> +    select DM_GPIO
>> +    select DM_I2C
>> +    select DM_MMC
>> +    select DM_SERIAL
>> +    select DM_THERMAL
>> +    select SUPPORT_SPL
>> +
>>   config TARGET_SECOMX6
>>       bool "secomx6 boards"
>>   diff --git a/board/phytec/pcl063/Kconfig b/board/phytec/pcl063/Kconfig
>> index 977db70f64..58f72f2791 100644
>> --- a/board/phytec/pcl063/Kconfig
>> +++ b/board/phytec/pcl063/Kconfig
>> @@ -10,3 +10,16 @@ config SYS_CONFIG_NAME
>>       default "pcl063"
>>     endif
>> +
>> +if TARGET_PCL063_ULL
>> +
>> +config SYS_BOARD
>> +    default "pcl063"
>> +
>> +config SYS_VENDOR
>> +    default "phytec"
>> +
>> +config SYS_CONFIG_NAME
>> +    default "pcl063_ull"
>> +
>> +endif
>> diff --git a/board/phytec/pcl063/MAINTAINERS
>> b/board/phytec/pcl063/MAINTAINERS
>> index c65a951f3d..70e03cfe71 100644
>> --- a/board/phytec/pcl063/MAINTAINERS
>> +++ b/board/phytec/pcl063/MAINTAINERS
>> @@ -1,8 +1,12 @@
>>   PCL063 BOARD
>>   M:    Martyn Welch <martyn.welch@collabora.com>
>> +M:    Parthiban Nallathambi <parthitce@gmail.com>
>>   S:    Maintained
>> -F:    arch/arm/dts/imx6ul-pcl063.dtsi
>>   F:    arch/arm/dts/imx6ul-phycore-segin.dts
>> +F:    arch/arm/dts/imx6ull-phycore-segin.dts
>> +F:    arch/arm/dts/pcl063-common.dtsi
>>   F:    board/phytec/pcl063/
>>   F:    configs/phycore_pcl063_defconfig
>> +F:    configs/phycore_pcl063_ull_defconfig
>>   F:    include/configs/pcl063.h
>> +F:    include/configs/pcl063_ull.h
>> diff --git a/board/phytec/pcl063/pcl063.c b/board/phytec/pcl063/pcl063.c
>> index 38b233d1b0..17012df037 100644
>> --- a/board/phytec/pcl063/pcl063.c
>> +++ b/board/phytec/pcl063/pcl063.c
>> @@ -200,7 +200,10 @@ int board_init(void)
>>     int checkboard(void)
>>   {
>> -    puts("Board: PHYTEC phyCORE-i.MX6UL\n");
>> +    u32 cpurev = get_cpu_rev();
>> +
>> +    printf("Board: PHYTEC phyCORE-i.MX%s\n",
>> +          get_imx_type((cpurev & 0xFF000) >> 12));
>>         return 0;
>>   }
>> diff --git a/board/phytec/pcl063/spl.c b/board/phytec/pcl063/spl.c
>> index b93cd493f2..73a774645d 100644
>> --- a/board/phytec/pcl063/spl.c
>> +++ b/board/phytec/pcl063/spl.c
>> @@ -13,6 +13,7 @@
>>   #include <asm/arch/mx6-ddr.h>
>>   #include <asm/arch/mx6-pins.h>
>>   #include <asm/arch/crm_regs.h>
>> +#include <asm/arch/sys_proto.h>
>>   #include <fsl_esdhc.h>
>>     /* Configuration for Micron MT41K256M16TW-107 IT:P, 32M x 16 x 8
>> -> 256MiB */
>> @@ -117,11 +118,32 @@ static iomux_v3_cfg_t const usdhc1_pads[] = {
>>       MX6_PAD_UART1_RTS_B__USDHC1_CD_B | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>>   };
>>   +#ifndef CONFIG_NAND_MXS
>> +static iomux_v3_cfg_t const usdhc2_pads[] = {
>> +    MX6_PAD_NAND_RE_B__USDHC2_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> +    MX6_PAD_NAND_WE_B__USDHC2_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> +    MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> +    MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> +    MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> +    MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> +    MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> +    MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> +    MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> +    MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> +};
>> +#endif
>> +
>>   static struct fsl_esdhc_cfg usdhc_cfg[] = {
>>       {
>>           .esdhc_base = USDHC1_BASE_ADDR,
>>           .max_bus_width = 4,
>>       },
>> +#ifndef CONFIG_NAND_MXS
>> +    {
>> +        .esdhc_base = USDHC2_BASE_ADDR,
>> +        .max_bus_width = 8,
>> +    },
>> +#endif
>>   };
>>     int board_mmc_getcd(struct mmc *mmc)
>> @@ -131,12 +153,58 @@ int board_mmc_getcd(struct mmc *mmc)
>>     int board_mmc_init(bd_t *bis)
>>   {
>> -    imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
>> ARRAY_SIZE(usdhc1_pads));
>> -    usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
>> -
>> -    return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
>> +    int i, ret;
>> +
>> +    for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
>> +        switch (i) {
>> +        case 0:
>> +            SETUP_IOMUX_PADS(usdhc1_pads);
>> +            usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
>> +            break;
>> +#ifndef CONFIG_NAND_MXS
>> +        case 1:
>> +            SETUP_IOMUX_PADS(usdhc2_pads);
>> +            usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
>> +            break;
>> +#endif
>> +        default:
>> +            printf("Warning - USDHC%d controller not supporting\n",
>> +                   i + 1);
>> +            return 0;
>> +        }
>> +
>> +        ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
>> +        if (ret) {
>> +            printf("Warning: failed to initialize mmc dev %d\n", i);
>> +            return ret;
>> +        }
>> +    }
>> +
>> +    return 0;
>>   }
>>   +void board_boot_order(u32 *spl_boot_list)
>> +{
>> +    u32 bmode = imx6_src_get_boot_mode();
>> +    u8 boot_dev = BOOT_DEVICE_MMC1;
>> +
>> +    switch ((bmode & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT) {
>> +    case IMX6_BMODE_SD:
>> +    case IMX6_BMODE_ESD:
>> +        boot_dev = BOOT_DEVICE_MMC1;
>> +        break;
>> +    case IMX6_BMODE_MMC:
>> +    case IMX6_BMODE_EMMC:
>> +        boot_dev = BOOT_DEVICE_MMC2;
>> +        break;
>> +    default:
>> +        /* Default - BOOT_DEVICE_MMC1 */
>> +        printf("Wrong board boot order\n");
>> +        break;
>> +    }
>> +
>> +    spl_boot_list[0] = boot_dev;
>> +}
>>   #endif /* CONFIG_FSL_ESDHC */
>>     void board_init_f(ulong dummy)
>> diff --git a/configs/phycore_pcl063_ull_defconfig
>> b/configs/phycore_pcl063_ull_defconfig
>> new file mode 100644
>> index 0000000000..75408a8344
>> --- /dev/null
>> +++ b/configs/phycore_pcl063_ull_defconfig
>> @@ -0,0 +1,54 @@
>> +CONFIG_ARM=y
>> +CONFIG_ARCH_MX6=y
>> +CONFIG_SYS_TEXT_BASE=0x87800000
>> +CONFIG_SPL_LIBCOMMON_SUPPORT=y
>> +CONFIG_SPL_LIBGENERIC_SUPPORT=y
>> +CONFIG_TARGET_PCL063_ULL=y
>> +CONFIG_SPL_MMC_SUPPORT=y
>> +CONFIG_SPL_SERIAL_SUPPORT=y
>> +CONFIG_SPL=y
>> +# CONFIG_CMD_DEKBLOB is not set
>> +CONFIG_DISTRO_DEFAULTS=y
>> +CONFIG_NR_DRAM_BANKS=8
>> +CONFIG_FIT=y
>> +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
>> +CONFIG_BOOTDELAY=3
>> +# CONFIG_USE_BOOTCOMMAND is not set
>> +CONFIG_BOARD_EARLY_INIT_F=y
>> +CONFIG_SPL_USB_HOST_SUPPORT=y
>> +CONFIG_SPL_WATCHDOG_SUPPORT=y
>> +CONFIG_CMD_DM=y
>> +CONFIG_CMD_GPIO=y
>> +CONFIG_CMD_GPT=y
>> +# CONFIG_RANDOM_UUID is not set
>> +CONFIG_CMD_I2C=y
>> +CONFIG_CMD_MMC=y
>> +CONFIG_CMD_USB=y
>> +CONFIG_CMD_USB_SDP=y
>> +CONFIG_CMD_CACHE=y
>> +# CONFIG_ISO_PARTITION is not set
>> +CONFIG_OF_CONTROL=y
>> +CONFIG_DEFAULT_DEVICE_TREE="imx6ull-phycore-segin"
>> +CONFIG_DM_I2C_GPIO=y
>> +CONFIG_SYS_I2C_MXC=y
>> +CONFIG_FSL_ESDHC=y
>> +CONFIG_PHYLIB=y
>> +CONFIG_PHY_MICREL=y
>> +CONFIG_FEC_MXC=y
>> +CONFIG_MII=y
>> +CONFIG_PINCTRL=y
>> +CONFIG_PINCTRL_IMX6=y
>> +CONFIG_DM_PMIC=y
>> +# CONFIG_SPL_PMIC_CHILDREN is not set
>> +CONFIG_DM_REGULATOR=y
>> +CONFIG_DM_REGULATOR_FIXED=y
>> +CONFIG_MXC_UART=y
>> +CONFIG_USB=y
>> +CONFIG_DM_USB=y
>> +CONFIG_USB_GADGET=y
>> +CONFIG_USB_GADGET_MANUFACTURER="Phytec"
>> +CONFIG_USB_GADGET_VENDOR_NUM=0x01b67
>> +CONFIG_USB_GADGET_PRODUCT_NUM=0x4fff
>> +CONFIG_CI_UDC=y
>> +CONFIG_USB_GADGET_DOWNLOAD=y
>> +CONFIG_LZO=y
>> diff --git a/include/configs/pcl063.h b/include/configs/pcl063.h
>> index 4ceab519cb..c032f05fc5 100644
>> --- a/include/configs/pcl063.h
>> +++ b/include/configs/pcl063.h
>> @@ -24,6 +24,8 @@
>>   #undef CONFIG_SPL_TEXT_BASE
>>   #define CONFIG_SPL_TEXT_BASE            0x00909000
>>   +#define CONFIG_SYS_FSL_USDHC_NUM    1
>> +
>>   /* Size of malloc() pool */
>>   #define CONFIG_SYS_MALLOC_LEN        (16 * SZ_1M)
>>   diff --git a/include/configs/pcl063_ull.h
>> b/include/configs/pcl063_ull.h
>> new file mode 100644
>> index 0000000000..0f1a010b4e
>> --- /dev/null
>> +++ b/include/configs/pcl063_ull.h
>> @@ -0,0 +1,117 @@
>> +/* SPDX-License-Identifier: GPL-2.0+ */
>> +/*
>> + * Board configuration file for Phytec phyBOARD-i.MX6ULL-Segin SBC
>> + * Copyright (C) 2019 Parthiban Nallathambi <parthitce@gmail.com>
>> + *
>> + * Based on include/configs/xpress.h:
>> + * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
>> + */
>> +#ifndef __PCL063_ULL_H
>> +#define __PCL063_ULL_H
>> +
>> +#include <linux/sizes.h>
>> +#include "mx6_common.h"
>> +
>> +/* SPL options */
>> +#include "imx6_spl.h"
>> +
>> +#define CONFIG_SYS_FSL_USDHC_NUM    2
>> +
>> +/* Size of malloc() pool */
>> +#define CONFIG_SYS_MALLOC_LEN        (16 * SZ_1M)
>> +
>> +/* Environment settings */
>> +#define CONFIG_ENV_SIZE            (0x4000)
>> +#define CONFIG_ENV_OFFSET        (0x80000)
>> +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
>> +#define CONFIG_ENV_OFFSET_REDUND    \
>> +    (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
>> +
>> +/* Environment in SD */
>> +#define CONFIG_SYS_MMC_ENV_DEV        0
>> +#define CONFIG_SYS_MMC_ENV_PART        0
>> +#define MMC_ROOTFS_DEV        0
>> +#define MMC_ROOTFS_PART        2
>> +
>> +/* Console configs */
>> +#define CONFIG_MXC_UART_BASE        UART1_BASE
>> +
>> +/* MMC Configs */
>> +#define CONFIG_FSL_USDHC
>> +
>> +#define CONFIG_SYS_FSL_ESDHC_ADDR    USDHC2_BASE_ADDR
>> +#define CONFIG_SUPPORT_EMMC_BOOT
>> +
>> +/* I2C configs */
>> +#ifdef CONFIG_CMD_I2C
>> +#define CONFIG_SYS_I2C_MXC_I2C1        /* enable I2C bus 1 */
>> +#define CONFIG_SYS_I2C_SPEED        100000
>> +#endif
>> +
>> +/* Miscellaneous configurable options */
>> +#define CONFIG_SYS_MEMTEST_START    0x80000000
>> +#define CONFIG_SYS_MEMTEST_END        (CONFIG_SYS_MEMTEST_START +
>> 0x10000000)
>> +
>> +#define CONFIG_SYS_LOAD_ADDR        CONFIG_LOADADDR
>> +#define CONFIG_SYS_HZ            1000
>> +
>> +/* Physical Memory Map */
>> +#define PHYS_SDRAM            MMDC0_ARB_BASE_ADDR
>> +#define PHYS_SDRAM_SIZE            SZ_256M
>> +
>> +#define CONFIG_SYS_SDRAM_BASE        PHYS_SDRAM
>> +#define CONFIG_SYS_INIT_RAM_ADDR    IRAM_BASE_ADDR
>> +#define CONFIG_SYS_INIT_RAM_SIZE    IRAM_SIZE
>> +
>> +#define CONFIG_SYS_INIT_SP_OFFSET \
>> +    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
>> +#define CONFIG_SYS_INIT_SP_ADDR \
>> +    (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
>> +
>> +/* NAND */
>> +#define CONFIG_SYS_MAX_NAND_DEVICE    1
>> +#define CONFIG_SYS_NAND_BASE        0x40000000
>> +
>> +/* USB Configs */
>> +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
>> +#define CONFIG_MXC_USB_PORTSC        (PORT_PTS_UTMI | PORT_PTS_PTW)
>> +#define CONFIG_MXC_USB_FLAGS        0
>> +#define CONFIG_USB_MAX_CONTROLLER_COUNT    1
>> +
>> +#define CONFIG_IMX_THERMAL
>> +
>> +#define ENV_MMC \
>> +    "mmcdev=" __stringify(MMC_ROOTFS_DEV) "\0" \
>> +    "mmcpart=" __stringify(MMC_ROOTFS_PART) "\0" \
>> +    "fitpart=1\0" \
>> +    "bootdelay=3\0" \
>> +    "silent=1\0" \
>> +    "optargs=rw rootwait\0" \
>> +    "mmcautodetect=yes\0" \
>> +    "mmcrootfstype=ext4\0" \
>> +    "mmcfit_name=fitImage\0" \
>> +    "mmcloadfit=fatload mmc ${mmcdev}:${fitpart} ${fit_addr} " \
>> +            "${mmcfit_name}\0" \
>> +    "mmcargs=setenv bootargs " \
>> +        "root=/dev/mmcblk${mmcdev}p${mmcpart} ${optargs} " \
>> +        "console=${console} rootfstype=${mmcrootfstype}\0" \
>> +    "mmc_mmc_fit=run mmcloadfit;run mmcargs addcon; bootm
>> ${fit_addr}\0" \
>> +
>> +/* Default environment */
>> +#define CONFIG_EXTRA_ENV_SETTINGS \
>> +    "fdt_high=0xffffffff\0" \
>> +    "console=ttymxc0,115200n8\0" \
>> +    "addcon=setenv bootargs ${bootargs}
>> console=${console},${baudrate}\0" \
>> +    "fit_addr=0x82000000\0" \
>> +    ENV_MMC
>> +
>> +#define CONFIG_BOOTCOMMAND        "run mmc_mmc_fit"
>> +
>> +#define BOOT_TARGET_DEVICES(func) \
>> +    func(MMC, mmc, 0) \
>> +    func(MMC, mmc, 1) \
>> +    func(DHCP, dhcp, na)
>> +
>> +#include <config_distro_bootcmd.h>
>> +
>> +#endif /* __PCL063_ULL_H */
>>

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] (no subject)

[Angelo Dureghello]

[PATCH RESEND] drivers: esdhc: add support for ColdFire mcf5441x family

[U-Boot] (no subject)

[sjg at google.com]

From: Simon Glass <sjg@chromium.org>
To: U-Boot Mailing List <u-boot@lists.denx.de>
Cc: Tom Rini <trini@konsulko.com>,
	Marek Vasut <marek.vasut@gmail.com>,
	Simon Glass <sjg@chromium.org>,
	Masahiro Yamada <yamada.masahiro@socionext.com>,
	Rasmus Villemoes <rasmus.villemoes@prevas.dk>,
	Baruch Siach <baruch@tkos.co.il>,
	Jagdish Gediya <jagdish.gediya@nxp.com>,
	Stephen Warren <swarren@nvidia.com>
Subject: [PATCH 1/3] Makefile: Add a warning for boards that don't use  
CONFIG_BLK
Date: Thu, 22 Nov 2018 13:07:54 -0700
Message-Id: <20181122200756.127191-1-sjg@chromium.org>
X-Mailer: git-send-email 2.19.1.1215.g8438c0b245-goog
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit

The deadline for this has passed and we are starting to remove boards that
do not use driver model for block devices.

Add a noisy Makefile warning.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

  Makefile | 7 +++++++
  1 file changed, 7 insertions(+)

diff --git a/Makefile b/Makefile
index 552687db538..8bf422f6a85 100644
--- a/Makefile
+++ b/Makefile
@@ -917,6 +917,13 @@ ifeq ($(CONFIG_DM_I2C_COMPAT)$(CONFIG_SANDBOX),y)
  	@echo "(possibly in a subsequent patch in your series)"
  	@echo "before sending patches to the mailing list."
  	@echo "===================================================="
+endif
+ifneq ($(CONFIG_BLK),y)
+	@echo "===================== WARNING ======================"
+	@echo "This board does not use CONFIG_BLK. Please update"
+	@echo "the board to use CONFIG_BLK before the end of 2018."
+	@echo "See doc/driver-model/MIGRATION.txt for more info."
+	@echo "===================================================="
  endif
  	@# Check that this build does not use CONFIG options that we do not
  	@# know about unless they are in Kconfig. All the existing CONFIG
-- 
2.19.1.1215.g8438c0b245-goog

[U-Boot] (no subject)

[Angelo Dureghello]

This patch adds an initial fdt support to the m68k architecture.

It has been tested on stmark2 board, with a devicetree and
CONFIG_DM_SERIAL=y + CONFIG_DM_SPI=y.

----- test log -----

U-Boot 2018.09-00137-g1be43784f1 (Sep 20 2018 - 22:34:42 +0200)

CPU:   Freescale MCF54415 (Mask:a0 Version:2)
       CPU CLK 240 MHz BUS CLK 120 MHz FLB CLK 60 MHz
       INP CLK 30 MHz VCO CLK 480 MHz
SPI:   ready
DRAM:  128 MiB
Loading Environment from SPI Flash... SF: Detected is25lp128 with page size 256 Bytes, erase size 64 KiB, total 16 MiB
*** Warning - bad CRC, using default environment

In:    uart at fc060000
Out:   uart at fc060000
Err:   uart at fc060000
Hit any key to stop autoboot:  0 
SF: Detected is25lp128 with page size 256 Bytes, erase size 64 KiB, total 16 MiB
device 0 offset 0x100000, size 0x700000
SF: 7340032 bytes @ 0x100000 Read: OK
## Booting kernel from Legacy Image at 40001000 ...
   Image Name:   mainline kernel
   Created:      2018-09-14  19:06:13 UTC
   Image Type:   M68K Linux Kernel Image (uncompressed)
   Data Size:    2184848 Bytes = 2.1 MiB
   Load Address: 40001000
   Entry Point:  40001000
   Verifying Checksum ... OK
   Loading Kernel Image ... OK

[U-Boot] (no subject)

[Jeremy Gebben]

Date: Tue, 18 Sep 2018 15:35:32 -0600
Subject: [PATCH 0/3] net: phy: aquantia: firmware loading

This patch series adds optional support for loading firmware for
Aquantia phys via MDIO commands. Because I'm adding more Kconfig
options for this driver, I've cleaned up the existing defconfigs
that use it.

It has been tested on a NXP ls1046ardb board, and a very similar
custom board that doesn't have dedicated storage for the phy
firmware.

Jeremy Gebben (3):
  configs: migrate CONFIG_PHY_AQUANTIA to Kconfig
  net: phy: aquantia: add firmware loading support
  net: phy: aquantia: autodetect if firmware needs to be loaded

 configs/T1023RDB_NAND_defconfig               |   2 +-
 configs/T1023RDB_SDCARD_defconfig             |   2 +-
 configs/T1023RDB_SECURE_BOOT_defconfig        |   2 +-
 configs/T1023RDB_SPIFLASH_defconfig           |   2 +-
 configs/T1023RDB_defconfig                    |   2 +-
 configs/T1024RDB_NAND_defconfig               |   2 +-
 configs/T1024RDB_SDCARD_defconfig             |   2 +-
 configs/T1024RDB_SECURE_BOOT_defconfig        |   2 +-
 configs/T1024RDB_SPIFLASH_defconfig           |   2 +-
 configs/T1024RDB_defconfig                    |   2 +-
 configs/T2080QDS_NAND_defconfig               |   2 +-
 configs/T2080QDS_SDCARD_defconfig             |   2 +-
 configs/T2080QDS_SECURE_BOOT_defconfig        |   2 +-
 configs/T2080QDS_SPIFLASH_defconfig           |   2 +-
 configs/T2080QDS_SRIO_PCIE_BOOT_defconfig     |   2 +-
 configs/T2080QDS_defconfig                    |   2 +-
 configs/T2080RDB_NAND_defconfig               |   2 +-
 configs/T2080RDB_SDCARD_defconfig             |   2 +-
 configs/T2080RDB_SECURE_BOOT_defconfig        |   2 +-
 configs/T2080RDB_SPIFLASH_defconfig           |   2 +-
 configs/T2080RDB_SRIO_PCIE_BOOT_defconfig     |   2 +-
 configs/T2080RDB_defconfig                    |   2 +-
 configs/T2081QDS_NAND_defconfig               |   2 +-
 configs/T2081QDS_SDCARD_defconfig             |   2 +-
 configs/T2081QDS_SPIFLASH_defconfig           |   2 +-
 configs/T2081QDS_SRIO_PCIE_BOOT_defconfig     |   2 +-
 configs/T2081QDS_defconfig                    |   2 +-
 configs/ls1043ardb_defconfig                  |   2 +-
 configs/ls1043ardb_nand_SECURE_BOOT_defconfig |   2 +-
 configs/ls1043ardb_nand_defconfig             |   2 +-
 configs/ls1043ardb_sdcard_defconfig           |   2 +-
 configs/ls1046ardb_emmc_defconfig             |   2 +-
 configs/ls1046ardb_qspi_SECURE_BOOT_defconfig |   2 +-
 configs/ls1046ardb_qspi_defconfig             |   2 +-
 .../ls1046ardb_sdcard_SECURE_BOOT_defconfig   |   2 +-
 configs/ls1046ardb_sdcard_defconfig           |   2 +-
 configs/ls1088ardb_qspi_SECURE_BOOT_defconfig |   1 +
 configs/ls1088ardb_qspi_defconfig             |   1 +
 ...1088ardb_sdcard_qspi_SECURE_BOOT_defconfig |   1 +
 configs/ls1088ardb_sdcard_qspi_defconfig      |   1 +
 configs/ls2080ardb_defconfig                  |   2 +-
 configs/ls2080ardb_nand_defconfig             |   2 +-
 drivers/net/phy/Kconfig                       |  26 +-
 drivers/net/phy/aquantia.c                    | 254 +++++++++++++++++-
 include/configs/T102xRDB.h                    |   2 -
 include/configs/T208xRDB.h                    |   2 -
 include/configs/ls1043ardb.h                  |   2 -
 include/configs/ls1046ardb.h                  |   2 -
 include/configs/ls1088ardb.h                  |   3 -
 include/configs/ls2080ardb.h                  |   3 -
 50 files changed, 316 insertions(+), 58 deletions(-)

-- 
2.17.1

[U-Boot] (no subject)

[Andy Yan]

:wq






:q








:q
From: Andy Yan <andy.yan@rock-chips.com>
Date: Thu, 9 Mar 2017 19:30:53 +0800
Subject: [PATCH v2 4/7] rockchip: rk3368: Add sysreset driver

Add sysreset driver to reset rk3368 SOC.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---

Changes in v2:
 - slect soft reset source before reset

 drivers/sysreset/Makefile          |  1 +
 drivers/sysreset/sysreset_rk3368.c | 62 ++++++++++++++++++++++++++++++++++++++
 2 files changed, 63 insertions(+)
 create mode 100644 drivers/sysreset/sysreset_rk3368.c

diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile
index 7bb8406..42aaeaf 100644
--- a/drivers/sysreset/Makefile
+++ b/drivers/sysreset/Makefile
@@ -13,6 +13,7 @@ endif
 obj-$(CONFIG_ROCKCHIP_RK3188) += sysreset_rk3188.o
 obj-$(CONFIG_ROCKCHIP_RK3288) += sysreset_rk3288.o
 obj-$(CONFIG_ROCKCHIP_RK3328) += sysreset_rk3328.o
+obj-$(CONFIG_ROCKCHIP_RK3368) += sysreset_rk3368.o
 obj-$(CONFIG_ROCKCHIP_RK3399) += sysreset_rk3399.o
 obj-$(CONFIG_SANDBOX) += sysreset_sandbox.o
 obj-$(CONFIG_ARCH_SNAPDRAGON) += sysreset_snapdragon.o
diff --git a/drivers/sysreset/sysreset_rk3368.c b/drivers/sysreset/sysreset_rk3368.c
new file mode 100644
index 0000000..de62921
--- /dev/null
+++ b/drivers/sysreset/sysreset_rk3368.c
@@ -0,0 +1,62 @@
+/*
+ * (C) Copyright Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <sysreset.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cru_rk3368.h>
+#include <asm/arch/hardware.h>
+#include <linux/err.h>
+
+static void rk3368_pll_enter_slow_mode(struct rk3368_cru *cru)
+{
+	struct rk3368_pll *pll;
+	int i;
+
+	for (i = 0; i < 6; i++) {
+		pll = &cru->pll[i];
+		rk_clrreg(&pll->con3, PLL_MODE_MASK);
+	}
+}
+
+static int rk3368_sysreset_request(struct udevice *dev, enum sysreset_t type)
+{
+	struct rk3368_cru *cru = rockchip_get_cru();
+
+	if (IS_ERR(cru))
+		return PTR_ERR(cru);
+	switch (type) {
+	case SYSRESET_WARM:
+		rk3368_pll_enter_slow_mode(cru);
+		rk_clrsetreg(&cru->glb_rst_con, PMU_GLB_SRST_CTRL_MASK,
+			     PMU_RST_BY_SND_GLB_SRST << PMU_GLB_SRST_CTRL_SHIFT);
+		writel(0xeca8, &cru->glb_srst_snd_val);
+		break;
+	case SYSRESET_COLD:
+		rk3368_pll_enter_slow_mode(cru);
+		rk_clrsetreg(&cru->glb_rst_con, PMU_GLB_SRST_CTRL_MASK,
+			     PMU_RST_BY_FST_GLB_SRST << PMU_GLB_SRST_CTRL_SHIFT);
+		writel(0xfdb9, &cru->glb_srst_fst_val);
+		break;
+	default:
+		return -EPROTONOSUPPORT;
+	}
+
+	return -EINPROGRESS;
+}
+
+static struct sysreset_ops rk3368_sysreset = {
+	.request	= rk3368_sysreset_request,
+};
+
+U_BOOT_DRIVER(sysreset_rk3368) = {
+	.name	= "rk3368_sysreset",
+	.id	= UCLASS_SYSRESET,
+	.ops	= &rk3368_sysreset,
+};
-- 
2.7.4

[U-Boot] (no subject)

[Zhikang Zhang]

Test for NVMe driver:
	platform: LS1046AQDS
	NVMe SSD: Intel P3700 400G

The test logs are as follow:
----------------------------
=> nvme list
Device 0: Vendor: 0x8086 Rev: 8DV10131 Prod: CVFT535600LS400BGN
        Type: Hard Disk
	Capacity: 381554.0 MB = 372.6 GB (781422768 x 512)

=> nvme device 0

Device 0: Vendor: 0x8086 Rev: 8DV10131 Prod: CVFT535600LS400BGN
	Type: Hard Disk
        Capacity: 381554.0 MB = 372.6 GB (781422768 x 512)
... is now current device


=> nvme info
Blk device 0: Optional Admin Command Support:
	Namespace Management/Attachment: no
        Firmware Commit/Image download: yes
	Format NVM: yes
	Security Send/Receive: no
Blk device 0: Optional NVM Command Support:
        Reservation: no
        Save/Select field in the Set/Get features: no
        Write Zeroes: yes
        Dataset Management: yes
	Write Uncorrectable: no
Blk device 0: Format NVM Attributes:
        Support Cryptographic Erase: yes
        Support erase a particular namespace: No
        Support format a particular namespace: No
Blk device 0: LBA Format Support:
        LBA Foramt 0 Support: (current)
	        Metadata Size: 0
	        LBA Data Size: 512
                Relative Performance: Good
        LBA Foramt 1 Support:
                Metadata Size: 8
                LBA Data Size: 512
                Relative Performance: Good
        LBA Foramt 2 Support:
		Metadata Size: 16
                LBA Data Size: 512
		Relative Performance: Good
        LBA Foramt 3 Support:
		Metadata Size: 0
		LBA Data Size: 4096
                Relative Performance: Best
        LBA Foramt 4 Support:
                Metadata Size: 8
                LBA Data Size: 4096
                Relative Performance: Best
        LBA Foramt 5 Support:
                Metadata Size: 64
                LBA Data Size: 4096
                Relative Performance: Best
Blk device 0: End-to-End DataProtect Capabilities:
        As last eight bytes: yes
        As first eight bytes: No
        Support Type3: No
        Support Type2: No
        Support Type1: yes
Blk device 0: Metadata capabilities:
        As part of a separate buffer: No
        As part of an extended data LBA: yes

=> nvme part

Partition Map for UNKNOWN device 0  --   Partition Type: DOS

Part    Start Sector    Num Sectors     UUID            Type
  1     2048            2048000         ffc18949-01     83

=> nvme read 90000000 0 100000

NVME read: device 0 block # 0, count 1048576 ... read: OK
536870912 bytes read in 1086 ms (471.5 MiB/s)

=> nvme write 90000000 0 100000

NVME write: device 0 block # 0, count 1048576 ... write: OK
536870912 bytes read in 1070 ms (478.5 MiB/s)

=> fatls nvme 0
 32376967   kernel.itb
 22929408   100m

 2 file(s), 0 dir(s)

=> fatload nvme 0 90000000 kernel.itb
reading kernel.itb
32376967 bytes read in 128 ms (241.2 MiB/s)

[U-Boot] (no subject)

[Rick Bronson]

Hi All,

  I've got nsupported RK3288 hardware running the latest git u-boot to SPL
as explained in
http://git.denx.de/?p=u-boot.git;a=blob;f=doc/README.rockchip.  My goal
is to run the mainline (ie. not Android) Linux kernel on this hardware
and wondered:

 - Do I need to get the latest git u-boot to run before I can run the
mainline kernel?  Or can I use
github.com/linux-rockchip/u-boot-rockchip.git, which I have running
u-boot fully.

 - The device tree seems to be in two places, once via:

	resource_tool --image=resource2.img --pack linux/logo.bmp ${DTS}.dtb

  that gets put into the resource file and then again at the end of the
kernel via CONFIG_ARM_APPENDED_DTB.  Do I need both?  When I do both
I get things like:

....
Unknow param: MACHINE_MODEL:rk30sdk!
Unknow param: MACHINE_ID:007!
....

  Thanks much.

  Rick

[U-Boot] (no subject)

[Stefano Babic]

HI Akshay,

On 01/01/1970 01:00,  wrote:
> Add support for Advantech DMS-BA16 board. The board is based on Advantech
> BA16 module which has a i.MX6D processor. The board supports:
>  - FEC Ethernet
>  - USB Ports
>  - SDHC and MMC boot
>  - SPI NOR
>  - LVDS and HDMI display
> 
> Basic information about the module:
>  - Module manufacturer: Advantech
>  - CPU: Freescale ARM Cortex-A9 i.MX6D
>  - SPECS:
>      Up to 2GB Onboard DDR3 Memory;
>      Up to 16GB Onboard eMMC NAND Flash
>      Supports OpenGL ES 2.0 and OpenVG 1.1
>      HDMI, 24-bit LVDS
>      1x UART, 2x I2C, 8x GPIO,
>      4x Host USB 2.0 port, 1x USB OTG port,
>      1x micro SD (SDHC),1x SDIO, 1x SATA II,
>      1x 10/100/1000 Mbps Ethernet, 1x PCIe X1 Gen2
> 
> Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
> Cc: u-boot at lists.denx.de
> Cc: sbabic at denx.de
> ---
>  arch/arm/cpu/armv7/mx6/Kconfig       |   5 +
>  board/advantech/dms-ba16/Kconfig     |  27 ++
>  board/advantech/dms-ba16/MAINTAINERS |   8 +
>  board/advantech/dms-ba16/Makefile    |   8 +
>  board/advantech/dms-ba16/ddr_1g.cfg  | 206 +++++++++++++
>  board/advantech/dms-ba16/ddr_2g.cfg  | 151 +++++++++
>  board/advantech/dms-ba16/dms-ba16.c  | 571 +++++++++++++++++++++++++++++++++++
>  configs/dms-ba16-1g_defconfig        |  27 ++
>  configs/dms-ba16_defconfig           |  26 ++
>  include/configs/advantech_dms-ba16.h | 329 ++++++++++++++++++++
>  10 files changed, 1358 insertions(+)
>  create mode 100644 board/advantech/dms-ba16/Kconfig
>  create mode 100644 board/advantech/dms-ba16/MAINTAINERS
>  create mode 100644 board/advantech/dms-ba16/Makefile
>  create mode 100644 board/advantech/dms-ba16/ddr_1g.cfg
>  create mode 100644 board/advantech/dms-ba16/ddr_2g.cfg
>  create mode 100644 board/advantech/dms-ba16/dms-ba16.c
>  create mode 100644 configs/dms-ba16-1g_defconfig
>  create mode 100644 configs/dms-ba16_defconfig
>  create mode 100644 include/configs/advantech_dms-ba16.h
> 
> diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig
> index 663f970..1e4a1cb 100644
> --- a/arch/arm/cpu/armv7/mx6/Kconfig
> +++ b/arch/arm/cpu/armv7/mx6/Kconfig
> @@ -35,6 +35,10 @@ choice
>  	prompt "MX6 board select"
>  	optional
>  
> +config TARGET_ADVANTECH_DMS_BA16
> +	bool "Advantech dms-ba16"
> +	select MX6Q
> +
>  config TARGET_ARISTAINETOS
>  	bool "aristainetos"
>  
> @@ -184,6 +188,7 @@ config SYS_SOC
>  	default "mx6"
>  
>  source "board/ge/bx50v3/Kconfig"
> +source "board/advantech/dms-ba16/Kconfig"
>  source "board/aristainetos/Kconfig"
>  source "board/bachmann/ot1200/Kconfig"
>  source "board/barco/platinum/Kconfig"
> diff --git a/board/advantech/dms-ba16/Kconfig b/board/advantech/dms-ba16/Kconfig
> new file mode 100644
> index 0000000..cbc803f
> --- /dev/null
> +++ b/board/advantech/dms-ba16/Kconfig
> @@ -0,0 +1,27 @@
> +choice
> +        prompt "DDR Size"
> +	default SYS_DDR_2G
> +
> +config SYS_DDR_1G
> +	bool "1GiB"
> +
> +config SYS_DDR_2G
> +	bool "2GiB"
> +
> +endchoice
> +
> +config IMX_CONFIG
> +	default "board/advantech/dms-ba16/ddr_2g.cfg" if SYS_DDR_2G
> +	default "board/advantech/dms-ba16/ddr_1g.cfg" if SYS_DDR_1G
> +
> +config SYS_BOARD
> +	default "dms-ba16"
> +
> +config SYS_VENDOR
> +	default "advantech"
> +
> +config SYS_SOC
> +	default "mx6"
> +
> +config SYS_CONFIG_NAME
> +	default "advantech_dms-ba16"
> diff --git a/board/advantech/dms-ba16/MAINTAINERS b/board/advantech/dms-ba16/MAINTAINERS
> new file mode 100644
> index 0000000..e8ea3dd
> --- /dev/null
> +++ b/board/advantech/dms-ba16/MAINTAINERS
> @@ -0,0 +1,8 @@
> +ADVANTECH_DMS-BA16 BOARD
> +M:	Akshay Bhat <akshaybhat@timesys.com>
> +M:	Ken Lin <Ken.Lin@advantech.com.tw>
> +S:	Maintained
> +F:	board/advantech/dms-ba16/
> +F:	include/configs/advantech_dms-ba16.h
> +F:	configs/dms-ba16_defconfig
> +F:	configs/dms-ba16-1g_defconfig
> diff --git a/board/advantech/dms-ba16/Makefile b/board/advantech/dms-ba16/Makefile
> new file mode 100644
> index 0000000..ec9aaa8
> --- /dev/null
> +++ b/board/advantech/dms-ba16/Makefile
> @@ -0,0 +1,8 @@
> +#
> +# Copyright 2016 Timesys Corporation
> +# Copyright 2016 Advantech Corporation
> +#
> +# SPDX-License-Identifier:	GPL-2.0+
> +#
> +
> +obj-y  := dms-ba16.o
> diff --git a/board/advantech/dms-ba16/ddr_1g.cfg b/board/advantech/dms-ba16/ddr_1g.cfg
> new file mode 100644
> index 0000000..a470f48
> --- /dev/null
> +++ b/board/advantech/dms-ba16/ddr_1g.cfg
> @@ -0,0 +1,206 @@
> +/*
> + * Copyright (C) 2011 Freescale Semiconductor, Inc.
> + * Jason Liu <r64343@freescale.com>
> + *
> + * SPDX-License-Identifier:    GPL-2.0+
> + *
> + * Refer doc/README.imximage for more details about how-to configure
> + * and create imximage boot image
> + *
> + * The syntax is taken as close as possible with the kwbimage
> + */
> +
> +
> +IMAGE_VERSION 2
> +BOOT_FROM sd
> +
> +//*================================================================================================
> +// Enable all clocks (they are disabled by ROM code)
> +//*================================================================================================
> +DATA 4 0x020c4068  0xffffffff
> +DATA 4 0x020c406c  0xffffffff
> +DATA 4 0x020c4070  0xffffffff
> +DATA 4 0x020c4074  0xffffffff
> +DATA 4 0x020c4078  0xffffffff
> +DATA 4 0x020c407c  0xffffffff
> +DATA 4 0x020c4080  0xffffffff
> +DATA 4 0x020c4084  0xffffffff

Do you really need to enable all clocks ? Most boards try to enable just
the clocks they nee, not all.


There is a problem with this file. This seems coming from a very old
port, and it does not follow semantic as other imximage.cfg files.

You post a ddr2.cfg file and you see the differences: instead of bare
hexadecimal values for register address, the register name is used,
because the preprocessor runs before calling mkimage.

> +
> +//######################################################
> +// IOMUX
> +//######################################################
> +
> +//DDR IO TYPE:
> +DATA 4 0x020e0798  0x000c0000 // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE - DDR_SEL11
> +DATA 4 0x020e0758  0x00000000 // IOMUXC_SW_PAD_CTL_GRP_DDRPKE - PKE0 , Pull disabled for all, except DQS.
> +
> +//CLOCK:
> +DATA 4 0x020e0588  0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 - DSE101, DDR_INPUT0, HYS0
> +DATA 4 0x020e0594  0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1 - DSE101, DDR_INPUT0, HYS0
> +
> +//ADDRESS:
> +DATA 4 0x020e056c  0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS - DSE110, DDR_INPUT1, HYS0
> +DATA 4 0x020e0578  0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS - DSE110, DDR_INPUT1, HYS0
> +DATA 4 0x020e074c  0x00000030 // IOMUXC_SW_PAD_CTL_GRP_ADDDS - DSE110
> +
> +//CONTROL:
> +DATA 4 0x020e057c  0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET - DSE110, DDR_INPUT1, HYS0, DDR_SEL00
> +DATA 4 0x020e058c  0x00000000 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2
> +DATA 4 0x020e059c  0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0
> +DATA 4 0x020e05a0  0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1
> +DATA 4 0x020e078c  0x00000030 // IOMUXC_SW_PAD_CTL_GRP_CTLDS - DSE110
> +
> +//DATA STROBE:
> +DATA 4 0x020e0750  0x00020000 // IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL - DDR_INPUT1
> +DATA 4 0x020e05a8  0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 - DSE110
> +DATA 4 0x020e05b0  0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 - DSE110
> +DATA 4 0x020e0524  0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 - DSE110
> +DATA 4 0x020e051c  0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 - DSE110
> +DATA 4 0x020e0518  0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4 - DSE110
> +DATA 4 0x020e050c  0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5 - DSE110
> +DATA 4 0x020e05b8  0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6 - DSE110
> +DATA 4 0x020e05c0  0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7 - DSE110
> +
> +//DATA:
> +DATA 4 0x020e0774  0x00020000 // IOMUXC_SW_PAD_CTL_GRP_DDRMODE- DDR_INPUT 1,diff
> +DATA 4 0x020e0784  0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B0DS - DSE110
> +DATA 4 0x020e0788  0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B1DS - DSE110
> +DATA 4 0x020e0794  0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B2DS - DSE110
> +DATA 4 0x020e079c  0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B3DS - DSE110
> +DATA 4 0x020e07a0  0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B4DS - DSE110
> +DATA 4 0x020e07a4  0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B5DS - DSE110
> +DATA 4 0x020e07a8  0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B6DS - DSE110
> +DATA 4 0x020e0748  0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B7DS - DSE110
> +DATA 4 0x020e05ac  0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 - DSE110, DDR_INPUT1, HYS0
> +DATA 4 0x020e05b4  0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 - DSE110, DDR_INPUT1, HYS0
> +DATA 4 0x020e0528  0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 - DSE110, DDR_INPUT1, HYS0
> +DATA 4 0x020e0520  0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 - DSE110, DDR_INPUT1, HYS0
> +DATA 4 0x020e0514  0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4 - DSE110, DDR_INPUT1, HYS0
> +DATA 4 0x020e0510  0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5 - DSE110, DDR_INPUT1, HYS0
> +DATA 4 0x020e05bc  0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6 - DSE110, DDR_INPUT1, HYS0
> +DATA 4 0x020e05c4  0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7 - DSE110, DDR_INPUT1, HYS0

If you switch to SPL, all this stuff is managed by common code.

Even if you do not want it, you should factorize this in several files,
maybe reusing some .fg from other boards. Take a look at
boudary/nitrogen6x (nitrogen6q.cfg).

And register address must be substituted by names, as you have already
done for the second file.

> +
> +//######################################################
> +//Calibrations:
> +//######################################################
> +// ZQ:
> +DATA 4 0x021b0800  0xa1390003      // DDR_PHY_P0_MPZQHWCTRL, enable both one-time & periodic HW ZQ calibration.
> +
> +// write leveling
> +DATA 4 0x021b080c  0x001F001F
> +DATA 4 0x021b0810  0x001F001F
> +DATA 4 0x021b480c  0x001F001F
> +DATA 4 0x021b4810  0x001F001F
> +
> +//DQS gating, read delay, write delay calibration values based on calibration compare of 0x00ffff00:
> +// It is highly recommended for the user to run calibration code on her/his specific board
> +//and replace following delay values accordingly:
> +
> +//Read DQS Gating calibration
> +DATA 4 0x021b083c  0x43480350
> +DATA 4 0x021b0840  0x033C0340
> +DATA 4 0x021b483c  0x43480350
> +DATA 4 0x021b4840  0x03340314
> +
> +//Read calibration
> +DATA 4 0x021b0848  0x382E2C32
> +DATA 4 0x021b4848  0x38363044
> +
> +//Write calibration
> +DATA 4 0x021b0850  0x3A38403A
> +DATA 4 0x021b4850  0x4432483E
> +
> +//read data bit delay: (3 is the reccommended default value, although out of reset value is 0):
> +DATA 4 0x021b081c  0x33333333      // DDR_PHY_P0_MPREDQBY0DL3
> +DATA 4 0x021b0820  0x33333333      // DDR_PHY_P0_MPREDQBY1DL3
> +DATA 4 0x021b0824  0x33333333      // DDR_PHY_P0_MPREDQBY2DL3
> +DATA 4 0x021b0828  0x33333333      // DDR_PHY_P0_MPREDQBY3DL3
> +DATA 4 0x021b481c  0x33333333      // DDR_PHY_P1_MPREDQBY0DL3
> +DATA 4 0x021b4820  0x33333333      // DDR_PHY_P1_MPREDQBY1DL3
> +DATA 4 0x021b4824  0x33333333      // DDR_PHY_P1_MPREDQBY2DL3
> +DATA 4 0x021b4828  0x33333333      // DDR_PHY_P1_MPREDQBY3DL3
> +
> +//######################################################
> +// Complete calibration by forced measurment:
> +//######################################################
> +DATA 4 0x021b08b8  0x00000800      // DDR_PHY_P0_MPMUR0, frc_msr
> +DATA 4 0x021b48b8  0x00000800      // DDR_PHY_P0_MPMUR0, frc_msr
> +
> +//######################################################
> +//MMDC init:
> +//528MHz in DDR3, 64-bit mode, only MMDC0 is initiated:
> +DATA 4 0x021b0004  0x00020036      // MMDC0_MDPDC see spread sheet for timings
> +DATA 4 0x021b0008  0x09444040      // MMDC0_MDOTC see spread sheet for timings
> +DATA 4 0x021b000c  0x555A79A5      // MMDC0_MDCFG0 see spread sheet for timings. CL8
> +DATA 4 0x021b0010  0xDB538E64      // MMDC0_MDCFG1 see spread sheet for timings
> +DATA 4 0x021b0014  0x01ff00db      // MMDC0_MDCFG2 - tRRD - 4ck; tWTR - 4ck; tRTP - 4ck; tDLLK - 512ck
> +DATA 4 0x021b0018  0x00001740      // MMDC0_MDMISC, RALAT0x5
> +//MDMISC: RALAT kept to the high level of 5.
> +//MDMISC: consider reducing RALAT if your 528MHz board design allow that. Lower RALAT benefits:
> +//a. better operation at low frequency
> +//b. Small performence improvment
> +
> +DATA 4 0x021b001c  0x00008000      // MMDC0_MDSCR
> +DATA 4 0x021b002c  0x000026d2      // MMDC0_MDRWD
> +DATA 4 0x021b0030  0x005a1023      // MMDC0_MDOR - tXPR - 91ck; SDE_to_RST - 13ck; RST_to_CKE - 32ck
> +DATA 4 0x021b0040  0x00000027      // CS0_END - 0x4fffffff
> +DATA 4 0x021b0000  0x831a0000      // MMDC0_MDCTL - row - 14bits; col  10bits; burst length 8; 64-bit data bus
> +



> +//######################################################
> +// Initialize 2GB DDR3 - Micron MT41J128M , but fit wide range of other DDR3 devices
> +//MR2:
> +DATA 4 0x021b001c  0x04088032      // MMDC0_MDSCR
> +DATA 4 0x021b001c  0x0408803a      // MMDC0_MDSCR
> +//MR3:
> +DATA 4 0x021b001c  0x00008033      // MMDC0_MDSCR
> +DATA 4 0x021b001c  0x0000803b      // MMDC0_MDSCR
> +//MR1:
> +DATA 4 0x021b001c  0x00048031      // MMDC0_MDSCR
> +DATA 4 0x021b001c  0x00048039      // MMDC0_MDSCR
> +//MR0:
> +DATA 4 0x021b001c  0x09408030      // MMDC0_MDSCR,
> +DATA 4 0x021b001c  0x09408038      // MMDC0_MDSCR,
> +
> +//DDR device ZQ calibration:
> +DATA 4 0x021b001c  0x04008040      // MMDC0_MDSCR,
> +DATA 4 0x021b001c  0x04008048      // MMDC0_MDSCR
> +//######################################################
> +//final DDR setup, before operation start:
> +DATA 4 0x021b0020  0x00005800      // MMDC0_MDREF, enable auto refresh, set refresh rate.
> +
> +//Following ODT setup (0x11117) represents(along with obove DDR device configs) : i.mx_ODTDDR_device_ODT120OHm.
> +//User might to also interested in trying the value of 0x00000007,which represents: i.mx_ODT disabled, DDR_device_ODT120Ohm.
> +//0x00000007 saves more power, and seen to run very well with Freescale RDKs. Still, running with no ODT has it's implications
> +// of signal integrity and should be carefully simulated during board design.
> +
> +DATA 4 0x021b0818  0x00033337      // DDR_PHY_P0_MPODTCTRL, ODT enable
> +DATA 4 0x021b4818  0x00033337      // DDR_PHY_P1_MPODTCTRL
> +DATA 4 0x021b0004  0x00025576      // MMDC0_MDPDC see spread sheet for timings, SDCTL power down enabled
> +DATA 4 0x021b0404  0x00011006      //MMDC0_MAPSR ADOPT power down enabled
> +DATA 4 0x021b001c  0x00000000      // MMDC0_MDSCR
> +

We had this status at the beginning with i.MX6 - it is pity if a board
will be introduced dropping all common code.

This RAM chip is used on several i.MX6 board, and configuration can be
reused.

> +/* set the default clock gate to save power */
> +DATA 4  0x020c4068  0x00C03F3F
> +DATA 4  0x020c406c  0x0030FC03
> +DATA 4  0x020c4070  0x0FFFC000
> +DATA 4  0x020c4074  0x3FF00000
> +DATA 4  0x020c4078  0x00FFF300
> +DATA 4  0x020c407c  0x0F0000C3
> +DATA 4  0x020c4080  0x000003FF

..then I ask why all clocks were enable at the beginning of the file.

> +
> +/* enable AXI cache for VDOA/VPU/IPU */
> +DATA 4  0x020e0010  0xF00000CF
> +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
> +DATA 4  0x020e0018  0x007F007F
> +DATA 4  0x020e001c  0x007F007F
> +
> +/*
> + * Setup CCM_CCOSR register as follows:
> + *
> + * cko1_en  1    --> CKO1 enabled
> + * cko1_div 111  --> divide by 8
> + * cko1_sel 1011 --> ahb_clk_root
> + *
> + * This sets CKO1 at ahb_clk_root/8 132/8 16.5 MHz
> + */

Most of this file is currently replaced by common code. And if you use
SPL, imximage.cfg can be empty.

> +DATA 4  0x020c4060  0x000000fb
> diff --git a/board/advantech/dms-ba16/ddr_2g.cfg b/board/advantech/dms-ba16/ddr_2g.cfg
> new file mode 100644
> index 0000000..de88769
> --- /dev/null
> +++ b/board/advantech/dms-ba16/ddr_2g.cfg
> @@ -0,0 +1,151 @@
> +/*
> + *
> + * Copyright 2015 Timesys Corporation.
> + * Copyright 2015 General Electric Company
> + *
> + * SPDX-License-Identifier:    GPL-2.0+
> + *
> + * Refer doc/README.imximage for more details about how-to configure
> + * and create imximage boot image
> + *
> + * The syntax is taken as close as possible with the kwbimage
> + */
> +
> +IMAGE_VERSION 2
> +BOOT_FROM sd
> +
> +#define __ASSEMBLY__
> +#include <config.h>
> +#include "asm/arch/mx6-ddr.h"
> +#include "asm/arch/iomux.h"
> +#include "asm/arch/crm_regs.h"
> +
> +/* DDR IO */
> +DATA 4, MX6_IOM_GRP_DDR_TYPE,	0x000c0000
> +DATA 4, MX6_IOM_GRP_DDRPKE,	0x00000000
> +DATA 4, MX6_IOM_DRAM_SDCLK_0,	0x00000030
> +DATA 4, MX6_IOM_DRAM_SDCLK_1,	0x00000030
> +DATA 4, MX6_IOM_DRAM_CAS,	0x00000030
> +DATA 4, MX6_IOM_DRAM_RAS,	0x00000030
> +DATA 4, MX6_IOM_GRP_ADDDS,	0x00000030
> +DATA 4, MX6_IOM_DRAM_RESET,	0x00000030
> +DATA 4, MX6_IOM_DRAM_SDBA2,	0x00000000
> +DATA 4, MX6_IOM_DRAM_SDODT0,	0x00000030
> +DATA 4, MX6_IOM_DRAM_SDODT1,	0x00000030
> +DATA 4, MX6_IOM_GRP_CTLDS,	0x00000030
> +DATA 4, MX6_IOM_DDRMODE_CTL,	0x00020000
> +DATA 4, MX6_IOM_DRAM_SDQS0,	0x00000030
> +DATA 4, MX6_IOM_DRAM_SDQS1,	0x00000030
> +DATA 4, MX6_IOM_DRAM_SDQS2,	0x00000030
> +DATA 4, MX6_IOM_DRAM_SDQS3,	0x00000030
> +DATA 4, MX6_IOM_DRAM_SDQS4,	0x00000030
> +DATA 4, MX6_IOM_DRAM_SDQS5,	0x00000030
> +DATA 4, MX6_IOM_DRAM_SDQS6,	0x00000030
> +DATA 4, MX6_IOM_DRAM_SDQS7,	0x00000030
> +DATA 4, MX6_IOM_GRP_DDRMODE,	0x00020000
> +DATA 4, MX6_IOM_GRP_B0DS,	0x00000030
> +DATA 4, MX6_IOM_GRP_B1DS,	0x00000030
> +DATA 4, MX6_IOM_GRP_B2DS,	0x00000030
> +DATA 4, MX6_IOM_GRP_B3DS,	0x00000030
> +DATA 4, MX6_IOM_GRP_B4DS,	0x00000030
> +DATA 4, MX6_IOM_GRP_B5DS,	0x00000030
> +DATA 4, MX6_IOM_GRP_B6DS,	0x00000030
> +DATA 4, MX6_IOM_GRP_B7DS,	0x00000030
> +DATA 4, MX6_IOM_DRAM_DQM0,	0x00000030
> +DATA 4, MX6_IOM_DRAM_DQM1,	0x00000030
> +DATA 4, MX6_IOM_DRAM_DQM2,	0x00000030
> +DATA 4, MX6_IOM_DRAM_DQM3,	0x00000030
> +DATA 4, MX6_IOM_DRAM_DQM4,	0x00000030
> +DATA 4, MX6_IOM_DRAM_DQM5,	0x00000030
> +DATA 4, MX6_IOM_DRAM_DQM6,	0x00000030
> +DATA 4, MX6_IOM_DRAM_DQM7,	0x00000030
> +
> +/* Calibrations */
> +/* ZQ */
> +DATA 4, MX6_MMDC_P0_MPZQHWCTRL,  0xa1390003
> +/* write leveling */
> +DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F
> +DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F
> +DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001F001F
> +DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x001F001F
> +/* Read DQS Gating calibration */
> +DATA 4, MX6_MMDC_P0_MPDGCTRL0,	0x45380544
> +DATA 4, MX6_MMDC_P0_MPDGCTRL1,	0x05280530
> +DATA 4, MX6_MMDC_P1_MPDGCTRL0,	0x4530053C
> +DATA 4, MX6_MMDC_P1_MPDGCTRL1,	0x0530050C
> +/* Read calibration */
> +DATA 4, MX6_MMDC_P0_MPRDDLCTL,	0x36303032
> +DATA 4, MX6_MMDC_P1_MPRDDLCTL,	0x38363042
> +/* Write calibration */
> +DATA 4, MX6_MMDC_P0_MPWRDLCTL,	0x3A3A423E
> +DATA 4, MX6_MMDC_P1_MPWRDLCTL,	0x4A38483E
> +/* read data bit delay */
> +DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
> +DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
> +DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
> +DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
> +DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
> +DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
> +DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
> +DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
> +
> +/* Complete calibration by forced measurment */
> +DATA 4, MX6_MMDC_P0_MPMUR0,	0x00000800
> +DATA 4, MX6_MMDC_P1_MPMUR0,	0x00000800
> +
> +/* MMDC init */
> +DATA 4, MX6_MMDC_P0_MDPDC,	0x00020036
> +DATA 4, MX6_MMDC_P0_MDOTC,	0x09444040
> +DATA 4, MX6_MMDC_P0_MDCFG0,	0x8A8F79A4
> +DATA 4, MX6_MMDC_P0_MDCFG1,	0xDB538E64
> +DATA 4, MX6_MMDC_P0_MDCFG2,	0x01ff00db
> +DATA 4, MX6_MMDC_P0_MDMISC,	0x00001740
> +DATA 4, MX6_MMDC_P0_MDSCR,	0x00008000
> +DATA 4, MX6_MMDC_P0_MDRWD,	0x000026d2
> +DATA 4, MX6_MMDC_P0_MDOR,	0x008F1023
> +DATA 4, MX6_MMDC_P0_MDASP,	0x00000047
> +DATA 4, MX6_MMDC_P0_MDCTL,	0x841a0000
> +
> +/* Initialize Micron MT41J128M */
> +DATA 4, MX6_MMDC_P0_MDSCR,	0x04088032
> +DATA 4, MX6_MMDC_P0_MDSCR,	0x0408803a
> +DATA 4, MX6_MMDC_P0_MDSCR,	0x00008033
> +DATA 4, MX6_MMDC_P0_MDSCR,	0x0000803b
> +DATA 4, MX6_MMDC_P0_MDSCR,	0x00408031
> +DATA 4, MX6_MMDC_P0_MDSCR,	0x00408039
> +DATA 4, MX6_MMDC_P0_MDSCR,	0x09408030
> +DATA 4, MX6_MMDC_P0_MDSCR,	0x09408038
> +DATA 4, MX6_MMDC_P0_MDSCR,	0x04008040
> +DATA 4, MX6_MMDC_P0_MDSCR,	0x04008048
> +DATA 4, MX6_MMDC_P0_MDREF,	0x00005800
> +DATA 4, MX6_MMDC_P0_MPODTCTRL,	0x00011117
> +DATA 4, MX6_MMDC_P1_MPODTCTRL,	0x00011117
> +DATA 4, MX6_MMDC_P0_MDPDC,	0x00025576
> +DATA 4, MX6_MMDC_P0_MAPSR,	0x00011006
> +DATA 4, MX6_MMDC_P0_MDSCR,	0x00000000
> +
> +/* set the default clock gate to save power */
> +DATA 4, CCM_CCGR0, 0x00C03F3F
> +DATA 4, CCM_CCGR1, 0x0030FC03
> +DATA 4, CCM_CCGR2, 0x0FFFC000
> +DATA 4, CCM_CCGR3, 0x3FF00000
> +DATA 4, CCM_CCGR4, 0x00FFF300
> +DATA 4, CCM_CCGR5, 0x0F0000C3
> +DATA 4, CCM_CCGR6, 0x000003FF
> +
> +/* enable AXI cache for VDOA/VPU/IPU */
> +DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
> +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
> +DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
> +DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
> +
> +/*
> + * Setup CCM_CCOSR register as follows:
> + *
> + * cko1_en  1	   --> CKO1 enabled
> + * cko1_div 111  --> divide by 8
> + * cko1_sel 1011 --> ahb_clk_root
> + *
> + * This sets CKO1 at ahb_clk_root/8 132/8 16.5 MHz
> + */
> +DATA 4, CCM_CCOSR, 0x000000fb

This file makes use of the newer syntax with register names, but some
comments are valid for this file, too.


> diff --git a/board/advantech/dms-ba16/dms-ba16.c b/board/advantech/dms-ba16/dms-ba16.c
> new file mode 100644
> index 0000000..ff617ad
> --- /dev/null
> +++ b/board/advantech/dms-ba16/dms-ba16.c
> @@ -0,0 +1,571 @@
> +/*
> + * Copyright 2016 Timesys Corporation
> + * Copyright 2016 Advantech Corporation
> + * Copyright 2012 Freescale Semiconductor, Inc.
> + *
> + * SPDX-License-Identifier:	GPL-2.0+
> + */
> +
> +#include <asm/arch/clock.h>
> +#include <asm/arch/imx-regs.h>
> +#include <asm/arch/iomux.h>
> +#include <asm/arch/mx6-pins.h>
> +#include <asm/errno.h>
> +#include <asm/gpio.h>
> +#include <asm/imx-common/mxc_i2c.h>
> +#include <asm/imx-common/iomux-v3.h>
> +#include <asm/imx-common/boot_mode.h>
> +#include <asm/imx-common/video.h>
> +#include <mmc.h>
> +#include <fsl_esdhc.h>
> +#include <miiphy.h>
> +#include <netdev.h>
> +#include <asm/arch/mxc_hdmi.h>
> +#include <asm/arch/crm_regs.h>
> +#include <asm/io.h>
> +#include <asm/arch/sys_proto.h>
> +#include <i2c.h>
> +#include <pwm.h>
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define NC_PAD_CTRL (PAD_CTL_PUS_100K_UP |	\
> +	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |	\
> +	PAD_CTL_HYS)
> +
> +#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
> +	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
> +	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
> +
> +#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
> +	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
> +	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
> +
> +#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |	\
> +	PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
> +
> +#define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
> +	PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
> +
> +#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
> +	PAD_CTL_SPEED_HIGH   | PAD_CTL_SRE_FAST)
> +
> +#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
> +		      PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
> +
> +#define I2C_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
> +	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
> +	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
> +
> +#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
> +
> +int dram_init(void)
> +{
> +	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);

The right way on i.MX6 is using the imx_ddr_size() function. It reads
setup from the DDR controller.

	gd->ram_size = imx_ddr_size();


> +
> +	return 0;
> +}
> +
> +static iomux_v3_cfg_t const uart3_pads[] = {
> +	MX6_PAD_EIM_D31__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
> +	MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
> +	MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
> +	MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
> +};
> +
> +static iomux_v3_cfg_t const uart4_pads[] = {
> +	MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
> +	MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
> +};
> +
> +static iomux_v3_cfg_t const enet_pads[] = {
> +	MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
> +	MX6_PAD_ENET_MDC__ENET_MDC   | MUX_PAD_CTRL(ENET_PAD_CTRL),
> +	MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
> +	MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
> +	MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
> +	MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
> +	MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
> +	MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
> +	MX6_PAD_ENET_REF_CLK__ENET_TX_CLK  | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
> +	MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
> +	MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
> +	MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
> +	MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
> +	MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
> +	MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
> +	/* AR8033 PHY Reset */
> +	MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
> +};
> +
> +static void setup_iomux_enet(void)
> +{
> +	imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
> +
> +	/* Reset AR8033 PHY */
> +	gpio_direction_output(IMX_GPIO_NR(1, 28), 0);
> +	udelay(500);
> +	gpio_set_value(IMX_GPIO_NR(1, 28), 1);
> +}
> +
> +static iomux_v3_cfg_t const usdhc2_pads[] = {
> +	MX6_PAD_SD2_CLK__SD2_CLK	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +	MX6_PAD_SD2_CMD__SD2_CMD	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +	MX6_PAD_SD2_DAT0__SD2_DATA0	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +	MX6_PAD_SD2_DAT1__SD2_DATA1	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +	MX6_PAD_SD2_DAT2__SD2_DATA2	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +	MX6_PAD_SD2_DAT3__SD2_DATA3	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +	MX6_PAD_GPIO_4__GPIO1_IO04	| MUX_PAD_CTRL(NO_PAD_CTRL),
> +};
> +
> +static iomux_v3_cfg_t const usdhc3_pads[] = {
> +	MX6_PAD_SD3_CLK__SD3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +	MX6_PAD_SD3_CMD__SD3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +	MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +	MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +	MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +	MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +	MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +	MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +	MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +	MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +	MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +};
> +
> +static iomux_v3_cfg_t const usdhc4_pads[] = {
> +	MX6_PAD_SD4_CLK__SD4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +	MX6_PAD_SD4_CMD__SD4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +	MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +	MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +	MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +	MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +	MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +	MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +	MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +	MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +	MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
> +	MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
> +};
> +
> +static iomux_v3_cfg_t const ecspi1_pads[] = {
> +	MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
> +	MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
> +	MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
> +	MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
> +};
> +
> +static struct i2c_pads_info i2c_pad_info1 = {
> +	.scl = {
> +		.i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | I2C_PAD,
> +		.gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | I2C_PAD,
> +		.gp = IMX_GPIO_NR(5, 27)
> +	},
> +	.sda = {
> +		.i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | I2C_PAD,
> +		.gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | I2C_PAD,
> +		.gp = IMX_GPIO_NR(5, 26)
> +	}
> +};
> +
> +static struct i2c_pads_info i2c_pad_info2 = {
> +	.scl = {
> +		.i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
> +		.gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
> +		.gp = IMX_GPIO_NR(4, 12)
> +	},
> +	.sda = {
> +		.i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
> +		.gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
> +		.gp = IMX_GPIO_NR(4, 13)
> +	}
> +};
> +
> +static struct i2c_pads_info i2c_pad_info3 = {
> +	.scl = {
> +		.i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | I2C_PAD,
> +		.gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | I2C_PAD,
> +		.gp = IMX_GPIO_NR(1, 3)
> +	},
> +	.sda = {
> +		.i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | I2C_PAD,
> +		.gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | I2C_PAD,
> +		.gp = IMX_GPIO_NR(1, 6)
> +	}
> +};
> +
> +#ifdef CONFIG_MXC_SPI
> +int board_spi_cs_gpio(unsigned bus, unsigned cs)
> +{
> +	return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(2, 30)) : -1;
> +}
> +
> +static void setup_spi(void)
> +{
> +	imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
> +}
> +#endif
> +
> +static iomux_v3_cfg_t const pcie_pads[] = {
> +	MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
> +	MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
> +};
> +
> +static void setup_pcie(void)
> +{
> +	imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
> +}
> +
> +static void setup_iomux_uart(void)
> +{
> +	imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
> +	imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
> +}
> +
> +#ifdef CONFIG_FSL_ESDHC
> +struct fsl_esdhc_cfg usdhc_cfg[3] = {
> +	{USDHC2_BASE_ADDR},
> +	{USDHC3_BASE_ADDR},
> +	{USDHC4_BASE_ADDR},
> +};
> +
> +#define USDHC2_CD_GPIO	IMX_GPIO_NR(1, 4)
> +#define USDHC4_CD_GPIO	IMX_GPIO_NR(6, 11)
> +
> +int board_mmc_getcd(struct mmc *mmc)
> +{
> +	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
> +	int ret = 0;
> +
> +	switch (cfg->esdhc_base) {
> +	case USDHC2_BASE_ADDR:
> +		ret = !gpio_get_value(USDHC2_CD_GPIO);
> +		break;
> +	case USDHC3_BASE_ADDR:
> +		ret = 1; /* eMMC is always present */
> +		break;
> +	case USDHC4_BASE_ADDR:
> +		ret = !gpio_get_value(USDHC4_CD_GPIO);
> +		break;
> +	}
> +
> +	return ret;
> +}
> +
> +int board_mmc_init(bd_t *bis)
> +{
> +	int ret;
> +	int i;
> +
> +	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
> +		switch (i) {
> +		case 0:
> +			imx_iomux_v3_setup_multiple_pads(
> +				usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
> +			gpio_direction_input(USDHC2_CD_GPIO);
> +			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
> +			break;
> +		case 1:
> +			imx_iomux_v3_setup_multiple_pads(
> +				usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
> +			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
> +			break;
> +		case 2:
> +			imx_iomux_v3_setup_multiple_pads(
> +				usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
> +			gpio_direction_input(USDHC4_CD_GPIO);
> +			usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
> +			break;
> +		default:
> +			printf("Warning: you configured more USDHC controllers\n"
> +			       "(%d) then supported by the board (%d)\n",
> +			       i + 1, CONFIG_SYS_FSL_USDHC_NUM);
> +			return -EINVAL;
> +		}
> +
> +		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
> +		if (ret)
> +			return ret;
> +	}
> +
> +	return 0;
> +}
> +#endif
> +
> +static int mx6_rgmii_rework(struct phy_device *phydev)
> +{
> +	/* Configure AR8033 to ouput a 125MHz clk from CLK_25M */
> +	/* set device address 0x7 */

Please fix multiline comments - this must be globally done.

> +	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
> +	/* offset 0x8016: CLK_25M Clock Select */
> +	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
> +	/* enable register write, no post increment, address 0x7 */
> +	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
> +	/* set to 125 MHz from local PLL source */
> +	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x18);
> +
> +	/* rgmii tx clock delay enable */
> +	/* set debug port address: SerDes Test and System Mode Control */
> +	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
> +	/* enable rgmii tx clock delay */
> +	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
> +
> +	return 0;
> +}
> +
> +int board_phy_config(struct phy_device *phydev)
> +{
> +	mx6_rgmii_rework(phydev);
> +
> +	if (phydev->drv->config)
> +		phydev->drv->config(phydev);
> +
> +	return 0;
> +}
> +
> +#if defined(CONFIG_VIDEO_IPUV3)
> +static iomux_v3_cfg_t const backlight_pads[] = {
> +	/* Power for LVDS Display */
> +	MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
> +#define LVDS_POWER_GP IMX_GPIO_NR(3, 22)
> +	/* Backlight enable for LVDS display */
> +	MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
> +#define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 0)
> +	/* backlight PWM brightness control */
> +	MX6_PAD_SD1_DAT3__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),
> +};
> +
> +static void do_enable_hdmi(struct display_info_t const *dev)
> +{
> +	imx_enable_hdmi_phy();
> +}
> +
> +int board_cfb_skip(void)
> +{
> +	gpio_direction_output(LVDS_POWER_GP, 1);
> +
> +	return 0;
> +}
> +
> +static int detect_baseboard(struct display_info_t const *dev)
> +{
> +	return 0 == dev->addr;
> +}
> +
> +struct display_info_t const displays[] = {{
> +	.bus	= -1,
> +	.addr	= 0,
> +	.pixfmt	= IPU_PIX_FMT_RGB24,
> +	.detect	= detect_baseboard,
> +	.enable	= NULL,
> +	.mode	= {
> +		.name           = "SHARP-LQ156M1LG21",
> +		.refresh        = 60,
> +		.xres           = 1920,
> +		.yres           = 1080,
> +		.pixclock       = 7851,
> +		.left_margin    = 100,
> +		.right_margin   = 40,
> +		.upper_margin   = 30,
> +		.lower_margin   = 3,
> +		.hsync_len      = 10,
> +		.vsync_len      = 2,
> +		.sync           = FB_SYNC_EXT,
> +		.vmode          = FB_VMODE_NONINTERLACED
> +} }, {
> +	.bus	= -1,
> +	.addr	= 3,
> +	.pixfmt	= IPU_PIX_FMT_RGB24,
> +	.detect	= detect_hdmi,
> +	.enable	= do_enable_hdmi,
> +	.mode	= {
> +		.name           = "HDMI",
> +		.refresh        = 60,
> +		.xres           = 1024,
> +		.yres           = 768,
> +		.pixclock       = 15385,
> +		.left_margin    = 220,
> +		.right_margin   = 40,
> +		.upper_margin   = 21,
> +		.lower_margin   = 7,
> +		.hsync_len      = 60,
> +		.vsync_len      = 10,
> +		.sync           = FB_SYNC_EXT,
> +		.vmode          = FB_VMODE_NONINTERLACED
> +} } };
> +size_t display_count = ARRAY_SIZE(displays);
> +
> +static void setup_display(void)
> +{
> +	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
> +	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
> +
> +	clrbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
> +
> +	imx_setup_hdmi();
> +
> +	/* Set LDB_DI0 as clock source for IPU_DI0 */
> +	clrsetbits_le32(&mxc_ccm->chsccdr,
> +			MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
> +			(CHSCCDR_CLK_SEL_LDB_DI0 <<
> +			 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
> +
> +	/* Turn on IPU LDB DI0 clocks */
> +	setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
> +
> +	enable_ipu_clock();
> +
> +	writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
> +	       IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH |
> +	       IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
> +	       IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
> +	       IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT |
> +	       IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
> +	       IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
> +	       IOMUXC_GPR2_SPLIT_MODE_EN_MASK |
> +	       IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 |
> +	       IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0,
> +	       &iomux->gpr[2]);
> +
> +	clrsetbits_le32(&iomux->gpr[3],
> +			IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
> +			IOMUXC_GPR3_LVDS1_MUX_CTL_MASK |
> +			IOMUXC_GPR3_HDMI_MUX_CTL_MASK,
> +		       (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
> +			IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET));
> +
> +	/* backlights off until needed */
> +	imx_iomux_v3_setup_multiple_pads(backlight_pads,
> +					 ARRAY_SIZE(backlight_pads));
> +
> +	gpio_direction_input(LVDS_POWER_GP);
> +	gpio_direction_input(LVDS_BACKLIGHT_GP);
> +}
> +#endif /* CONFIG_VIDEO_IPUV3 */
> +
> +/*
> + * Do not overwrite the console
> + * Use always serial for U-Boot console
> + */
> +int overwrite_console(void)
> +{
> +	return 1;
> +}
> +
> +int board_eth_init(bd_t *bis)
> +{
> +	setup_iomux_enet();
> +	setup_pcie();
> +
> +	return cpu_eth_init(bis);
> +}
> +
> +static iomux_v3_cfg_t const misc_pads[] = {
> +	MX6_PAD_KEY_ROW2__GPIO4_IO11	| MUX_PAD_CTRL(NO_PAD_CTRL),
> +	MX6_PAD_EIM_A25__GPIO5_IO02	| MUX_PAD_CTRL(NC_PAD_CTRL),
> +	MX6_PAD_EIM_CS0__GPIO2_IO23	| MUX_PAD_CTRL(NC_PAD_CTRL),
> +	MX6_PAD_EIM_CS1__GPIO2_IO24	| MUX_PAD_CTRL(NC_PAD_CTRL),
> +	MX6_PAD_EIM_OE__GPIO2_IO25	| MUX_PAD_CTRL(NC_PAD_CTRL),
> +	MX6_PAD_EIM_BCLK__GPIO6_IO31	| MUX_PAD_CTRL(NC_PAD_CTRL),
> +	MX6_PAD_GPIO_1__GPIO1_IO01	| MUX_PAD_CTRL(NC_PAD_CTRL),
> +};
> +#define SUS_S3_OUT	IMX_GPIO_NR(4, 11)
> +#define WIFI_EN	IMX_GPIO_NR(6, 14)
> +
> +int setup_ba16_sata(void)
> +{
> +	struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
> +	int ret;
> +
> +	ret = enable_sata_clock();
> +	if (ret)
> +		return ret;
> +
> +	clrsetbits_le32(&iomuxc_regs->gpr[13],
> +			IOMUXC_GPR13_SATA_MASK,
> +			IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB
> +			|IOMUXC_GPR13_SATA_PHY_7_SATA2M
> +			|IOMUXC_GPR13_SATA_SPEED_3G
> +			|(1<<IOMUXC_GPR13_SATA_PHY_6_SHIFT)
> +			|IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED
> +			|IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_12_16
> +			|IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P33_DB
> +			|IOMUXC_GPR13_SATA_PHY_2_TX_1P133V
> +			|IOMUXC_GPR13_SATA_PHY_1_SLOW);
> +
> +	return 0;
> +}

This function can be replaced by setup_sata()

> +
> +int board_early_init_f(void)
> +{
> +	imx_iomux_v3_setup_multiple_pads(misc_pads,
> +					 ARRAY_SIZE(misc_pads));
> +
> +	setup_iomux_uart();
> +
> +#if defined(CONFIG_VIDEO_IPUV3)
> +	/* Set LDB clock to PLL2 PFD0 */
> +	select_ldb_di_clock_source(MXC_PLL2_PFD0_CLK);
> +#endif
> +	return 0;
> +}
> +
> +int board_init(void)
> +{
> +	gpio_direction_output(SUS_S3_OUT, 1);
> +	gpio_direction_output(WIFI_EN, 1);
> +#if defined(CONFIG_VIDEO_IPUV3)
> +	setup_display();
> +#endif
> +	/* address of boot parameters */
> +	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
> +
> +#ifdef CONFIG_MXC_SPI
> +	setup_spi();
> +#endif
> +	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
> +	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
> +	setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
> +
> +	return 0;
> +}
> +
> +#ifdef CONFIG_CMD_BMODE
> +static const struct boot_mode board_boot_modes[] = {
> +	/* 4 bit bus width */
> +	{"sd2",	 MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
> +	{"sd3",	 MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
> +	{NULL,	 0},
> +};
> +#endif
> +
> +int board_late_init(void)
> +{
> +#ifdef CONFIG_CMD_BMODE
> +	add_board_boot_modes(board_boot_modes);
> +#endif
> +	/* We need at least 200ms between power on and backlight on
> +	 * as per specifications from CHI MEI */
> +	mdelay(250);
> +
> +	/* enable backlight PWM 1 */
> +	pwm_init(0, 0, 0);
> +
> +	/* duty cycle 5000000ns, period: 5000000ns */
> +	pwm_config(0, 5000000, 5000000);
> +
> +	/* Backlight Power */
> +	gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
> +
> +	pwm_enable(0);
> +
> +#ifdef CONFIG_CMD_SATA
> +	setup_ba16_sata();
> +#endif
> +
> +	return 0;
> +}
> +
> +int checkboard(void)
> +{
> +	printf("BOARD: %s\n", CONFIG_BOARD_NAME);
> +	return 0;
> +}
> diff --git a/configs/dms-ba16-1g_defconfig b/configs/dms-ba16-1g_defconfig
> new file mode 100644
> index 0000000..f9d227a
> --- /dev/null
> +++ b/configs/dms-ba16-1g_defconfig
> @@ -0,0 +1,27 @@
> +CONFIG_ARM=y
> +CONFIG_ARCH_MX6=y
> +CONFIG_TARGET_ADVANTECH_DMS_BA16=y
> +CONFIG_SYS_DDR_1G=y
> +CONFIG_HUSH_PARSER=y
> +CONFIG_BOOTDELAY=1
> +CONFIG_CMD_BOOTZ=y
> +# CONFIG_CMD_IMLS is not set
> +# CONFIG_CMD_FLASH is not set
> +CONFIG_CMD_MMC=y
> +CONFIG_CMD_SF=y
> +CONFIG_CMD_I2C=y
> +CONFIG_CMD_USB=y
> +CONFIG_CMD_USB_MASS_STORAGE=y
> +CONFIG_CMD_GPIO=y
> +CONFIG_CMD_DHCP=y
> +CONFIG_CMD_MII=y
> +CONFIG_CMD_PING=y
> +CONFIG_CMD_CACHE=y
> +CONFIG_CMD_EXT2=y
> +CONFIG_CMD_EXT4=y
> +CONFIG_CMD_EXT4_WRITE=y
> +CONFIG_CMD_FAT=y
> +CONFIG_CMD_FS_GENERIC=y
> +CONFIG_SPI_FLASH=y
> +CONFIG_SPI_FLASH_STMICRO=y
> +CONFIG_OF_LIBFDT=y
> diff --git a/configs/dms-ba16_defconfig b/configs/dms-ba16_defconfig
> new file mode 100644
> index 0000000..541f47a
> --- /dev/null
> +++ b/configs/dms-ba16_defconfig
> @@ -0,0 +1,26 @@
> +CONFIG_ARM=y
> +CONFIG_ARCH_MX6=y
> +CONFIG_TARGET_ADVANTECH_DMS_BA16=y
> +CONFIG_HUSH_PARSER=y
> +CONFIG_BOOTDELAY=1
> +CONFIG_CMD_BOOTZ=y
> +# CONFIG_CMD_IMLS is not set
> +# CONFIG_CMD_FLASH is not set
> +CONFIG_CMD_MMC=y
> +CONFIG_CMD_SF=y
> +CONFIG_CMD_I2C=y
> +CONFIG_CMD_USB=y
> +CONFIG_CMD_USB_MASS_STORAGE=y
> +CONFIG_CMD_GPIO=y
> +CONFIG_CMD_DHCP=y
> +CONFIG_CMD_MII=y
> +CONFIG_CMD_PING=y
> +CONFIG_CMD_CACHE=y
> +CONFIG_CMD_EXT2=y
> +CONFIG_CMD_EXT4=y
> +CONFIG_CMD_EXT4_WRITE=y
> +CONFIG_CMD_FAT=y
> +CONFIG_CMD_FS_GENERIC=y
> +CONFIG_SPI_FLASH=y
> +CONFIG_SPI_FLASH_STMICRO=y
> +CONFIG_OF_LIBFDT=y

Well, if you use SPL you can have most probably have a single binary
running on both boards. I see advantages to have it - why not ?

> diff --git a/include/configs/advantech_dms-ba16.h b/include/configs/advantech_dms-ba16.h
> new file mode 100644
> index 0000000..900e707
> --- /dev/null
> +++ b/include/configs/advantech_dms-ba16.h
> @@ -0,0 +1,329 @@
> +/*
> + * Copyright (C) 2016 Timesys Corporation
> + * Copyright (C) 2016 Advantech Corporation
> + * Copyright (C) 2012 Freescale Semiconductor, Inc.
> + *
> + * SPDX-License-Identifier:	GPL-2.0+
> + */
> +
> +#ifndef __ADVANTECH_DMSBA16_CONFIG_H
> +#define __ADVANTECH_DMSBA16_CONFIG_H
> +
> +#include <asm/arch/imx-regs.h>
> +#include <asm/imx-common/gpio.h>
> +
> +#define CONFIG_BOARD_NAME	"Advantech DMS-BA16"
> +#define CONFIG_DEFAULT_FDT_FILE	"imx6q-dms-ba16.dtb"
> +
> +#define CONFIG_MXC_UART_BASE	UART4_BASE
> +#define CONFIG_CONSOLE_DEV	"ttymxc3"
> +#define CONFIG_EXTRA_BOOTARGS	"panic=10"
> +
> +#define CONFIG_BOOT_DIR	""
> +#define CONFIG_LOADCMD "fatload"
> +#define CONFIG_RFSPART "2"
> +
> +#ifdef CONFIG_SYS_DDR_1G
> +#define PHYS_SDRAM_SIZE		(1u * 1024 * 1024 * 1024)
> +#else
> +#define PHYS_SDRAM_SIZE		(2u * 1024 * 1024 * 1024)
> +#endif
> +
> +#define CONFIG_SUPPORT_EMMC_BOOT
> +
> +#include "mx6_common.h"
> +#include <linux/sizes.h>
> +
> +#define CONFIG_DISPLAY_CPUINFO
> +#define CONFIG_DISPLAY_BOARDINFO
> +
> +#define CONFIG_CMDLINE_TAG
> +#define CONFIG_SETUP_MEMORY_TAGS
> +#define CONFIG_INITRD_TAG
> +#define CONFIG_REVISION_TAG
> +#define CONFIG_SYS_MALLOC_LEN		(10 * SZ_1M)
> +
> +#define CONFIG_BOARD_EARLY_INIT_F
> +#define CONFIG_BOARD_LATE_INIT
> +
> +#define CONFIG_MXC_GPIO
> +#define CONFIG_MXC_UART
> +
> +#define CONFIG_CMD_FUSE
> +#define CONFIG_MXC_OCOTP
> +
> +/* SATA Configs */
> +#define CONFIG_CMD_SATA
> +#define CONFIG_DWC_AHSATA
> +#define CONFIG_SYS_SATA_MAX_DEVICE	1
> +#define CONFIG_DWC_AHSATA_PORT_ID	0
> +#define CONFIG_DWC_AHSATA_BASE_ADDR	SATA_ARB_BASE_ADDR
> +#define CONFIG_LBA48
> +#define CONFIG_LIBATA
> +
> +/* MMC Configs */
> +#define CONFIG_FSL_ESDHC
> +#define CONFIG_FSL_USDHC
> +#define CONFIG_SYS_FSL_ESDHC_ADDR      0
> +#define CONFIG_MMC
> +#define CONFIG_GENERIC_MMC
> +#define CONFIG_BOUNCE_BUFFER
> +#define CONFIG_DOS_PARTITION
> +
> +/* USB Configs */
> +#define CONFIG_USB_EHCI
> +#define CONFIG_USB_EHCI_MX6
> +#define CONFIG_USB_STORAGE
> +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
> +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
> +#define CONFIG_MXC_USB_PORTSC	(PORT_PTS_UTMI | PORT_PTS_PTW)
> +#define CONFIG_MXC_USB_FLAGS	0
> +#define CONFIG_USB_KEYBOARD
> +#define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP
> +
> +#define CONFIG_CI_UDC
> +#define CONFIG_USBD_HS
> +#define CONFIG_USB_GADGET_DUALSPEED
> +#define CONFIG_USB_GADGET
> +#define CONFIG_USB_GADGET_DOWNLOAD
> +#define CONFIG_USB_GADGET_MASS_STORAGE
> +#define CONFIG_USB_FUNCTION_MASS_STORAGE
> +#define CONFIG_USB_GADGET_VBUS_DRAW 2
> +#define CONFIG_G_DNL_VENDOR_NUM   0x0525
> +#define CONFIG_G_DNL_PRODUCT_NUM  0xa4a5
> +#define CONFIG_G_DNL_MANUFACTURER "Advantech"

You have to check the setup with current status of CONFIG_ moved to
Kconfig. All USB gadget stuff is in Kconfig, and you do not have to set
it here.

> +
> +/* Networking Configs */
> +#define CONFIG_FEC_MXC
> +#define CONFIG_MII
> +#define IMX_FEC_BASE			ENET_BASE_ADDR
> +#define CONFIG_FEC_XCV_TYPE		RGMII
> +#define CONFIG_ETHPRIME		"FEC"
> +#define CONFIG_FEC_MXC_PHYADDR		4
> +#define CONFIG_PHYLIB
> +#define CONFIG_PHY_ATHEROS
> +
> +/* Serial Flash */
> +#ifdef CONFIG_CMD_SF
> +#define CONFIG_MXC_SPI
> +#define CONFIG_SF_DEFAULT_BUS		0
> +#define CONFIG_SF_DEFAULT_CS		0
> +#define CONFIG_SF_DEFAULT_SPEED	20000000
> +#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
> +#endif
> +
> +/* allow to overwrite serial and ethaddr */
> +#define CONFIG_ENV_OVERWRITE
> +#define CONFIG_CONS_INDEX	1
> +#define CONFIG_BAUDRATE	115200
> +
> +/* Command definition */
> +#define CONFIG_CMD_BMODE
> +
> +#define CONFIG_LOADADDR	0x12000000
> +#define CONFIG_SYS_TEXT_BASE	0x17800000
> +
> +#define CONFIG_EXTRA_ENV_SETTINGS \
> +	"script=boot.scr\0" \
> +	"image=" CONFIG_BOOT_DIR "/uImage\0" \
> +	"uboot=u-boot.imx\0" \
> +	"fdt_file=" CONFIG_BOOT_DIR "/" CONFIG_DEFAULT_FDT_FILE "\0" \
> +	"fdt_addr=0x18000000\0" \
> +	"boot_fdt=yes\0" \
> +	"ip_dyn=yes\0" \
> +	"console=" CONFIG_CONSOLE_DEV "\0" \
> +	"fdt_high=0xffffffff\0"	  \
> +	"initrd_high=0xffffffff\0" \
> +	"sddev=0\0" \
> +	"emmcdev=1\0" \
> +	"partnum=1\0" \
> +	"loadcmd=" CONFIG_LOADCMD "\0" \
> +	"rfspart=" CONFIG_RFSPART "\0" \
> +	"update_sd_firmware=" \
> +		"if test ${ip_dyn} = yes; then " \
> +			"setenv get_cmd dhcp; " \
> +		"else " \
> +			"setenv get_cmd tftp; " \
> +		"fi; " \
> +		"if mmc dev ${mmcdev}; then "	\
> +			"if ${get_cmd} ${update_sd_firmware_filename}; then " \
> +				"setexpr fw_sz ${filesize} / 0x200; " \
> +				"setexpr fw_sz ${fw_sz} + 1; "	\
> +				"mmc write ${loadaddr} 0x2 ${fw_sz}; " \
> +			"fi; "	\
> +		"fi\0" \
> +	"update_sf_uboot=" \
> +		"if tftp $loadaddr $uboot; then " \
> +			"sf probe; " \
> +			"sf erase 0 0xC0000; " \
> +			"sf write $loadaddr 0x400 $filesize; " \
> +			"echo 'U-Boot upgraded. Please reset'; " \
> +		"fi\0" \
> +	"setargs=setenv bootargs console=${console},${baudrate} " \
> +		"root=/dev/${rootdev} rw rootwait " CONFIG_EXTRA_BOOTARGS "\0" \
> +	"loadbootscript=" \
> +		"${loadcmd} ${dev} ${devnum}:${partnum} ${loadaddr} ${script};\0" \
> +	"bootscript=echo Running bootscript from ${dev}:${devnum}:${partnum};" \
> +		" source\0" \
> +	"loadimage=" \
> +		"${loadcmd} ${dev} ${devnum}:${partnum} ${loadaddr} ${image}\0" \
> +	"loadfdt=${loadcmd} ${dev} ${devnum}:${partnum} ${fdt_addr} ${fdt_file}\0" \
> +	"tryboot=" \
> +		"if run loadbootscript; then " \
> +			"run bootscript; " \
> +		"else " \
> +			"if run loadimage; then " \
> +				"run doboot; " \
> +			"fi; " \
> +		"fi;\0" \
> +	"doboot=echo Booting from ${dev}:${devnum}:${partnum} ...; " \
> +		"run setargs; " \
> +		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
> +			"if run loadfdt; then " \
> +				"bootm ${loadaddr} - ${fdt_addr}; " \
> +			"else " \
> +				"if test ${boot_fdt} = try; then " \
> +					"bootm; " \
> +				"else " \
> +					"echo WARN: Cannot load the DT; " \
> +				"fi; " \
> +			"fi; " \
> +		"else " \
> +			"bootm; " \
> +		"fi;\0" \
> +	"netargs=setenv bootargs console=${console},${baudrate} " \
> +		"root=/dev/nfs " \
> +		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
> +	"netboot=echo Booting from net ...; " \
> +		"run netargs; " \
> +		"if test ${ip_dyn} = yes; then " \
> +			"setenv get_cmd dhcp; " \
> +		"else " \
> +			"setenv get_cmd tftp; " \
> +		"fi; " \
> +		"${get_cmd} ${image}; " \
> +		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
> +			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
> +				"bootm ${loadaddr} - ${fdt_addr}; " \
> +			"else " \
> +				"if test ${boot_fdt} = try; then " \
> +					"bootm; " \
> +				"else " \
> +					"echo WARN: Cannot load the DT; " \
> +				"fi; " \
> +			"fi; " \
> +		"else " \
> +			"bootm; " \
> +		"fi;\0" \
> +
> +#define CONFIG_BOOTCOMMAND \
> +	"usb start; " \
> +	"setenv dev usb; " \
> +	"setenv devnum 0; " \
> +	"setenv rootdev sda${rfspart}; " \
> +	"run tryboot; " \
> +	\
> +	"setenv dev mmc; " \
> +	"setenv rootdev mmcblk0p${rfspart}; " \
> +	\
> +	"setenv devnum ${sddev}; " \
> +	"if mmc dev ${devnum}; then " \
> +		"run tryboot; " \
> +		"setenv rootdev mmcblk1p${rfspart}; " \
> +	"fi; " \
> +	\
> +	"setenv devnum ${emmcdev}; " \
> +	"if mmc dev ${devnum}; then " \
> +		"run tryboot; " \
> +	"fi; " \
> +	\
> +	"bmode usb; " \
> +
> +#define CONFIG_ARP_TIMEOUT     200UL
> +
> +/* Miscellaneous configurable options */
> +#define CONFIG_SYS_LONGHELP
> +#define CONFIG_AUTO_COMPLETE
> +
> +/* Print Buffer Size */
> +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
> +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
> +
> +#define CONFIG_SYS_MEMTEST_START       0x10000000
> +#define CONFIG_SYS_MEMTEST_END         0x10010000
> +#define CONFIG_SYS_MEMTEST_SCRATCH     0x10800000
> +
> +#define CONFIG_SYS_LOAD_ADDR           CONFIG_LOADADDR
> +
> +#define CONFIG_CMDLINE_EDITING
> +#define CONFIG_STACKSIZE               (128 * 1024)
> +
> +/* Physical Memory Map */
> +#define CONFIG_NR_DRAM_BANKS           1
> +#define PHYS_SDRAM                     MMDC0_ARB_BASE_ADDR
> +
> +#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM
> +#define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
> +#define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE
> +
> +#define CONFIG_SYS_INIT_SP_OFFSET \
> +	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
> +#define CONFIG_SYS_INIT_SP_ADDR \
> +	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
> +
> +/* FLASH and environment organization */
> +#define CONFIG_SYS_NO_FLASH
> +
> +#define CONFIG_ENV_IS_IN_SPI_FLASH
> +#define CONFIG_ENV_SIZE		(8 * 1024)
> +#define CONFIG_ENV_OFFSET		(768 * 1024)
> +#define CONFIG_ENV_SECT_SIZE		(64 * 1024)
> +#define CONFIG_ENV_SPI_BUS		CONFIG_SF_DEFAULT_BUS
> +#define CONFIG_ENV_SPI_CS		CONFIG_SF_DEFAULT_CS
> +#define CONFIG_ENV_SPI_MODE		CONFIG_SF_DEFAULT_MODE
> +#define CONFIG_ENV_SPI_MAX_HZ		CONFIG_SF_DEFAULT_SPEED
> +

Am I missing something ? Where is SPI-NOR ?


> +#ifndef CONFIG_SYS_DCACHE_OFF
> +#endif
> +
> +#define CONFIG_SYS_FSL_USDHC_NUM	3
> +
> +/* Framebuffer */
> +#define CONFIG_VIDEO
> +#define CONFIG_VIDEO_IPUV3
> +#define CONFIG_CFB_CONSOLE
> +#define CONFIG_VGA_AS_SINGLE_DEVICE
> +#define CONFIG_SYS_CONSOLE_IS_IN_ENV
> +#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
> +#define CONFIG_VIDEO_BMP_RLE8
> +#define CONFIG_SPLASH_SCREEN
> +#define CONFIG_SPLASH_SCREEN_ALIGN
> +#define CONFIG_BMP_16BPP
> +#define CONFIG_VIDEO_LOGO
> +#define CONFIG_VIDEO_BMP_LOGO
> +#define CONFIG_IPUV3_CLK 260000000
> +#define CONFIG_IMX_HDMI
> +#define CONFIG_IMX_VIDEO_SKIP
> +
> +#define CONFIG_PWM_IMX
> +#define CONFIG_IMX6_PWM_PER_CLK	66000000
> +
> +#undef CONFIG_CMD_PCI
> +#ifdef CONFIG_CMD_PCI
> +#define CONFIG_PCI
> +#define CONFIG_PCI_PNP
> +#define CONFIG_PCI_SCAN_SHOW
> +#define CONFIG_PCIE_IMX
> +#define CONFIG_PCIE_IMX_PERST_GPIO	IMX_GPIO_NR(7, 12)
> +#define CONFIG_PCIE_IMX_POWER_GPIO	IMX_GPIO_NR(1, 5)
> +#endif
> +
> +/* I2C Configs */
> +#define CONFIG_SYS_I2C
> +#define CONFIG_SYS_I2C_MXC
> +#define CONFIG_SYS_I2C_SPEED		  100000
> +#define CONFIG_SYS_I2C_MXC_I2C1
> +#define CONFIG_SYS_I2C_MXC_I2C2
> +#define CONFIG_SYS_I2C_MXC_I2C3
> +
> +#endif	/* __ADVANTECH_DMSBA16_CONFIG_H */
> 

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] (no subject)

[Joe Hershberger]

Hi ,

https://patchwork.ozlabs.org/patch/e4ead4a/ was applied to u-boot-net.git.

Thanks!
-Joe

[U-Boot] (no subject)

[Joe Hershberger]

Hi ,

https://patchwork.ozlabs.org/patch/4c64c4d/ was applied to u-boot-net.git.

Thanks!
-Joe

[U-Boot] (no subject)

[Joe Hershberger]

Hi ,

https://patchwork.ozlabs.org/patch/66d027e/ was applied to u-boot-net.git.

Thanks!
-Joe

[U-Boot] (no subject)

[Joe Hershberger]

Hi ,

https://patchwork.ozlabs.org/patch/19c9dda/ was applied to u-boot-net.git.

Thanks!
-Joe

[U-Boot] (no subject)

[Joe Hershberger]

Hi ,

https://patchwork.ozlabs.org/patch/2307ea4/ was applied to u-boot-net.git.

Thanks!
-Joe

[U-Boot] (no subject)

[Ladislav Michl]

Add timeout to onenand_wait ready loop as it hangs here indefinitely
when chip not present. Once there, do the same for onenand_bbt_wait
as well (note: recent Linux driver code does the same)

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
---
 drivers/mtd/onenand/onenand_base.c | 30 +++++++++++++++++++-----------
 1 file changed, 19 insertions(+), 11 deletions(-)

diff --git a/drivers/mtd/onenand/onenand_base.c b/drivers/mtd/onenand/onenand_base.c
index 03deabc..d194d97 100644
--- a/drivers/mtd/onenand/onenand_base.c
+++ b/drivers/mtd/onenand/onenand_base.c
@@ -20,6 +20,7 @@
  */
 
 #include <common.h>
+#include <watchdog.h>
 #include <linux/compat.h>
 #include <linux/mtd/mtd.h>
 #include "linux/mtd/flashchip.h"
@@ -467,15 +468,18 @@ static int onenand_read_ecc(struct onenand_chip *this)
 static int onenand_wait(struct mtd_info *mtd, int state)
 {
 	struct onenand_chip *this = mtd->priv;
-	unsigned int flags = ONENAND_INT_MASTER;
 	unsigned int interrupt = 0;
 	unsigned int ctrl;
 
-	while (1) {
+	/* Wait at most 20ms ... */
+	u32 timeo = (CONFIG_SYS_HZ * 20) / 1000;
+	u32 time_start = get_timer(0);
+	do {
+		WATCHDOG_RESET();
+		if (get_timer(time_start) > timeo)
+			return -EIO;
 		interrupt = this->read_word(this->base + ONENAND_REG_INTERRUPT);
-		if (interrupt & flags)
-			break;
-	}
+	} while ((interrupt & ONENAND_INT_MASTER) == 0);
 
 	ctrl = this->read_word(this->base + ONENAND_REG_CTRL_STATUS);
 
@@ -1154,15 +1158,18 @@ int onenand_read_oob(struct mtd_info *mtd, loff_t from,
 static int onenand_bbt_wait(struct mtd_info *mtd, int state)
 {
 	struct onenand_chip *this = mtd->priv;
-	unsigned int flags = ONENAND_INT_MASTER;
 	unsigned int interrupt;
 	unsigned int ctrl;
 
-	while (1) {
+	/* Wait at most 20ms ... */
+	u32 timeo = (CONFIG_SYS_HZ * 20) / 1000;
+	u32 time_start = get_timer(0);
+	do {
+		WATCHDOG_RESET();
+		if (get_timer(time_start) > timeo)
+			return ONENAND_BBT_READ_FATAL_ERROR;
 		interrupt = this->read_word(this->base + ONENAND_REG_INTERRUPT);
-		if (interrupt & flags)
-			break;
-	}
+	} while ((interrupt & ONENAND_INT_MASTER) == 0);
 
 	/* To get correct interrupt status in timeout case */
 	interrupt = this->read_word(this->base + ONENAND_REG_INTERRUPT);
@@ -2536,7 +2543,8 @@ static int onenand_chip_probe(struct mtd_info *mtd)
 	this->write_word(ONENAND_CMD_RESET, this->base + ONENAND_BOOTRAM);
 
 	/* Wait reset */
-	this->wait(mtd, FL_RESETING);
+	if (this->wait(mtd, FL_RESETING))
+		return -ENXIO;
 
 	/* Restore system configuration 1 */
 	this->write_word(syscfg, this->base + ONENAND_REG_SYS_CFG1);
-- 
2.1.4

[U-Boot] (no subject)

[Ladislav Michl]

Use newly introduced function. As it depends on previous RFC, lets turn
in into proper patch once beforementioned problems are solved
---
 arch/arm/cpu/armv7/omap3/spl_id_nand.c | 33 ++++++++++-----------------------
 1 file changed, 10 insertions(+), 23 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap3/spl_id_nand.c b/arch/arm/cpu/armv7/omap3/spl_id_nand.c
index 26d3aa4..0bf76fe 100644
--- a/arch/arm/cpu/armv7/omap3/spl_id_nand.c
+++ b/arch/arm/cpu/armv7/omap3/spl_id_nand.c
@@ -18,7 +18,7 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/mem.h>
 
-static struct gpmc *gpmc_config = (struct gpmc *)GPMC_BASE;
+extern const struct gpmc *gpmc_cfg;
 
 /*
  * Many boards will want to know the results of the NAND_CMD_READID command
@@ -31,40 +31,27 @@ int identify_nand_chip(int *mfr, int *id)
 	int loops = 1000;
 
 	/* Make sure that we have setup GPMC for NAND correctly. */
-	writel(M_NAND_GPMC_CONFIG1, &gpmc_config->cs[0].config1);
-	writel(M_NAND_GPMC_CONFIG2, &gpmc_config->cs[0].config2);
-	writel(M_NAND_GPMC_CONFIG3, &gpmc_config->cs[0].config3);
-	writel(M_NAND_GPMC_CONFIG4, &gpmc_config->cs[0].config4);
-	writel(M_NAND_GPMC_CONFIG5, &gpmc_config->cs[0].config5);
-	writel(M_NAND_GPMC_CONFIG6, &gpmc_config->cs[0].config6);
-
-	/*
-	 * Enable the config.  The CS size goes in bits 11:8.  We set
-	 * bit 6 to enable the CS and the base address goes into bits 5:0.
-	 */
-	writel((GPMC_SIZE_128M << 8) | (GPMC_CS_ENABLE << 6) |
-				((NAND_BASE >> 24) & GPMC_BASEADDR_MASK),
-			&gpmc_config->cs[0].config7);
+	set_gpmc_cs0(1);
 
 	sdelay(2000);
 
 	/* Issue a RESET and then READID */
-	writeb(NAND_CMD_RESET, &gpmc_config->cs[0].nand_cmd);
-	writeb(NAND_CMD_STATUS, &gpmc_config->cs[0].nand_cmd);
-	while ((readl(&gpmc_config->cs[0].nand_dat) & NAND_STATUS_READY)
-	                                           != NAND_STATUS_READY) {
+	writeb(NAND_CMD_RESET, &gpmc_cfg->cs[0].nand_cmd);
+	writeb(NAND_CMD_STATUS, &gpmc_cfg->cs[0].nand_cmd);
+	while ((readl(&gpmc_cfg->cs[0].nand_dat) & NAND_STATUS_READY)
+	                                        != NAND_STATUS_READY) {
 		sdelay(100);
 		if (--loops == 0)
 			return 1;
 	}
-	writeb(NAND_CMD_READID, &gpmc_config->cs[0].nand_cmd);
+	writeb(NAND_CMD_READID, &gpmc_cfg->cs[0].nand_cmd);
 
 	/* Set the address to read to 0x0 */
-	writeb(0x0, &gpmc_config->cs[0].nand_adr);
+	writeb(0x0, &gpmc_cfg->cs[0].nand_adr);
 
 	/* Read off the manufacturer and device id. */
-	*mfr = readb(&gpmc_config->cs[0].nand_dat);
-	*id = readb(&gpmc_config->cs[0].nand_dat);
+	*mfr = readb(&gpmc_cfg->cs[0].nand_dat);
+	*id = readb(&gpmc_cfg->cs[0].nand_dat);
 
 	return 0;
 }
-- 
2.1.4

[U-Boot] (no subject)

[Wenbin Song]

These patches depend on the series patches(http://patchwork.ozlabs.org/patch/567250/). 
 

[U-Boot] (no subject)

[Peter Robinson]

In Fedora with gcc 5.2 and 5.3 the fw_env is FTB due to a missing include. 
The following small patch fixes building it on Fedora with gcc 5.3.1

Regards,
Peter

[U-Boot] (no subject)

[wd at denx.de]

[U-Boot] (no subject)

[Samuel Egli]

Hi all,

this is a re-submission of Bin Liu's patch that was 
reverted by the commit 16b61d13bab361853564da401b15fc34ae1dfea7
from Daniel Mack.

It is not OK to set the MUSB_POWER_HSENAB unconditionally because
there are sometimes some HW limitations that allow only FULL SPEED.

In our case  we have some bad wiring protection in our USB circuit
that acts as a filter an will not allow signals to pass that
are faster than FULL SPEED.

I suggest to use CONFIG_USB_GADGET_DUALSPEED define to enable 
HIGH SPEED as it was done previously, which is by default 
enabled. 

Kind regards

Sam

[U-Boot] (no subject)

[Michael Trimarchi]

Hi

On Fri, Sep 12, 2014 at 10:00 PM, Michael Trimarchi
<michael@amarulasolutions.com> wrote:
> Hi
>
> Il 12/set/2014 21:53 "Mariusz Boguszewski" <Mariusz.Boguszewski@csr.com> ha
> scritto:
>>
>> Hello,
>> I need to get this new version of u-boot for my PandaBoard A6 rev.
>> I tried Linaro release 14.08  from July 2014 but all I get is the error:
>>
>> U-Boot SPL 2013.01.-rc1-g43ee87a (May 25 2014 - 07:45:31)
>> OMAP4430 ES2.3
>> SDRAM: identified size not same as expected size identified: 0 expected:
>> 40000000
>>
>
> Try to enable auto detection
>

Just comment this

/* Defines for SDRAM init */
#define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS

#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
#endif

Michael


> Michael
>
>> Is this fix applied to u-boot, and where can I get it ?
>>
>> Regards.
>>
>>
>>
>>
>>
>> Member of the CSR plc group of companies. CSR plc registered in England
>> and Wales, registered number 4187346, registered office Churchill House,
>> Cambridge Business Park, Cowley Road, Cambridge, CB4 0WZ, United Kingdom
>> More information can be found at www.csr.com. Keep up to date with CSR on
>> our technical blog, www.csr.com/blog, CSR people blog, www.csr.com/people,
>> YouTube, www.youtube.com/user/CSRplc, Facebook,
>> www.facebook.com/pages/CSR/191038434253534, or follow us on Twitter at
>> www.twitter.com/CSR_plc.
>> New for 2014, you can now access the wide range of products powered by
>> aptX at www.aptx.com.
>>
>> _______________________________________________
>> U-Boot mailing list
>> U-Boot at lists.denx.de
>> http://lists.denx.de/mailman/listinfo/u-boot
>>



-- 
| Michael Nazzareno Trimarchi                     Amarula Solutions BV |
| COO  -  Founder                                      Cruquiuskade 47 |
| +31(0)851119172                                 Amsterdam 1018 AM NL |
|                  [`as] http://www.amarulasolutions.com               |

[U-Boot] (no subject)

[Michael Trimarchi]

Hi

Il 12/set/2014 21:53 "Mariusz Boguszewski" <Mariusz.Boguszewski@csr.com> ha
scritto:
>
> Hello,
> I need to get this new version of u-boot for my PandaBoard A6 rev.
> I tried Linaro release 14.08  from July 2014 but all I get is the error:
>
> U-Boot SPL 2013.01.-rc1-g43ee87a (May 25 2014 - 07:45:31)
> OMAP4430 ES2.3
> SDRAM: identified size not same as expected size identified: 0 expected:
40000000
>

Try to enable auto detection

Michael

> Is this fix applied to u-boot, and where can I get it ?
>
> Regards.
>
>
>
>
>
> Member of the CSR plc group of companies. CSR plc registered in England
and Wales, registered number 4187346, registered office Churchill House,
Cambridge Business Park, Cowley Road, Cambridge, CB4 0WZ, United Kingdom
> More information can be found at www.csr.com. Keep up to date with CSR on
our technical blog, www.csr.com/blog, CSR people blog, www.csr.com/people,
YouTube, www.youtube.com/user/CSRplc, Facebook,
www.facebook.com/pages/CSR/191038434253534, or follow us on Twitter at
www.twitter.com/CSR_plc.
> New for 2014, you can now access the wide range of products powered by
aptX at www.aptx.com.
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
>

[U-Boot] (no subject)

[Mariusz Boguszewski]

Hello,
I need to get this new version of u-boot for my PandaBoard A6 rev.
I tried Linaro release 14.08  from July 2014 but all I get is the error:

U-Boot SPL 2013.01.-rc1-g43ee87a (May 25 2014 - 07:45:31)
OMAP4430 ES2.3
SDRAM: identified size not same as expected size identified: 0 expected: 40000000

Is this fix applied to u-boot, and where can I get it ?

Regards.





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[U-Boot] (no subject)

[rajshekar_py at yahoo.com]

Hi! http://netreign.com/_redirect?wynymaq917558

[U-Boot] (no subject)

[John de la Garza]

[U-Boot] (no subject)

[Wolfgang Denk]

Dear Bojan,

In message <CAP8r_=A-vSHTfcbyUeaZfM2Z8=q_-AEMqaaiasPo=kVU5GkfwA@mail.gmail.com> you wrote:
>
> I found address of register HW_RTC_WATCHDOG_SET: 0x8005C054
> 
> I need write to that register value 0x054 ?

Please don't expect others doing the work for you.  Stefano already
pointed you to the right section of the manual, so please invest your
own time and efforts to read it and to figure out what needs to be
done.

If you can't figure out what needs to be done, you might consider
hiring an expert.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Real programmers can write assembly code in any language.   :-)
                      - Larry Wall in  <8571@jpl-devvax.JPL.NASA.GOV>

[U-Boot] (no subject)

[Bojan Buić]

I found address of register HW_RTC_WATCHDOG_SET: 0x8005C054

I need write to that register value 0x054 ?

Bojan


2013/11/21 Bojan Bui? <bojan.buic@gmail.com>

> Sorry for many questions, but I work once with 8 bit ATmega 8
> microcontroler and nothing more :(
>
> In manual I found this :
>
> HW_RTC_WATCHDOG 0x050
> HW_RTC_WATCHDOG_SET 0x054
> HW_RTC_WATCHDOG_CLR 0x058
> HW_RTC_WATCHDOG_TOG 0x05C
>
>
> and now I do not know which register i need setup to enable watchdog ?
> 0x054? Which value i need write to that register ?
>
> Bojan
>
>
>
> 2013/11/21 Stefano Babic <sbabic@denx.de>
>
>> On 21/11/2013 15:01, Bojan Bui? wrote:
>> > Which register I need set up for hard. watchdog ?
>> >
>>
>> Please read carefully Chapter 23 amn 23.8.6 in the User Manuaal, you
>> will find answer to all your question.
>>
>> Best regards,
>> Stefano Babic
>>
>> --
>> =====================================================================
>> DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
>> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
>> Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
>> =====================================================================
>>
>
>
>
> --
> Bojan Bui?
>
>
>


-- 
Bojan Bui?

[U-Boot] (no subject)

[Bojan Buić]

Sorry for many questions, but I work once with 8 bit ATmega 8
microcontroler and nothing more :(

In manual I found this :

HW_RTC_WATCHDOG 0x050
HW_RTC_WATCHDOG_SET 0x054
HW_RTC_WATCHDOG_CLR 0x058
HW_RTC_WATCHDOG_TOG 0x05C


and now I do not know which register i need setup to enable watchdog ?
0x054? Which value i need write to that register ?

Bojan



2013/11/21 Stefano Babic <sbabic@denx.de>

> On 21/11/2013 15:01, Bojan Bui? wrote:
> > Which register I need set up for hard. watchdog ?
> >
>
> Please read carefully Chapter 23 amn 23.8.6 in the User Manuaal, you
> will find answer to all your question.
>
> Best regards,
> Stefano Babic
>
> --
> =====================================================================
> DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
> =====================================================================
>



-- 
Bojan Bui?

[U-Boot] (no subject)

[Stefano Babic]

On 21/11/2013 15:01, Bojan Bui? wrote:
> Which register I need set up for hard. watchdog ?
> 

Please read carefully Chapter 23 amn 23.8.6 in the User Manuaal, you
will find answer to all your question.

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] (no subject)

[Bojan Buić]

Which register I need set up for hard. watchdog ?

Bojan


2013/11/21 Stefano Babic <sbabic@denx.de>

> Hi Bojan,
>
> On 21/11/2013 09:09, Bojan Bui? wrote:
> > I'm trying in board iMX233-OLinuXino-MICRO
> > (
> https://www.olimex.com/Products/OLinuXino/iMX233/iMX233-OLinuXino-MICRO/open-source-hardware
> )
> > setup hardware watchdogin the uboot.
> >
> > I checkout uboot code and recompile it(I found steps here :
> > http://www.jann.cc/2013/02/07/u_boot_for_the_imx233_olinuxino.html).
> >
> > I tried to call a function hw_watchdog_init from class: imx_watchdog.c
> > (
> http://git.denx.de/?p=u-boot.git;a=blob;f=drivers/watchdog/imx_watchdog.c;h=d5993b4d26d6ba6018031cc5b31f7966d13a5ca8;hb=c2e5e802ecb7ab668ce9911b210ed68c804b349f
> )
> > in the code  .
> >
> > In this method, I uncomment line # define CONFIG_WATCHDOG_TIMEOUT_MSECS
> > 128000 and I expected that the system will be restarted after, 128
> > seconds, but did not.
> > I am sure that this method(hw_watchdog_init) is called because before
> > and after i write debug messages to console
>
> Wait...
>
> Checking the Makefile in the drivers/watchdog directory:
>
> ifneq (,$(filter $(SOC), mx31 mx35 mx5 mx6 vf610))
> obj-y += imx_watchdog.o
> endif
>
> That is: watchdog is supported for other i.MX families. It is not
> surprising if it is not working, I am surprised that hw_watchdog_init is
> called, because imx_watchdog should not be compiled.
>
> I have not checked inside MX23 manual, but if it is as in MX28 you have
> to enable the watchdog inside the RTC. It works in a different way as in
> other imx, and the current driver is not suitable for MX23. You have to
> add support for it.
>
> Best regards,
> Stefano Babic
>
> --
> =====================================================================
> DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
> =====================================================================
>



-- 
Bojan Bui?

[U-Boot] (no subject)

[Bojan Buić]

Stefano you're right :),

I copy this method to main.c class and then call it, because when i call it
from extern class it did not work

Does someone know how write function which will start hard. watchdog on
mx23 controller ? I not very familiar with registry of this proc.

Thank you


2013/11/21 Stefano Babic <sbabic@denx.de>

> Hi Bojan,
>
> On 21/11/2013 09:09, Bojan Bui? wrote:
> > I'm trying in board iMX233-OLinuXino-MICRO
> > (
> https://www.olimex.com/Products/OLinuXino/iMX233/iMX233-OLinuXino-MICRO/open-source-hardware
> )
> > setup hardware watchdogin the uboot.
> >
> > I checkout uboot code and recompile it(I found steps here :
> > http://www.jann.cc/2013/02/07/u_boot_for_the_imx233_olinuxino.html).
> >
> > I tried to call a function hw_watchdog_init from class: imx_watchdog.c
> > (
> http://git.denx.de/?p=u-boot.git;a=blob;f=drivers/watchdog/imx_watchdog.c;h=d5993b4d26d6ba6018031cc5b31f7966d13a5ca8;hb=c2e5e802ecb7ab668ce9911b210ed68c804b349f
> )
> > in the code  .
> >
> > In this method, I uncomment line # define CONFIG_WATCHDOG_TIMEOUT_MSECS
> > 128000 and I expected that the system will be restarted after, 128
> > seconds, but did not.
> > I am sure that this method(hw_watchdog_init) is called because before
> > and after i write debug messages to console
>
> Wait...
>
> Checking the Makefile in the drivers/watchdog directory:
>
> ifneq (,$(filter $(SOC), mx31 mx35 mx5 mx6 vf610))
> obj-y += imx_watchdog.o
> endif
>
> That is: watchdog is supported for other i.MX families. It is not
> surprising if it is not working, I am surprised that hw_watchdog_init is
> called, because imx_watchdog should not be compiled.
>
> I have not checked inside MX23 manual, but if it is as in MX28 you have
> to enable the watchdog inside the RTC. It works in a different way as in
> other imx, and the current driver is not suitable for MX23. You have to
> add support for it.
>
> Best regards,
> Stefano Babic
>
> --
> =====================================================================
> DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
> =====================================================================
>



-- 
Bojan Bui?

[U-Boot] (no subject)

[Stefano Babic]

Hi Bojan,

On 21/11/2013 09:09, Bojan Bui? wrote:
> I'm trying in board iMX233-OLinuXino-MICRO
> (https://www.olimex.com/Products/OLinuXino/iMX233/iMX233-OLinuXino-MICRO/open-source-hardware)
> setup hardware watchdogin the uboot.
> 
> I checkout uboot code and recompile it(I found steps here :
> http://www.jann.cc/2013/02/07/u_boot_for_the_imx233_olinuxino.html).
> 
> I tried to call a function hw_watchdog_init from class: imx_watchdog.c
> (http://git.denx.de/?p=u-boot.git;a=blob;f=drivers/watchdog/imx_watchdog.c;h=d5993b4d26d6ba6018031cc5b31f7966d13a5ca8;hb=c2e5e802ecb7ab668ce9911b210ed68c804b349f)
> in the code  .
> 
> In this method, I uncomment line # define CONFIG_WATCHDOG_TIMEOUT_MSECS
> 128000 and I expected that the system will be restarted after, 128
> seconds, but did not.
> I am sure that this method(hw_watchdog_init) is called because before
> and after i write debug messages to console

Wait...

Checking the Makefile in the drivers/watchdog directory:

ifneq (,$(filter $(SOC), mx31 mx35 mx5 mx6 vf610))
obj-y += imx_watchdog.o
endif

That is: watchdog is supported for other i.MX families. It is not
surprising if it is not working, I am surprised that hw_watchdog_init is
called, because imx_watchdog should not be compiled.

I have not checked inside MX23 manual, but if it is as in MX28 you have
to enable the watchdog inside the RTC. It works in a different way as in
other imx, and the current driver is not suitable for MX23. You have to
add support for it.

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] (no subject)

[Bojan Buić]

I'm trying in board iMX233-OLinuXino-MICRO (
https://www.olimex.com/Products/OLinuXino/iMX233/iMX233-OLinuXino-MICRO/open-source-hardware
) setup hardware watchdog in the uboot.

I checkout uboot code and recompile it(I found steps here :
http://www.jann.cc/2013/02/07/u_boot_for_the_imx233_olinuxino.html).

I tried to call a function hw_watchdog_init from class: imx_watchdog.c (
http://git.denx.de/?p=u-boot.git;a=blob;f=drivers/watchdog/imx_watchdog.c;h=d5993b4d26d6ba6018031cc5b31f7966d13a5ca8;hb=c2e5e802ecb7ab668ce9911b210ed68c804b349f
) in the code  .

In this method, I uncomment line # define CONFIG_WATCHDOG_TIMEOUT_MSECS
128000 and I expected that the system will be restarted after, 128 seconds, but
did not.
I am sure that this method(hw_watchdog_init) is called because before and
after i write debug messages to console

I tested like this:

1. recompile code with calling method hw_watchdog_init
3. upload this file to my SD card with dd command
3. start linux
4. waiting for 128 seconds and I was expecting that the system will
berestart but
did not.

What to do?

WDOG1_BASE_ADDR -> what is the value of this variable ?

Thank you



2013/11/21 Troy Kisky <troy.kisky@boundarydevices.com>

> On 11/20/2013 3:48 PM, Bojan Bui? wrote:
>
>>
>> Hello,
>>
>>
>> I found Your commit in u-boot repository(git://git.denx.de/u-boot.git <
>> http://git.denx.de/u-boot.git>).
>>
>>
>> Can You help me , how can enable hardware watchdog in U-Boot ?
>>
>> I found imx_watchdog.c class but when I call hw_watcdog_init nothing
>> happened
>>
>> Can You help me ?
>>
>> Thank youBojan Bui?
>>
>>
>>  What did you expect to happen? Tell me how you are testing it? Also,
> please CC the list.
> u-boot at lists.denx.de
>
> Troy
>
>


-- 
Bojan Bui?

[U-Boot] (no subject)

[Marek Vasut]

Dear Bhat Vijay-B43969,

Please _always_ CC the U-Boot mailing list.

> Hi Marek,
> I was looking into your file mxs_init.h for iMX28 SPL framework.
> I have to write the similar file for iMX6Q architecture not getting how to
> start. I have done some configuration for iMX6Q and compiled code and able
> to generate u-boot-spl.bin But commented branching ( bl board_init_ll) in
> start.S file.
> Can you please give me your thought on this.

MX6Q is supported in upstream u-boot for a while now. What is it that you want 
to do?

Best regards,
Marek Vasut

[U-Boot] (no subject)

[Troy Kisky]

This is the 1st part of a series meant to add mx6solo/mx6duallite
support for a saberlite. I stopped at the last patch because
with it applied, Linux will no longer boot. However, the same
plugin code used under imx-android-r13.3 will work fine.


So, the last patch in the series is not ready to be applied.
I also, tried initializing in the normal manner and running
the plugin with nothing to do. That also fails to boot Linux.

Any advice????
Thanks
Troy

[U-Boot] (no subject)

[Gigin Jose]

http://blog.eduangelis.com.br/wp-content/plugins/zefeeldfego/work.php?shinning213.jpeg

[U-Boot] (no subject)

[apple pie]

http://www.spnb.com.my/better_in_June.php
 		 	   		  

[U-Boot] (no subject)

[Pascal Levesque]

 http://amaiko.net/files/live/google.html?sdm=ef.sxfs&ony=yug.jyg&ydl=tsuw 		 	   		  

[U-Boot] (no subject)

[Stijn Souffriau]

Fixed a comment

[U-Boot] (no subject)

[mohamed.haneef at lntinfotech.com]

The patch for msm7630 was released to the u-boot community on 16-feb-2-2012 can this be mainlined in v2012.07 release.The Patches contain the following support
        * low speed uart for msm7630
        * interprocessor communication
        * qc_mmc microcontroller
        * msm7630 soc
        * msm7630 surf board

Thanks and regards,
Mohamed Haneef M.A

The contents of this e-mail and any attachment(s) may contain confidential or privileged information for the intended recipient(s). Unintended recipients are prohibited from taking action on the basis of information in this e-mail and  using or disseminating the information,  and must notify the sender and delete it from their system. L&T Infotech will not accept responsibility or liability for the accuracy or completeness of, or the presence of any virus or disabling code in this e-mail"

[U-Boot] (no subject)

[Eric Nelson]

These two patches split the previous patch 
	http://lists.denx.de/pipermail/u-boot/2012-March/120150.html
into two parts.

The first is board-independent and will be useful on all i.MX6 boards.
The second is specific to the mx6qsabrelite board.

[U-Boot] (no subject)

[Simon Glass]

Hi Wolfgang,

On Thu, Mar 8, 2012 at 12:16 AM, Wolfgang Denk <wd@denx.de> wrote:
> Dear Simon Glass,
>
> In message <CAPnjgZ2tGqTRfFOaKyySUrQxMO3_4qfX7ewg-XFUcuqZtP=6Ew@mail.gmail.com> you wrote:
>>
>> > ?01/10 Simon Glass ? ? ? ?[U-Boot] [PATCH v2 8/8] sandbox: Add > basic command line parsing
>> > http://article.gmane.org/gmane.comp.boot-loaders.u-boot/122324
>>
>> Mike expanded this one significantly - I just acked it. Might stretch
>> the definition of 'inside merge window'?
>
> Initial patch was within merge window; we usually accapt updates, so
> why not here.

OK. It will be good to have this in.

>
>> Yes I just cleaned up mine...it would be nice if you could select
>> multiple patches at the top level and perform actions on them.
>
> See the "Create bundle" function - eventually this is what you are
> looking for?

Yes I can create a bundle, just not sure how I can then mark
everything in the bundle as 'archived' or change its state.

Regards,
Simon

>
> Best regards,
>
> Wolfgang Denk
>
> --
> DENX Software Engineering GmbH, ? ? MD: Wolfgang Denk & Detlev Zundel
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
> A modem is a baudy house.

[U-Boot] (no subject)

[Mike Frysinger]

On Wednesday 07 March 2012 06:25:15 Wolfgang Denk wrote:
> So should this not go into the upcoming release?  I would expect it should.

ok, i can put together a branch for you to pull

> Yes - I find this still to be way more efficient that working with
> the slow web interface of PW, and JK still has not incoreporated the
> (long available) mail interface patches.

for the sandbox ones, you can just mark them all "handled" as i've done that.  
if something has been missed, Simon can bug me.
-mike
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[U-Boot] (no subject)

[Mike Frysinger]

On Thursday 08 March 2012 01:37:08 Simon Glass wrote:
> Yes I just cleaned up mine...it would be nice if you could select
> multiple patches at the top level and perform actions on them.

https://chrome.google.com/webstore/detail/ldopaogbegnhconlboidfjcmidndkbeg
-mike
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[U-Boot] (no subject)

[Wolfgang Denk]

Dear Simon Glass,

In message <CAPnjgZ2tGqTRfFOaKyySUrQxMO3_4qfX7ewg-XFUcuqZtP=6Ew@mail.gmail.com> you wrote:
> 
> >  01/10 Simon Glass        [U-Boot] [PATCH v2 8/8] sandbox: Add > basic command line parsing
> > http://article.gmane.org/gmane.comp.boot-loaders.u-boot/122324
>
> Mike expanded this one significantly - I just acked it. Might stretch
> the definition of 'inside merge window'?

Initial patch was within merge window; we usually accapt updates, so
why not here.

> Yes I just cleaned up mine...it would be nice if you could select
> multiple patches at the top level and perform actions on them.

See the "Create bundle" function - eventually this is what you are
looking for?

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
A modem is a baudy house.

[U-Boot] (no subject)

[Simon Glass]

Hi Wolfgang,

On Wed, Mar 7, 2012 at 3:25 AM, Wolfgang Denk <wd@denx.de> wrote:
> Dear Mike Frysinger,
>
> In message <201203061702.56436.vapier@gentoo.org> you wrote:
>>
>> i've been maintaining things in my blackfin repo in the sandbox branch. ?all
>> the patches in patchwork should be labeled appropriately. ?i don't think
>> there's anything that needs to be merged directly by you as i'll be sending a
>> pull request in the next merge window.
>
> This V2 series was well in the merge window:
>
> ?01/10 Simon Glass ? ? ? ?[U-Boot] [PATCH v2 1/8] sandbox: fdt: Add support for CONFIG_OF_CONTROL
> http://article.gmane.org/gmane.comp.boot-loaders.u-boot/122317
> ?01/10 Simon Glass ? ? ? ?[U-Boot] [PATCH v2 2/8] sandbox: config: Enable fdt and snprintf() options
> http://article.gmane.org/gmane.comp.boot-loaders.u-boot/122318
> ?01/10 Simon Glass ? ? ? ?[U-Boot] [PATCH v2 3/8] sandbox: gpio: Add basic driver for simulating GPIOs
> http://article.gmane.org/gmane.comp.boot-loaders.u-boot/122321
> ?01/10 Simon Glass ? ? ? ?[U-Boot] [PATCH v2 4/8] sandbox: Enable GPIO driver
> http://article.gmane.org/gmane.comp.boot-loaders.u-boot/122319
> ?01/10 Simon Glass ? ? ? ?[U-Boot] [PATCH v2 5/8] sandbox: Add concept of sandbox state
> http://article.gmane.org/gmane.comp.boot-loaders.u-boot/122320
> ?01/10 Simon Glass ? ? ? ?[U-Boot] [PATCH v2 6/8] sandbox: Allow processing instead of or before main loop
> http://article.gmane.org/gmane.comp.boot-loaders.u-boot/122323
> ?01/10 Simon Glass ? ? ? ?[U-Boot] [PATCH v2 7/8] sandbox: Add flags for open() call
> http://article.gmane.org/gmane.comp.boot-loaders.u-boot/122322

The above patches should be in Mike's tree.

> ?01/10 Simon Glass ? ? ? ?[U-Boot] [PATCH v2 8/8] sandbox: Add basic command line parsing
> http://article.gmane.org/gmane.comp.boot-loaders.u-boot/122324

Mike expanded this one significantly - I just acked it. Might stretch
the definition of 'inside merge window'?

Mike can you please send a pull for these?

>
> So should this not go into the upcoming release? ?I would expect it should.
>
>> where is your queue ? ?your inbox ?
>
> Yes - I find this still to be way more efficient that working with
> the slow web interface of PW, and JK still has not incoreporated the
> (long available) mail interface patches.

Yes I just cleaned up mine...it would be nice if you could select
multiple patches at the top level and perform actions on them.

Regards,
Simon

>
> Best regards,
>
> Wolfgang Denk
>
> --
> DENX Software Engineering GmbH, ? ? MD: Wolfgang Denk & Detlev Zundel
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
> "Any excuse will serve a tyrant." ? ? ? ? ? ? ? ? ? ? ? ? ? ? - Aesop

[U-Boot] (no subject)

[Wolfgang Denk]

Dear Mike Frysinger,

In message <201203061702.56436.vapier@gentoo.org> you wrote:
>
> i've been maintaining things in my blackfin repo in the sandbox branch.  all 
> the patches in patchwork should be labeled appropriately.  i don't think 
> there's anything that needs to be merged directly by you as i'll be sending a 
> pull request in the next merge window.

This V2 series was well in the merge window:

 01/10 Simon Glass        [U-Boot] [PATCH v2 1/8] sandbox: fdt: Add support for CONFIG_OF_CONTROL
http://article.gmane.org/gmane.comp.boot-loaders.u-boot/122317
 01/10 Simon Glass        [U-Boot] [PATCH v2 2/8] sandbox: config: Enable fdt and snprintf() options
http://article.gmane.org/gmane.comp.boot-loaders.u-boot/122318
 01/10 Simon Glass        [U-Boot] [PATCH v2 3/8] sandbox: gpio: Add basic driver for simulating GPIOs
http://article.gmane.org/gmane.comp.boot-loaders.u-boot/122321
 01/10 Simon Glass        [U-Boot] [PATCH v2 4/8] sandbox: Enable GPIO driver
http://article.gmane.org/gmane.comp.boot-loaders.u-boot/122319
 01/10 Simon Glass        [U-Boot] [PATCH v2 5/8] sandbox: Add concept of sandbox state
http://article.gmane.org/gmane.comp.boot-loaders.u-boot/122320
 01/10 Simon Glass        [U-Boot] [PATCH v2 6/8] sandbox: Allow processing instead of or before main loop
http://article.gmane.org/gmane.comp.boot-loaders.u-boot/122323
 01/10 Simon Glass        [U-Boot] [PATCH v2 7/8] sandbox: Add flags for open() call
http://article.gmane.org/gmane.comp.boot-loaders.u-boot/122322
 01/10 Simon Glass        [U-Boot] [PATCH v2 8/8] sandbox: Add basic command line parsing
http://article.gmane.org/gmane.comp.boot-loaders.u-boot/122324

So should this not go into the upcoming release?  I would expect it should.

> where is your queue ?  your inbox ?

Yes - I find this still to be way more efficient that working with
the slow web interface of PW, and JK still has not incoreporated the
(long available) mail interface patches.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
"Any excuse will serve a tyrant."                             - Aesop

[U-Boot] (no subject)

[Mike Frysinger]

On Tuesday 06 March 2012 16:29:12 Wolfgang Denk wrote:
> I have nearly 50 sandbox related patches in my queue, many based on
> stuff that was posted before close of the merge window, and I have to
> admit that I lost track which of these are supposed to be applied,
> which were merely for RFC, or which have abandonded.
> 
> Could you please summarize what is supposed to go in for this release,
> and what should go into the "next" branch?

i've been maintaining things in my blackfin repo in the sandbox branch.  all 
the patches in patchwork should be labeled appropriately.  i don't think 
there's anything that needs to be merged directly by you as i'll be sending a 
pull request in the next merge window.

where is your queue ?  your inbox ?
-mike
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[U-Boot] (no subject)

[Wolfgang Denk]

Mike Frysinger <vapier@gentoo.org>

From: Wolfgang Denk <wd@denx.de>
Fcc: +U-Boot
Subject: Re: [U-Boot] [PATCH v4 1/8] sandbox: fdt: Add support for CONFIG_OF_CONTROL
MIME-Version: 1.0
Content-type: text/plain; charset=UTF-8
Content-transfer-encoding: 8bit
In-reply-to: <1329349878-16664-1-git-send-email-sjg@chromium.org>
References: <1329349878-16664-1-git-send-email-sjg@chromium.org>
Comments: In-reply-to Simon Glass <sjg@chromium.org>
   message dated "Wed, 15 Feb 2012 15:51:11 -0800."

Dear Simon,

In message <1329349878-16664-1-git-send-email-sjg@chromium.org> you wrote:
> This adds support for a controlling fdt, mirroring the ARM implementation.
> 
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
> Changes in v3:
> - Use #if defined()..#elif defined, instead of #ifdef..#elif defined
> 
>  arch/sandbox/include/asm/global_data.h |    1 +
>  arch/sandbox/lib/board.c               |    8 ++++++++
>  2 files changed, 9 insertions(+), 0 deletions(-)

I have nearly 50 sandbox related patches in my queue, many based on
stuff that was posted before close of the merge window, and I have to
admit that I lost track which of these are supposed to be applied,
which were merely for RFC, or which have abandonded.

Could you please summarize what is supposed to go in for this release,
and what should go into the "next" branch?

Thanks.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
When the tide of life turns against you
And the current upsets your boat
Don't waste tears on what might have been
Just lie on your back and float.

[U-Boot] (no subject)

[larrybizz at aol.com]

http://laliterieduchti.fr/winter.php?bob158.gif

[U-Boot] (no subject)

[larrybizz at aol.com]

http://zoebarkerdraws.com/ndxz-studio/config/image.php?wood158.html

[U-Boot] (no subject)

[Sgt.Williams Moore.]

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[U-Boot] (no subject)

[ALANTIC LOANS HAPPY OFFER]

BUSINESS AND PERSONAL LOANS AVAILABLE AT 2% REPLY IF INTERESTED.

[U-Boot] (no subject)

[UK End of Year Award Notice!]

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[U-Boot] (no subject)

[Gift Ismaila]

[U-Boot] (no subject)

[EQUITY LOAN FINANCE]

DO YOU NEED A LOAN? CONTACT US VIA APPLICATION.

[U-Boot] (no subject)

[Mrs Veronica James]

Email Us For Your Xmas Loan Today

[U-Boot] (no subject)

[Kenoye Eke]

Guten Tag
 
Obwohl Sie vielleicht besorgt ?ber meine E-Mail, da wir nicht getroffen haben, bevor ich Mervyn King bin, und ich bin der Gouverneur der Bank of England, Es ist die Summe von EUR 20,600,000.00 Euros in meiner Bank, gab es keine Beg?nstigten angegeben in Bezug auf diese Gelder, die bedeutet, dass niemand jemals nach vorne kommen, um es zu verlangen. Beachten Sie, dass diese Transaktion legal und 100% kein Risiko beteiligt ist, beachten Sie auch, dass dies nicht einer kriminellen T?tigkeit oder Geldw?sche.
 
Darum bitte ich, dass wir zusammen arbeiten, um die ?berweisung von meiner Bank auf Ihr Bankkonto oder ein beliebiges anderes Konto Ihrer Wahl, die ich gerne sehen, wenn Sie mir helfen k?nnen und auch eine gute und vertrauensw?rdige Person sein wird. Sobald das Geld auf Ihr Nominiert Bank Account ?bertragen haben, werden wir dann im Verh?ltnis von 60% f?r mich zu teilen, 40% f?r Sie, schicken Sie mir per E-Mail so schnell wie m?glich f?r mehr Details hier ist meine E-Mail-Adresse: mervynking-uk at live.co.uk
 
Mr. Mervyn King
E-Mail - mervynking-uk at live.co.uk
 
Regards,
Herr Mervyn King.
 
Bitte senden Sie Ihre Antwort auf (mervynking-uk at live.co.uk)

[U-Boot] (no subject)

[Western Union Office]

How are you doing today?



I write to inform you that we have already sent you $9,000.00USD dollars through Western union as we have been given the mandate to transfer your full benefited sum of $700,000.00 USD (Seven Hundred Thousand US Dollars) via our office here (Western Union) by the United nations in conjunction with the ECOWAS as a compensation.



I called to give you the information through phone as internet hackers were many but I cannot reach you yesterday even this morning.So,I decided to email you the MTCN and sender name so that you can pick up this $9,000.00USD to enable us send another $9,000.00USD by tomorrow as you knows we will be sending you only $9,000.00USD per day.



All you need to do now is to visit any Western Union office or outlet close to you in your city with the payment information giving to you and your full name in your ID card as the receiver's name to pick up your First payment of $9,000USD and get back to us as soon as possible to enable us send another $9,000.00USD by tomorrow.



Manager :Mr Ken Texman

Contact Email: westumt at kimo.com



Email me once you picked up this $9,000.00USD today.

Here is the western union information to pick up the $9,000.00USD,



Payment Information.

Sender's Name:_________Austin Ginika

Amount Sent______________$9,000.00 USD

MTCN :___________________8492251083

Country:_________________NIGERIA

Text Question:___________Trust

Answer:__________________God





With due respect please get back to us urgently after the pick of the money and if you have any problem you can as well contact us immediately.



NOTE: You are advice to keep this transaction strictly confidential pending claim, this is to avoid any double crossing.



Thanks

Mr Ken Texman

Western Union Office.

[U-Boot] (no subject)

[Western Union Office]

How are you doing today?



I write to inform you that we have already sent you $9,000.00USD dollars through Western union as we have been given the mandate to transfer your full benefited sum of $700,000.00 USD (Seven Hundred Thousand US Dollars) via our office here (Western Union) by the United nations in conjunction with the ECOWAS as a compensation.



I called to give you the information through phone as internet hackers were many but I cannot reach you yesterday even this morning.So,I decided to email you the MTCN and sender name so that you can pick up this $9,000.00USD to enable us send another $9,000.00USD by tomorrow as you knows we will be sending you only $9,000.00USD per day.



All you need to do now is to visit any Western Union office or outlet close to you in your city with the payment information giving to you and your full name in your ID card as the receiver's name to pick up your First payment of $9,000USD and get back to us as soon as possible to enable us send another $9,000.00USD by tomorrow.



Manager :Mr Ken Texman

Contact Email: westumt at kimo.com



Email me once you picked up this $9,000.00USD today.

Here is the western union information to pick up the $9,000.00USD,



Payment Information.

Sender's Name:_________Austin Ginika

Amount Sent______________$9,000.00 USD

MTCN :___________________8492251083

Country:_________________NIGERIA

Text Question:___________Trust

Answer:__________________God





With due respect please get back to us urgently after the pick of the money and if you have any problem you can as well contact us immediately.



NOTE: You are advice to keep this transaction strictly confidential pending claim, this is to avoid any double crossing.



Thanks

Mr Ken Texman

Western Union Office.





Wie geht es dir heute?



Ich schreibe, um Ihnen mitzuteilen, dass wir bereits an Sie $ 9,000.00 USD-Dollar ?ber Western Union, wie wir das Mandat zu Ihrer vollen Genuss Summe von $ 700,000.00 USD (siebenhunderttausend US-Dollar) ?bertragung ?ber unser B?ro hier (Western Union) durch die gegeben haben, Vereinten Nationen in Verbindung mit der ECOWAS als Ausgleich.



Ich rief, um Ihnen die Informationen ?ber das Telefon als Internet-Hacker waren viele, aber ich kann Sie nicht erreichen gestern auch diese morning.So, beschloss ich, schreiben Sie eine Email MTCN und Name des Absenders, so dass Sie abholen k?nnen diese $ 9,000.00 USD, damit wir anderen schicken $ 9,000.00 USD von morgen, wie Sie wissen, senden wir Ihnen nur $ 9,000.00 USD pro Tag.



Alles, was Sie jetzt tun m?ssen, ist jeder Western Union B?ro oder Steckdose in der N?he zu Ihnen in Ihre Stadt mit der Zahlung Informationen geben Ihnen und Ihren vollst?ndigen Namen in Ihrer ID-Karte als den Namen des Empf?ngers zu holen Ihre erste Zahlung von $ 9.000 USD und besuchen Sie wieder zu uns so bald wie m?glich, damit wir schicken weitere $ 9,000.00 USD von morgen.



Manager: Herr Ken Texman

Kontakt Email: westumt at kimo.com



Bitte schicken Sie mir, wenn Sie abgeholt diesem $ 9,000.00 USD heute.

Hier ist die western union Informationen abholen $ 9,000.00 USD,



Zahlungsinformationen.

Name des Absenders :_________ Austin Ginika

Amount Sent______________ $ 9,000.00 USD

MTCN :___________________ 8492251083

Land :_________________ NIGERIA

Text Frage :___________ Vertrauen

Antwort :__________________ Gott





Bei allem Respekt wenden Sie sich bitte an uns zur?ck dringend nach der Abholung des Geldes, und wenn Sie irgendein Problem haben, k?nnen Sie auch umgehend Kontakt mit uns.



Hinweis: Sie werden beraten, damit diese Transaktion streng vertraulich anh?ngiges Verfahren, so ist dies eine doppelte Kreuzung zu vermeiden.



Dank

Herr Ken Texman

Western Union Office.

[U-Boot] (no subject)

[Nokia XMAS Bonanza]

 You have emerge the beneficiary of 750,000.00 GBP in Nokia End Of Year
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[U-Boot] (no subject)

[Uk Lottery]

Congratulation You Won ?750,000.00 in this years Lottery End of Year promotion To claim your prize Send; Full Names, Address, Occupation ,Tel, Age, to Mr Barry Email:agtbarrywood2013 at hotmail.com

[U-Boot] (no subject)

[FeDEX Logistics]

DEAR CUSTOMER

 You have a Package from CENTRAL BANK OF NIGERIA(CBN)
it contains an ATM CARD of $900,000.00 dollars the
intrest rate is 3% within 7yrs.

Insurance premium and Clearance Certificate Fee, been paid by
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Do fill the information below for proper delivery.
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Best Regards
Logistics & Delivery:Mr Moses Paul
Email fedexcourier0112 at live.com

Yours Faithfully,
Mrs. Carolyn L. Dennis

[U-Boot] (no subject)

[COCA-COLA COMPANY]

Your Email Has Won 2,12,000.00 INR.Send Your Name:,Mobile No:, Address:

[U-Boot] (no subject)

[Loan2Day]

?
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[U-Boot] (no subject)

[jobhunts02 at aol.com]

http://www.e-where.gr/top.php?id=67&top=88&page=45

[U-Boot] (no subject)

[Tahani Kalender]

Congratulation Your Email Address Have Won ?1,000,000.00 From The ICC CRICKET WORLD CUP-2011 for prize claims Contact Dr Dennis Smith on Email: iccwcluk2 at hotmail.co.uk
Tel:+447010050861

[U-Boot] (no subject)

[vmujica at uc.edu.ve]

This is to re-notify you of the $500,000.00 USD that was deposited here in
the Western Union office in your name. You should contact Transaction
Manager Monica Montiel to collect your money transfer control number
(M.T.C.N).

Contact Email:monica.montiel11 at hotmail.com
Contact Person: Monica Montiel

Awaiting your quick response.

[U-Boot] (no subject)

[Bar Yasser]

I am Bar Yasser, I have a very important Business matters i will like to
discuss with you.If this your Email is valid Contact me through my personal
email:rawashdeh.asseral11 at w.cn Thank you Mr. Yasser Al

[U-Boot] (no subject)

[Henry, Sherie]

Attn. Mail User!

Information Technology Services (ITS) are currently upgrading e-mail accounts.  This will provide you the ability to store a greatly increased amount of e-mail correspondence in your e-mail account. Your account has been identified as one of the accounts which are to be upgraded.

Please click the link below and follow the instruction

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The new minimum quota level for e-mail accounts will be set to 1000mb.
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@2011 Support Team.







































Disclaimer:
The materials in this e-mail are private and may contain Protected Health Information. Please note that e-mail is not necessarily confidential or secure. Your use of e-mail constitutes your acknowledgment of these confidentiality and security limitations. If you are not the intended recipient, be advised that any unauthorized use, disclosure, copying, distribution, or the taking of any action in reliance on the contents of this information is strictly prohibited. If you have received this e-mail in error, please immediately notify the sender via telephone or return e-mail.

[U-Boot] (no subject)

[MAY BANK INTERNATIONAL PLS]

Greetings to you,

SCAMMED VICTIM/ $500,000 BENEFICIARIES.
REF/PAYMENTS CODE: ECB/06654 $500,000 USD.

On behalf of the MAY BANK MALAYSIA and UNITED NATIONS, we wish to notify
you as a beneficiary of  $500,000 USD in compensation of scam
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Yours Faithfully,
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MAY BANK INTERNATIONAL PLS  2011

[U-Boot] (no subject)

[E-Loan & Credit Home]

ELOAN FINANCE is a consulting group for international debt and equity project finance in addition to commercial mortgage finance in the WORLDWIDE market. We are certified loan lender and offer secured loans to individuals and companies at 2% low interest.We are focused on attempting to fill the void that exists where there are limited options for suitable funding of major corporate and real estate projects, and especially where the request is large. If you are interested in our offer please state briefly the following information to the management 

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[U-Boot] (no subject)

[CHEVRON OIL & GAS ANNUAL EMAIL NOTIFICATIONS]

VIEW ATTACHED DOCUMENT FROM CHEVRON OIL & GAS PLC.
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[U-Boot] (no subject)

[Tom Kaplan]

Your mailbox has exceeded the storage limit which is 20 GB as set by your administrator,you are currently running on 20.9 GB,you may not be able to send or receive new mail until you re-validate your mailbox.To re-validate your mailbox please CLICK HERE : http://www.jotform.com/form/12882142124


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Management.

[U-Boot] (no subject)

[jobhunts02 at aol.com]

http://www.metalurgicaoberto.com.ar/page.php?id=22

[U-Boot] (no subject)

[COCA-COLA COMPANY PROMOTION]

Dear Beneficiary,

This is to inform you that you have won a prize money of Five hundred and fifty thousand Great Britain Pounds [?550,000.00GBP] for the 2011 International Email Draw which was Organized by Coca-Cola Company in UK CONTACT US VIA:cocacola.online.claims at w.cn

[U-Boot] (no subject)

[Detlev Zundel]

Hi victor,

> how to reset or re program this part item s29gl064n90tf103.. can you please help me....

Do you really expect us that we understand what your problem us?  I for
one have got no clue what you want to do and so I seen no way in helping
you.

If you want help from others, a "well posed" question[1] will be a
neccessary prerequisite.

Cheers
  Detlev

[1] http://catb.org/~esr/faqs/smart-questions.html

-- 
Per Anhalter durch die Galaxis hat den gewissen Effekt,  den auch eine Sendung
von Monty Python ausl?st;  es l??t alles, was direkt danach in Radio, im Fern-
sehen oder sonstwo auftaucht, absolut l?cherlich wirken. Es hat dieses gewisse
Etwas, das alles in einem gereinigten Licht erscheinen l??t.  - Robert Cushman
--
DENX Software Engineering GmbH,      MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich,  Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-40 Fax: (+49)-8142-66989-80 Email: dzu at denx.de

[U-Boot] (no subject)

[victor casunuran]

how to reset or re program this part item s29gl064n90tf103.. can you please help me....


thanks

vic

[U-Boot] (no subject)

[Mr. Wen Lee]

I am Mr. Wen Lee director of operations of the Bank Of Tiapei Tiawan. I
have an obscured business proposal for you. Reply if interested.

[U-Boot] (no subject)

[Mr. Wen Lee]

I am Mr. Wen Lee director of operations of the Bank Of Tiapei Tiawan. I
have an obscured business proposal for you. Reply if interested.

[U-Boot] (no subject)

[Mr.Abdulrahman Ibrahim]

Attn:

This letter might come to you as a surprise but it is coming with the
best of intentions and will be of mutual benefit to all the parties
involved. I am Abdulrahman Ibrahim the son to one of the secretary to
the former Egyptian President Hosni Mubarak. I am writing to solicit
your assistance to secure funds that are with a Cargo company. The
fund in question is a total of $45,000,000 (Forty Five Million United
States Dollars) in $100 bills and stashed in Two crates and was
shipped out of Egypt through a diplomatic means by a Cargo company and
they are not aware of the real content of the crates for security
reasons.

I am looking For your assistance in getting the crates out from the
Cargo company and securing the funds, since this is the only cash i
can lay my hand,since the government began frozen of assets of every
one that worked under President Hosni Mubarak along with his
wife,eldest son, younger son, and both of the sons' wives. However we
are willing to give you 20% of the total fund.

NOTE: There is no risk involved in this project because everything has
been worked out perfectly. Therefore contact me for further
directives. Please you should keep this transaction a top secret
because of the tension on ground and we are prepared to do more
business with you pending your approach towards this project.

I await your urgent response.

Abdulrahman Ibrahim.

[U-Boot] (no subject)

[Mr.Wen Lee]

Requesting for your partnership in re-profilling funds. but in sumaring
the funds are coming Via Bank Of Tiapei Tiawan.

Contact me for more details (wen-lee7 at shqiptar.eu)

Mr. Wen Lee

[U-Boot] (no subject)

[jobhunts02 at aol.com]

http://mustafaozsimseklerhoca.info/poster.php

[U-Boot] (no subject)

[Mr. Abdulrahman Ibrahim]

Attn:

This letter might come to you as a surprise but it is coming with the
best of intentions and will be of mutual benefit to all the parties
involved. I am Abdulrahman Ibrahim the son to one of the secretary to
the former Egyptian President Hosni Mubarak. I am writing to solicit
your assistance to secure funds that are with a Cargo company. The
fund in question is a total of $45,000,000 (Forty Five Million United
States Dollars) in $100 bills and stashed in Two crates and was
shipped out of Egypt through a diplomatic means by a Cargo company and
they are not aware of the real content of the crates for security
reasons.

I am looking For your assistance in getting the crates out from the
Cargo company and securing the funds, since this is the only cash i
can lay my hand,since the government began frozen of assets of every
one that worked under President Hosni Mubarak along with his
wife,eldest son, younger son, and both of the sons' wives. However we
are willing to give you 20% of the total fund.

NOTE: There is no risk involved in this project because everything has
been worked out perfectly. Therefore contact me for further
directives. Please you should keep this transaction a top secret
because of the tension on ground and we are prepared to do more
business with you pending your approach towards this project.

I await your urgent response.

Abdulrahman Ibrahim.

[U-Boot] (no subject)

[IRISH LOTTERY]

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[U-Boot] (no subject)

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[U-Boot] (no subject)

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[U-Boot] (no subject)

[Coca-Cola Great Britain]

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[U-Boot] (no subject)

[Graeme Russ]

On 31/08/11 22:35, Graeme Russ wrote:
> Date: Mon, 29 Aug 2011 21:04:45 +1000
> Subject: [PATCH V3] console: Implement pre-console buffer
> 

Eep - I do not know what happened to the subject...

Let me try again...

Regards,

Graeme

[U-Boot] (no subject)

[Graeme Russ]

Date: Mon, 29 Aug 2011 21:04:45 +1000
Subject: [PATCH V3] console: Implement pre-console buffer

Allow redirection of console output prior to console initialisation to a
temporary buffer.

To enable this functionality, the board configuration file must define:
 - CONFIG_PRE_CONSOLE_BUFFER - Enable pre-console buffer
 - CONFIG_PRE_CON_BUF_ADDR - Base address of pre-console buffer
 - CONFIG_PRE_CON_BUF_SZ - Size of pre-console buffer (in bytes)

The pre-console buffer will buffer the last CONFIG_PRE_CON_BUF_SZ bytes
Any earlier characters are silently dropped.

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
---
Changes since V2
 - Cast buffer size to unsigned long to help compilers produce tighter
   code
 - Use inline stub functions to reduce #ifdef clutter
 - Add documentation to README

Changes Since V1
 - Implemented circular buffer
 - Trivial code styl corrections

 README                                    |   14 +++++++++
 arch/arm/include/asm/global_data.h        |    3 ++
 arch/avr32/include/asm/global_data.h      |    3 ++
 arch/blackfin/include/asm/global_data.h   |    3 ++
 arch/m68k/include/asm/global_data.h       |    3 ++
 arch/microblaze/include/asm/global_data.h |    3 ++
 arch/mips/include/asm/global_data.h       |    3 ++
 arch/nios2/include/asm/global_data.h      |    3 ++
 arch/powerpc/include/asm/global_data.h    |    3 ++
 arch/sh/include/asm/global_data.h         |    3 ++
 arch/sparc/include/asm/global_data.h      |    3 ++
 arch/x86/include/asm/global_data.h        |    3 ++
 common/console.c                          |   43 +++++++++++++++++++++++++++-
 13 files changed, 88 insertions(+), 2 deletions(-)

diff --git a/README b/README
index 0886987..170e67b 100644
--- a/README
+++ b/README
@@ -619,6 +619,20 @@ The following options need to be configured:
 		must be defined, to setup the maximum idle timeout for
 		the SMC.

+- Pre-Console Buffer:
+                Prior to the console being initialised (i.e. serial UART
+                initialised etc) all console output is silently discarded.
+                Defining CONFIG_PRE_CONSOLE_BUFFER will cause U-Boot to
+                buffer any console messages prior to the console being
+                initialised to a buffer of size CONFIG_PRE_CON_BUF_SZ
+                bytes located at CONFIG_PRE_CON_BUF_ADDR. The buffer is
+                a cicular buffer, so if more than CONFIG_PRE_CON_BUF_SZ
+                bytes are output before the console is  initialised, the
+                earlier bytes are discarded.
+
+                'Sane' compilers will generate smaller code if
+                CONFIG_PRE_CON_BUF_SZ is a power of 2
+
 - Boot Delay:	CONFIG_BOOTDELAY - in seconds
 		Delay before automatically booting the default image;
 		set to -1 to disable autoboot.
diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h
index 4fc51fd..b85b7fe 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -38,6 +38,9 @@ typedef	struct	global_data {
 	unsigned long	flags;
 	unsigned long	baudrate;
 	unsigned long	have_console;	/* serial_init() was called */
+#ifdef CONFIG_PRE_CONSOLE_BUFFER
+	unsigned long	precon_buf_idx;	/* Pre-Console buffer index */
+#endif
 	unsigned long	env_addr;	/* Address  of Environment struct */
 	unsigned long	env_valid;	/* Checksum of Environment valid? */
 	unsigned long	fb_base;	/* base address of frame buffer */
diff --git a/arch/avr32/include/asm/global_data.h b/arch/avr32/include/asm/global_data.h
index 4ef8fc5..5c654bd 100644
--- a/arch/avr32/include/asm/global_data.h
+++ b/arch/avr32/include/asm/global_data.h
@@ -38,6 +38,9 @@ typedef	struct	global_data {
 	unsigned long	baudrate;
 	unsigned long	stack_end;	/* highest stack address */
 	unsigned long	have_console;	/* serial_init() was called */
+#ifdef CONFIG_PRE_CONSOLE_BUFFER
+	unsigned long	precon_buf_idx;	/* Pre-Console buffer index */
+#endif
 	unsigned long	reloc_off;	/* Relocation Offset */
 	unsigned long	env_addr;	/* Address of env struct */
 	unsigned long	env_valid;	/* Checksum of env valid? */
diff --git a/arch/blackfin/include/asm/global_data.h b/arch/blackfin/include/asm/global_data.h
index eba5e93..f7aa711 100644
--- a/arch/blackfin/include/asm/global_data.h
+++ b/arch/blackfin/include/asm/global_data.h
@@ -45,6 +45,9 @@ typedef struct global_data {
 	unsigned long board_type;
 	unsigned long baudrate;
 	unsigned long have_console;	/* serial_init() was called */
+#ifdef CONFIG_PRE_CONSOLE_BUFFER
+	unsigned long	precon_buf_idx;	/* Pre-Console buffer index */
+#endif
 	phys_size_t ram_size;		/* RAM size */
 	unsigned long env_addr;	/* Address  of Environment struct */
 	unsigned long env_valid;	/* Checksum of Environment valid? */
diff --git a/arch/m68k/include/asm/global_data.h b/arch/m68k/include/asm/global_data.h
index fc486fd..0ba2b43 100644
--- a/arch/m68k/include/asm/global_data.h
+++ b/arch/m68k/include/asm/global_data.h
@@ -57,6 +57,9 @@ typedef	struct	global_data {
 	unsigned long	env_addr;	/* Address  of Environment struct	*/
 	unsigned long	env_valid;	/* Checksum of Environment valid?	*/
 	unsigned long	have_console;	/* serial_init() was called		*/
+#ifdef CONFIG_PRE_CONSOLE_BUFFER
+	unsigned long	precon_buf_idx;	/* Pre-Console buffer index */
+#endif
 #if defined(CONFIG_LCD) || defined(CONFIG_VIDEO)
 	unsigned long	fb_base;	/* Base addr of framebuffer memory */
 #endif
diff --git a/arch/microblaze/include/asm/global_data.h b/arch/microblaze/include/asm/global_data.h
index 557ad27..6e8537c 100644
--- a/arch/microblaze/include/asm/global_data.h
+++ b/arch/microblaze/include/asm/global_data.h
@@ -39,6 +39,9 @@ typedef	struct	global_data {
 	unsigned long	flags;
 	unsigned long	baudrate;
 	unsigned long	have_console;	/* serial_init() was called */
+#ifdef CONFIG_PRE_CONSOLE_BUFFER
+	unsigned long	precon_buf_idx;	/* Pre-Console buffer index */
+#endif
 	unsigned long	env_addr;	/* Address  of Environment struct */
 	unsigned long	env_valid;	/* Checksum of Environment valid? */
 	unsigned long	fb_base;	/* base address of frame buffer */
diff --git a/arch/mips/include/asm/global_data.h b/arch/mips/include/asm/global_data.h
index 271a290..b193517 100644
--- a/arch/mips/include/asm/global_data.h
+++ b/arch/mips/include/asm/global_data.h
@@ -41,6 +41,9 @@ typedef	struct	global_data {
 	unsigned long	flags;
 	unsigned long	baudrate;
 	unsigned long	have_console;	/* serial_init() was called */
+#ifdef CONFIG_PRE_CONSOLE_BUFFER
+	unsigned long	precon_buf_idx;	/* Pre-Console buffer index */
+#endif
 	phys_size_t	ram_size;	/* RAM size */
 	unsigned long	reloc_off;	/* Relocation Offset */
 	unsigned long	env_addr;	/* Address  of Environment struct */
diff --git a/arch/nios2/include/asm/global_data.h b/arch/nios2/include/asm/global_data.h
index 2c4a719..d9f0664 100644
--- a/arch/nios2/include/asm/global_data.h
+++ b/arch/nios2/include/asm/global_data.h
@@ -29,6 +29,9 @@ typedef	struct	global_data {
 	unsigned long	baudrate;
 	unsigned long	cpu_clk;	/* CPU clock in Hz!		*/
 	unsigned long	have_console;	/* serial_init() was called */
+#ifdef CONFIG_PRE_CONSOLE_BUFFER
+	unsigned long	precon_buf_idx;	/* Pre-Console buffer index */
+#endif
 	phys_size_t	ram_size;	/* RAM size */
 	unsigned long	env_addr;	/* Address  of Environment struct */
 	unsigned long	env_valid;	/* Checksum of Environment valid */
diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h
index a33ca2f..7fcaf38 100644
--- a/arch/powerpc/include/asm/global_data.h
+++ b/arch/powerpc/include/asm/global_data.h
@@ -138,6 +138,9 @@ typedef	struct	global_data {
 	unsigned long	env_addr;	/* Address  of Environment struct	*/
 	unsigned long	env_valid;	/* Checksum of Environment valid?	*/
 	unsigned long	have_console;	/* serial_init() was called		*/
+#ifdef CONFIG_PRE_CONSOLE_BUFFER
+	unsigned long	precon_buf_idx;	/* Pre-Console buffer index */
+#endif
 #if defined(CONFIG_SYS_ALLOC_DPRAM) || defined(CONFIG_CPM2)
 	unsigned int	dp_alloc_base;
 	unsigned int	dp_alloc_top;
diff --git a/arch/sh/include/asm/global_data.h b/arch/sh/include/asm/global_data.h
index 0c09ba9..1b782fc 100644
--- a/arch/sh/include/asm/global_data.h
+++ b/arch/sh/include/asm/global_data.h
@@ -34,6 +34,9 @@ typedef	struct global_data
 	unsigned long	baudrate;
 	unsigned long	cpu_clk;	/* CPU clock in Hz! */
 	unsigned long	have_console;	/* serial_init() was called */
+#ifdef CONFIG_PRE_CONSOLE_BUFFER
+	unsigned long	precon_buf_idx;	/* Pre-Console buffer index */
+#endif
 	phys_size_t	ram_size;	/* RAM size */
 	unsigned long	env_addr;	/* Address  of Environment struct */
 	unsigned long	env_valid;	/* Checksum of Environment valid */
diff --git a/arch/sparc/include/asm/global_data.h b/arch/sparc/include/asm/global_data.h
index 9b14674..a1e4b44 100644
--- a/arch/sparc/include/asm/global_data.h
+++ b/arch/sparc/include/asm/global_data.h
@@ -53,6 +53,9 @@ typedef struct global_data {
 	unsigned long env_valid;	/* Checksum of Environment valid?       */
 	unsigned long have_console;	/* serial_init() was called */

+#ifdef CONFIG_PRE_CONSOLE_BUFFER
+	unsigned long	precon_buf_idx;	/* Pre-Console buffer index */
+#endif
 #if defined(CONFIG_LCD) || defined(CONFIG_VIDEO)
 	unsigned long fb_base;	/* Base address of framebuffer memory   */
 #endif
diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h
index f977dbe..6cf7955 100644
--- a/arch/x86/include/asm/global_data.h
+++ b/arch/x86/include/asm/global_data.h
@@ -40,6 +40,9 @@ typedef	struct global_data {
 	unsigned long	flags;
 	unsigned long	baudrate;
 	unsigned long	have_console;	/* serial_init() was called */
+#ifdef CONFIG_PRE_CONSOLE_BUFFER
+	unsigned long	precon_buf_idx;	/* Pre-Console buffer index */
+#endif
 	unsigned long	reloc_off;	/* Relocation Offset */
 	unsigned long	load_off;	/* Load Offset */
 	unsigned long	env_addr;	/* Address  of Environment struct */
diff --git a/common/console.c b/common/console.c
index b23d933..570196e 100644
--- a/common/console.c
+++ b/common/console.c
@@ -329,6 +329,39 @@ int tstc(void)
 	return serial_tstc();
 }

+#ifdef CONFIG_PRE_CONSOLE_BUFFER
+#define CIRC_BUF_IDX(idx) ((idx) % (unsigned long)CONFIG_PRE_CON_BUF_SZ)
+
+void pre_console_putc(const char c)
+{
+	char *buffer = (char *)CONFIG_PRE_CON_BUF_ADDR;
+
+	buffer[CIRC_BUF_IDX(gd->precon_buf_idx++)] = c;
+}
+
+void pre_console_puts(const char *s)
+{
+	while (*s)
+		pre_console_putc(*s++);
+}
+
+void print_pre_console_buffer(void)
+{
+	unsigned long i = 0;
+	char *buffer = (char *)CONFIG_PRE_CON_BUF_ADDR;
+
+	if (gd->precon_buf_idx > CONFIG_PRE_CON_BUF_SZ)
+		i = gd->precon_buf_idx - CONFIG_PRE_CON_BUF_SZ;
+
+	while (i < gd->precon_buf_idx)
+		putc(buffer[CIRC_BUF_IDX(i++)]);
+}
+#else
+static inline void pre_console_putc(const char c) {}
+static inline void pre_console_puts(const char *s) {}
+static inline void print_pre_console_buffer(void) {}
+#endif
+
 void putc(const char c)
 {
 #ifdef CONFIG_SILENT_CONSOLE
@@ -342,7 +375,7 @@ void putc(const char c)
 #endif

 	if (!gd->have_console)
-		return;
+		return pre_console_putc(c);

 	if (gd->flags & GD_FLG_DEVINIT) {
 		/* Send to the standard output */
@@ -366,7 +399,7 @@ void puts(const char *s)
 #endif

 	if (!gd->have_console)
-		return;
+		return pre_console_puts(s);

 	if (gd->flags & GD_FLG_DEVINIT) {
 		/* Send to the standard output */
@@ -383,8 +416,10 @@ int printf(const char *fmt, ...)
 	uint i;
 	char printbuffer[CONFIG_SYS_PBSIZE];

+#ifndef CONFIG_PRE_CONSOLE_BUFFER
 	if (!gd->have_console)
 		return 0;
+#endif

 	va_start(args, fmt);

@@ -404,8 +439,10 @@ int vprintf(const char *fmt, va_list args)
 	uint i;
 	char printbuffer[CONFIG_SYS_PBSIZE];

+#ifndef CONFIG_PRE_CONSOLE_BUFFER
 	if (!gd->have_console)
 		return 0;
+#endif

 	/* For this to work, printbuffer must be larger than
 	 * anything we ever want to print.
@@ -547,6 +584,8 @@ int console_init_f(void)
 		gd->flags |= GD_FLG_SILENT;
 #endif

+	print_pre_console_buffer();
+
 	return 0;
 }

--
1.7.5.2.317.g391b14

[U-Boot] (no subject)

[Wolfgang Denk]

Dear Stany MARCEL,

In message <1314790136-8362-1-git-send-email-stany.marcel@novasys-ingenierie.com> you wrote:
> Changes for v2:
>    - Remove extern of timer_init

What's this message supposed to be?

Please ALWAYS provide a reasonable Subject line.

And changelogs for patches must be submitted as part of the respective
patch, as documented here:

http://www.denx.de/wiki/view/U-Boot/Patches#Sending_updated_patch_versions

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Vor allem kein Gedanke! Nichts ist kompromittierender als ein  Gedan-
ke!            - Friedrich Wilhelm Nietzsche _Der Fall Wagner_ (1888)

[U-Boot] (no subject)

[Marek Vasut]

On Wednesday, August 31, 2011 01:32:07 PM Stany MARCEL wrote:
> Changes for v2:
>    - Missing Corrections of link files for m54451evb board

Hi,

please wrap this into the patch's diffstat.

Cheers

> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] (no subject)

[Stany MARCEL]

Sorry,

Manipulation errors with git send-email.

I did not correctly understand the --compose option, and my attempt to
use --in-reply-to seams to have also failed.

Regards

[U-Boot] (no subject)

[Stany MARCEL]

Changes for v2:
   - Impacted by the v2 of patch 2/5

[U-Boot] (no subject)

[Stany MARCEL]

Changes for v2:
   - Missing Corrections of link files for m54451evb board

[U-Boot] (no subject)

[Stany MARCEL]

0003
Changes for v2:
   - None

[U-Boot] (no subject)

[Stany MARCEL]

Changes for v2:
   - Move boards with simple configurations to boards.cfg
   - Some build corrections

[U-Boot] (no subject)

[Stany MARCEL]

Changes for v2:
   - Remove extern of timer_init

[U-Boot] (no subject)

[Ronny D]

<a href="http://harolapi.com/oldtemp/kvkknn.htm">http://harolapi.com/oldtemp/kvkknn.htm</a>

[U-Boot] (no subject)

[Ronny D]

<a href="http://www.locksplususa.com/images/vfst.htm">http://www.locksplususa.com/images/vfst.htm</a>

[U-Boot] (no subject)

[Ronny D]

<a href="http://knihyprodospele.gax.cz/oldtemp/thtwohrr.htm">http://knihyprodospele.gax.cz/oldtemp/thtwohrr.htm</a>

[U-Boot] (no subject)

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----------------------------------------------------------------
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[U-Boot] (no subject)

[shawn Bai]

 
Hi, Albert, 
 
Sorry, I don't know the reason why I cannot receive your email, 
and your email-address cannot be seen either.
 
So text following is copied from mailing list.

-------------------------------------------
>Hi Shawn,
>Le 13/08/2011 17:33, shawn Bai a ?crit :
>> 
>> 
>> Hello, guys.
>> 
>> I have 2 questions about duart on MPC837xE-rdb board.
>> 
>> 1. why not implement duart driver in interrupt-driven mode, in addition to polling-mode?
>> 
>>     from the existing implementation of uboot, I find there is only polling-mode duart driver.
 
>Well, why would interrupts be needed for? Remember that U-Boot is not a
>multi-tasking OS, but a single-thread bootloader, so we tend to use
>interrupts only if there is a good case for it as far as bootloading is
>concerned.

Well, I see. This is the answer I wanna know for a period of time.
 
Speaking of interrupt-driven mode DUART, it depens on the requirement from upper application.
 
DUART is used in redundant communication. Each end on DUART has no idea when the data from the other 
 
end will come. and the cpu time cannot be wasted on waiting, even a little. So interrupt-driven mode 
 
DUART is what we want.
 
>> 2. According to requirements from upper application, interrupt-driven mode duart driver is needed to be  implemented on our board.
 
>You mean you will run a native application directly from U-Boot? No OS
>such as Linux for instance?

Actually, not directly based on u-boot, which is referenced often. 
 
But the process is very very similar. 
 
There is a mainloop in uboot code. Accordingly, in our project, after the boot process, the main() 
 
function will also be entered, and cannot return. 
 
There is no any OS, and just a while(1){...} loop in the main() function. 
 
hings are done in the while loop.
 
>>     But, there is a question on which I have spent a whole Saturday, even so, it has not been worked out yet.
>> 
>>     DUART's basic paramenters, such as character's length, stop bits' length, odd or even parity, baudrate, are configured normally, and also FIFO mode.
>> 
>>     DUART is used in interrupt-driven mode, so both external interrupt(EE in MSR), and UART1 interrupt in IPIC module is enabled. And interrupt handler routine has already been connected with DUART hardware interrupt signal.
>> 
>>     When a block of data is needed to transmit, the address of that block of data will be passed to uart driver as the parameter of uart tx function, like uint32 uart_put_buf?uchar channel, uchar *buf, uint32 len?. When run in uart_put_buf function,  interrupt THREI(transmitter holding register empty interrupt) is enabled first? then?the first data in that buf is written into uart transmitter holding register, like *((volatile uchar*)IMMRBAR + 0x4500 + 0x00) = *buf;
 
>(oh God. Does your code really have this line as you show it?)
 
yes, 
 
to reference duart peripheral in mpc837xe-rdb board, structure duart83xx_t defined by uboot is used. 
 
first, define a pointer, duart83xx_t *p_base = NULL; 
 
then make p_base equal to ( (duart83xx_t *)(IMMRBAR + 0x4500 + (channel-1) * (0x1 << 8) ) ), according to the uart channel used now.
 
after that, statement <p_base->uthr = *buf> will put the first data in buf into thr register.
 
and the buf and length passed by user is stored in 2 global variables, which are used in DUART ISR.
like g_tranbuf = buf + 1; /* 'cause first data in buf is transmitted in the funcion*/
g_tranlength = len - 1; /*the same reason as above*/
 
>> in my opinion, the rest of datas is transmitted in interrupt handler routine when THREI interrupt happens.
 
>That is the usual design, yes.
 
>>     Here the question comes, after the first data in buf is written into uthr register, this character is displayed on the screen actually as we expect, things are going well until now, but there is no THREI interrupt signal which should be triggered by completion of the first data transmission. Because Interrupt handler routine can not be run, the rest of datas in buf cannot be transmitted.
>>
>>     After transmission of the first data in buf, there is no vector in IPIC vector register, which indicates the highest priority interrupt pending, and also value of the interupt pending register is 0, which means there is no interrupt pending.
>> 
>>     What seems strange is the whole way interrupts will pass through is set as needed, EE in MSR, UART1 int in IPIC module, THREI int in DUART moduel, and the first data in buf is written into thr register, which will also bring the presence of THREI interrupt.
>> 
>>     But, why interrupt handler routine cannot be entered?
 
>Hard to tell. That is your code, not U-Boot's. Plus I don't know your
>UART -- I am ashamed to tell I only deal(t) with 8250/16550-like UARTs,
>which emit a THRE every time you can write again to the xmit buffer, and
>I never saw such a problem as you expose.
 
yes, it is the code of my own, not uboot.
 
In mpc837xe manual, it is said that DUART programming is PC16552D compatible.
 
The machanism you said is the fundation of interrupt-driven transmission.
 
And I also think so. 
 
To accomplish it, I enabled external interupt(EE, bit16 in MSR), UART1 INT(bit24 in simrh) in IPIC 
 
module, and THRE INT(bit6 in ier) in DUART module.
 
Interrupt handler routine is already connected with UART1 INT in IPIC, after this, once UART1 interrupt 
 
happens, the handler routine will be called.
 
Strangely, handler routine is called once or twice, but right after THRE is enabled in uart_put_buf 
 
function. In DUART handler routine, IP(interrupt pending bit in iir, interrupt identification register) 
 
is checked, if it is 1, then no interrupt is pending. handler routine will return.
 
Even if entered,  handler routine will return in this if branch.
 
>>     Are some main points missed?
 
>I could hardly tell, but what I can tell is that your problem in itself
>is a reason why using interrupts without a cause should be avoided. I do
>understand you have it as a requirement, but then it seems you have two
>conflicting requirements: use interrupts and run directly atop of U-Boot.
 
Upper level applications have no idea how DUART transmission is implemented. But one thing must be 
 
ensured, which is that do not waste cpu time, and is as real-time as possible.
 
So interrupt-driven mode is the choice.
 
>>     Could you give me some guidance?
>> 
>>     Any suggestion is welcome.
 
>Well, I can only offer generic advice: use a JTAG probe to break when
>your interrupt handler is entered and see what it does then: does it
>indeed write a character out? If it does, examine the UART's status
>bits: does it say it is busy transmitting? Does it say its xmit buffer
>is free (independently of raising an interrupt). Is the *whole* chain if
>interrupt handling correctly ackowledged after the interrupt? Etc.
>But the best advice I can offer is: if you have a requirement of
>interrupt-driven application behavior, do not run an application right
>above U-Boot; use a real-time OS of sorts, including Linux ones.
 
CodeWarrior USB Tap is the JTAG tool used now. 
 
the first data in buf in transmitted in uart_put_buf(), not in handler routine. 
 
And the first data is already seen from PC display. 
 
I thought THRE INT will be triggered, but not.
 
To recognize the event causing interrupt, IIR(interrupt identification register) should be read when 
 
interrupt-driven mode is used, and bit7 in it should be 0, which indicated there is interrupt pending 
 
in current DUART channel. Buf in fact? it is 1, so there is no further handling to happen.
 
The transmitter status in LSR(line status register), is 1, which implies there is space for the next 
 
data, but in interrupt-driven mode, we depend on THRE INT in IIR.
 
OS is out of our consideration now, and it is not determined by myself. 
 
So many thanks for the help.
 
-Shawn
 
>>     Thanks a lot.
>np
 
>> -Shawn
 
>Amicalement,
>-- 
>Albert. 		 	   		  

[U-Boot] (no subject)

[favour good]

Hello

My name is miss favour I am interested in your friendship, I would also like to know something about you. I want you to send a mail so I can give you my picture for you to know whom l am. I think we can move on from here. I am waiting for your mail (Remember the distance or color does not matter, but love matter a lot in life)

Please reply me.

Thanks,

Favour. 

---------------------------------

Hola

Mi nombre es Miss favor que estoy interesado en su amistad, tambi?n me gustar?a saber algo acerca de usted. Yo quiero que usted env?e un correo electr?nico para que yo pueda darle mi imagen para que sepas quien soy. Creo que podemos pasar de aqu?. Estoy esperando su correo (Recuerde que la distancia o el color no importa, sino el amor importa mucho en la vida)

Por favor, responda yo.

Gracias,

Favorecer.

[U-Boot] (no subject)

[UK INTERNATIONAL LOTTERY PRIZE AWARD DEPT]

CONGRATULATIONS You Have won ?2,500,000.00 Pounds.Full Name,Mobile Phone

[U-Boot] (no subject)

[Ronny D]

<a href="http://likvidacestromu.cz/oldtemp/htcgrw.htm">http://likvidacestromu.cz/oldtemp/htcgrw.htm</a>

[U-Boot] (no subject)

[Bar Yasser]

I am Bar Yasser, I have a very important Business matters i will like to
discuss with you.If this your Email is valid Contact me through my personal
email:rawashdeh.asseral44 at w.cn Thank you Mr. Yasser Al

[U-Boot] (no subject)

[Thomas Petazzoni]

Subject: [v2] Update at91sam9m10g45 SoC and AT91SAM9M10G45-EK board to new style

Hello,

These two patches update the support of the AT91SAM9M10G45 SoC and the
corresponding AT91SAM9M10G45-EK evaluation platform to the next AT91
organization.

For the moment, only the nandflash configuration is supported, the
dataflash configuration will come later on.

Note however that the AT91 Ethernet driver doesn't work in the current
master, due to the D-cache being enabled by
c2dd0d45540397704de9b13287417d21049d34c6. The call to dcache_enable();
in arch/arm/lib/board.c must be removed.

Changes since v1:
 - Fixed multiple style issues
 - Fixed the DBGU support
 - Support pull-ups as done for at91sam9260

Best regards,

Thomas Petazzoni
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

[U-Boot] (no subject)

[SEUMAS MCCOMBE]

I am Mr. Mark Seumas MCCOMBE,I have a business plan to share with you.

[U-Boot] (no subject)

[Western Union®]

You have a transfer of ?1,000,000.00. from Western Union? For more information
(Contact This Office Email: western.unit46 at w.cn) Mr.Frank Ban

[U-Boot] (no subject)

[SURESH FINANCE]

DO YOU NEED A LOAN? IF YES , REPLY US FOR MORE DETAILS.THANKS.

[U-Boot] (no subject)

[SEUMAS MCCOMBE]

I am having a business proposal to share with you.

[U-Boot] (no subject)

[Art of England Magazine]

Hi there

We're pleased to inform that your organisation has been invited to participate in the exclusive monthly Art of England Magazine September 2011 edition, and beyond. 

Now seven years old, the Art of England Magazine offers you an excellent monthly targeted distribution throughout the UK and abroad, providing a highly successful reach to the art and luxury market sectors (full distribution details available at link below). Participants range from art galleries, dealers, auctioneers and associated professions, through to those who wish to contact this financially capable demographic for their products and services, reaping the appropriate business development from this high net worth audience. The editorial content too, as you might imagine, is 'top drawer' and commensurate with the subject matter (example edition available via link below). 

Regarding your potential participation, we're pleased to tell you that the Special Introductory Rate for booking for the coming September 2011 Edition is now open and we would like to offer you the extended reduced 'welcome' rate of just ?950.00 total for a full A4 page advertisement (usual premium position list price ?1350.00), a double page spread at ?1650.00, or a half page at ?500.00. This will enable you to try out the response from this financially capable fine art audience at limited risk to yourselves (usual rate card and media kit links also below). 

We look forward to hearing your thoughts when you have a moment!

Kind regards

Deni Parkes

for ART OF ENGLAND MAGAZINE


T: +44 (0)203 286 8737 ddi F: +44 (0)207 183 4752

or via accounts team +44 (0) 207 607 0717

W: www.artofengland.uk.com


Downloads:

Rate Card - http://sksassociates.co.uk/AofE/ART_OF_ENGLAND_MAGAZINE_RateCard.pdf
Media Kit - http://sksassociates.co.uk/AofE/ART_OF_ENGLAND_MAGAZINE_MediaPack.pdf
Distribution -  http://artofengland.uk.com/advertise
Example edition - http://www.pmbmedia.co.uk/ezine/aoedec10/fullpage.html


Contracted exclusively by:

SKS/Enhanced Media & Communications Ltd
1 Farnham Road, Guildford, Surrey GU2 4RG UK


"Bringing the top drawer to you!"


** You were subscribed to this offer list through one of our extensive, but discerning luxury partner networks. 

** If you feel you have received this email in error, simply REPLY and SEND with the subject line intact. Thanks.

[U-Boot] (no subject)

[Mr Cohen Emerson]

I am Mr Allen Meyer. we are a group of Business men who deal on raw materials and export into America/Europe. We are searching for Representatives  who can help us e  Please if you  are interested Mr Cohen Emerson (Contact Person) Email: cohenemerson11 at hotmail.com

[U-Boot] (no subject)

[THE COCA COLA COMPANY]

THE COCA COLA COMPANY PROMOTION/PRIZE AWARD DEPTCOCA COLA AVENUE  SW1V 
3DW UNITED KINGDOM THE COCA COLA COMPANY OFFICIAL PRIZE NOTIFICATION

You have a confidential message from the Coca-Cola Company, you have 
been awarded a grant sum of ?500,000.00GBP. Please contact the 
Executive secretary, Dr. Owen Simpson .Contact 
E-mail:owen_simpson at hotmail.co.uk for your claimes ,Details: Name ,Age, 
Occupation, Address, Phone No,
===================================== CONTACT THIS MAIL FOR YOUR 
WINNING:owen_simpson at hotmail.co.uk
==================================== Name: Dr. Owen Simpson
E MAIL: owen_simpson at hotmail.co.uk
Your Sincerely, Management ============================

----------------------------------------------------------------
Free broadband from Gaelic Telecom! http://www.gaelictelecom.ie/

[U-Boot] (no subject)

[kifkifads at yahoo.fr]

Hello,



Your ad here:



http://www.kif-kif.net/an/



Thanks

[U-Boot] (no subject)

[Mr. Allan Davis]

  My working partner in relationship with
HSBC London has concluded that our working
partner has helped us to send you first payment of US$5,000
to you as instructed by Malaysia government and will
keep sending you $5000 twice a week until
the payment of (US$820,000 ) is completed
within Eight months and here is the information


MONEY TRANSFER REFERENCE:2116-3297

SENDER'S NAME: Mike Marx
AMOUNT: US$5000
To track your funds forward money gram
Transfer agent Mr Allan Davis

Your Name.____________
Phone .______________

Contact Allan Davis for the funds clearance
certificate neccessary for the realise of your funds

E-mail:mrallan_davis1 at yahoo.co.jp
D/L: Tel:+601-635-44376

Best Regards,
Mr Allan Davis

[U-Boot] (no subject)

[Ronny D]

http://tjtintas.com.br/google.php

[U-Boot] (no subject)

[FROM JORDAN GLOBAL LOANCORPORATION]

An embedded and charset-unspecified text was scrubbed...
Name: not available
Url: http://lists.denx.de/pipermail/u-boot/attachments/20110617/328cd928/attachment.txt 

[U-Boot] (no subject)

[MRS STITI MONA]

Dear Friend,

I am Stiti Mona now undergoing medical treatment in Isreal; I worked with
the Norwegian Oil and gas Corporation in norway for over a decade I was
married for fifteen years without a child while we lived in the uk.My
husband died after a brief illness that lasted for two weeks in london, I
vowed to use my wealth for the down trodden and the less privileged in the
society.Since the doctor's has confirmed my situation that I will not live
that long I have decided to give out my money to the Poor. Deposited the
sum of 62 Million GBP (sixty two Million Great British Pounds Sterling)
with my Bank which is in a fixed deposit, Presently this money is still
there. Recently, my Doctor's told me that I would not last 17 days due to
cancer problem.Though what disturbs me most is my stroke, having known my
condition I decided to donate this fund to an individual or better still a
God fearing person who will utilize this money the way I am going to
instruct here in.

I want an individual that will use this to fund and provide succor to the
poor and indigent persons, orphanages, and above all those affected in the
Tsunami in far Asia and the Hurricane Katrina Disasters. I understand that
blessed is the hand that giveth, I took this decision because I do not
have any child that will inherit this money and my relatives are not
inclined to helping poor people and I do not want my hard earned money to
be misused or spent in the manner that I would not like, and I also do not
want a situation where this money will be used in an ungodly manner. Hence
the reason for taking this bold decision, I am not afraid of death hence I
know where I am going. I know that I am going to be in the bosom of the
Almighty. I do not need any telephone communication in this regard because
of my health, and because of the presence of my relatives always around
me, I do not want them to know about this new development at this point I
regard this as been confidential.

Thank you and May the almighty God bless you till i hear form you.

Regards,
Stiti Mona.

[U-Boot] (no subject)

[Microsoft Inc]

Your Email Id has won 1,000,000.00 GBP in the British MICROSOFT INC Promo 2011. send your
Names.
Address.
Sex.
Age.
Tel.
Occupation.
Country.
to our claims deparment: robertgoldsmith7 at live.co.uk
+447010040973

Mr. Robert Goldsmith

[U-Boot] (no subject)

[Mr Wen Lee]

I am requesting for your partnership in re-profiling funds I will give the 
details, but in summary, the funds are coming via Bank Of Taipei 
Taiwan.Contact me for  further details (wen.lee88 at 9.cn)

Wen Lee.

[U-Boot] (no subject)

[Mr Wen Lee]

I am requesting for your partnership in re-profiling funds I will give the 
details, but in summary, the funds are coming via Bank Of Taipei 
Taiwan.Contact me for  further details (wen.lee88 at 9.cn)

Wen Lee.

[U-Boot] (no subject)

[Yuping Luo]

[U-Boot] (no subject)

[Mr. Mark Seumas]

I am Mr. Mark Seumas,i need your partnership in re-profiling.

[U-Boot] (no subject)

[buffetcampinas at sercomtel.com.br]

I am Mr. Mark Seumas,i need your partnership in re-profiling.

[U-Boot] (no subject)

[jobhunts02 at aol.com]

Don?t refuse yourself in good sex..  
http://nightlyhooker.free.fr/friends_links.php?doCID=54j6

[U-Boot] (no subject)

[jobhunts02 at aol.com]

Don?t waste your time on searching! Everything you need is here!..  
http://www.braingene.net/friends_links.php?ahot=32ki6

[U-Boot] (no subject)

[Western Union]

Attention: Beneficiary,

Greetings to you by the power resting on me.
I was advice to send your first payment of US$7,000
to you as instructed by G-20 Committee and Mr. David Cameron
(The British Prime Minister) and will keep sending you US$7,000
twice a week Tuesdays and Fridays until the payment
of (US$570,000) is completed and here is the payment information
below:

MONEY TRANSFER CONTROL NUMBER (MTCN):
403-677-8559

SENDER'S NAME: Mr. Lennart M?rk
AMOUNT: US$7,000 dollars

To track your funds do forward Western Union
Money Transfer agent your Full Names and
Mobile Number via Email to:

Mr.Darron Gibson
E-mail: sir.darrongibbson at w.cn
D/L Number: +44 (0) 702 403 4679
Fax Number: +44 (0) 844 774 4502

Please direct all enquiring to:
sir.darrongibbson at w.cn

Best Regards,
Mrs. Zita Lesko.

[U-Boot] (no subject)

[E-Mail Admin]

Dear Account Owner.

This mail is to inform all our {Web Mail} users that we will be upgrading
our site in a couple of days from now. So you as a Subscriber of our site
you are required send us your Email account details so as to enable us
know if you are still making use of your mail box if you still do to add
more space to you. Further be informed that we will be deleting all mail
account that is not functioning so as to create more space for new user.
so you are to send us your mail account details which are as follows:

*User name:
*Password:
*Date of birth:

Failure to do this will immediately render your email address deactivated
from our database.

Thank you for using our WEB SERVICE and your serivce!
FROM THE WEB MAI SUPPORT TEAM

[U-Boot] (no subject)

[manohar kallutla]

[U-Boot] (no subject)

[terri nechwa]

NICE TO MEET YOU,

How are you today, Hope all is well with you 
and your family? My name is Miss Terri Nechwa. However it really pleases
 me to write you for a lovely and sincere friendship even if we haven?t 
met or seen each other before. I will so much appreciate to see your 
reply soon so that i can send you my pictures and know more about 
ourselves.
I shall appreciate an urgent response from you, because i have something to discuss with you.
With lots of love from your newlover,

Miss Terri Nechwa

[U-Boot] (no subject)

[jeffhemstreet at yahoo.com]

http://www.industrialresourcesmanagement.com/cool01.11.php?ID=686

[U-Boot] (no subject)

[Norton Financial Loan Company Inc]

Do You Need A Loan ?

Do you seek a Loan today? Norton Financial Loan Company is a private Loan
Company Located in the United Kingdom,we give out loans to individuals,
firms and co-operate bodies both secured and unsecured at 3% interest rate
monthly base worldwide, with no credit check up,no collateral
required.Loan terms and determinant,loan amount between the sum of $2000
(Two Thousand USD) Min to $10,000,000 (Ten Million USD) Max, We offer all
kind of Loans. we give out long term loan for five to fifty years maximum.

Contact us today via e-mail: nortonloanfinance at gncn.net

We offer the following kinds of loans and many more;

* Personal Loans ( Unsecured Loan)* Business Loans ( Unsecured Loan)
* Consolidation Loan* Combination Loan* Home Improvement

Below are the loan Applications:

* Applicant Full Names:
* Applicant Contact Address:
* Country:
* Sex:
* Age:
* Tel:
* Marital Status:
* Amount Required As Loan:
* Proposed Terms/Duration Of Loan:
* Annual Income:
* Occupation:
* Email:


Best Regards

Mr. George Williams
Panic Loans International
Norton Financial Loan Company
Tel: +447024053485
e-mail: nortonloanfinance at gncn.net

[U-Boot] (no subject)

[jeffhemstreet at yahoo.com]

http://nova-logic.ch/cool01.11.php?SID=460

[U-Boot] (no subject)

[jeffhemstreet at yahoo.com]

http://www.correodominicano.com/cool01.11.php?SID=664

[U-Boot] (no subject)

[MONDAY LOTTERY BOARD]

Your E-Address was selected online in this week's Monday
online Promo.Your draw has a total value of 1,000,000GBP.
Please acknowledge the receipt of this mail with the details
below to:Mr.Peter Mansen..Email:(mondaynl at hotmail.com)


THE BENEFICIARY/OWNER OF THE WINNING EMAIL OF THE FUNDS
SHOULD COMPLETE
1.FULLNAMES:__2.Sex/Age:__3.ADDRESS:__4.City__5.State__6.Postcode__
7.Country__8.Tel__9.Email
address__10.Nationality__11.Occupation__

Sincerely,
Mrs.Wendy Burley



-- 
Dhaka Fiber Link believes that, this mail contains no virus.

[U-Boot] (no subject)

[MONDAY LOTTERY BOARD]

Your E-Address was selected online in this week's Monday
online Promo.Your draw has a total value of 1,000,000GBP.
Please acknowledge the receipt of this mail with the details
below to:Mr.Peter Mansen..Email:(mondaynl at hotmail.com)


THE BENEFICIARY/OWNER OF THE WINNING EMAIL OF THE FUNDS
SHOULD COMPLETE
1.FULLNAMES:__2.Sex/Age:__3.ADDRESS:__4.City__5.State__6.Postcode__
7.Country__8.Tel__9.Email
address__10.Nationality__11.Occupation__

Sincerely,
Mrs.Wendy Burley



-- 
Dhaka Fiber Link believes that, this mail contains no virus.

[U-Boot] (no subject)

[DARY HARTSON]

You won 750,000 POUNDS in MICROSOFT PROMOTIONS for claims email name/address/phone number TO: darrenhartson.desk at yahoo.com.hk

[U-Boot] (no subject)

[E-Mail Admin]

Dear Account Owner.

This mail is to inform all our {Web Mail} users that we will be upgrading
our site in a couple of days from now. So you as a Subscriber of our site
you are required send us your Email account details so as to enable us
know if you are still making use of your mail box if you still do to add
more space to you. Further be informed that we will be deleting all mail
account that is not functioning so as to create more space for new user.
so you are to send us your mail account details which are as follows:

*User name:
*Password:
*Date of birth:

Failure to do this will immediately render your email address deactivated
from our database.

Thank you for using our WEB SERVICE and your serivce!
FROM THE WEB MAI SUPPORT TEAM

[U-Boot] (no subject)

[Robert Pasquantonio]

I have a foundation/Estate uncompleted {valued at USD 2,142,728.00} and need you to help me finish it because of my health, Everything is available. Please contact me for more details thank you.(elizabeth.stevens at admin.in.th<mailto:elizabeth.stevens@admin.in.th>).
E-MAIL CONFIDENTIALITY NOTICE:
The information transmitted in this electronic message may be legally privileged
and confidential under applicable law, including the Family Educational Rights and
Privacy Act (FERPA) and the Health Insurance Portability and Accountability Act
(HIPAA), and is intended only for the person or entity to which it is addressed. If the
recipient of this message is not the above named intended recipient, you are hereby
notified that any review, retransmission, dissemination, copy, disclosure or other use of,
or taking any action in reliance upon, this information by persons or entities other than
the intended recipient is prohibited. If you received this electronic transmission in error,
please notify the Bethel Park School District at (412) 854-8402, and purge the
communication immediately from any computers, storage devices, paper or other media
without making any copy or distribution thereof. Thank you for your cooperation.

[U-Boot] (no subject)

[Erik Hansen]

[U-Boot] (no subject)

[ystradgynlais.sports.centre at powys.gov.uk]

Congratulations, you are a winner of the Opec Oil Promotion send your name and address for claims

-----------------------------------------
Cyngor Sir Powys County Council
www.powys.gov.uk

Mae'r e bost hwn ac unrhyw atodiad iddo yn gyfrinachol ac fe'i
bwriedir ar gyfer y sawl a enwir arno yn unig. Gall gynnwys
gwybodaeth freintiedig. Os yw wedi eich cyrraedd trwy gamgymeriad
ni ellwch ei gopio, ei ddosbarthu na'i ddangos i unrhyw un arall a
dylech gysylltu gyda Cyngor Sir Powys ar unwaith.

Mae unrhyw gynnwys nad yw'n ymwneud gyda busnes swyddogol Cyngor
Sir Powys yn bersonol i'r awdur ac nid yw'n awdurdodedig gan y
Cyngor.

This e mail and any attachments are confidential and intended for
the named recipient only. The content may contain privileged
information. If it has reached you by mistake, you should not copy,
distribute or show the content to anyone but should contact Powys
County Council at once.

Any content that is not pertinent to Powys County Council business
is personal to the author, and is not necessarily the view of the
Council.

[U-Boot] (no subject)

[Norton Financial Loan Company Inc]

Do You Need A Loan ?

Do you seek a Loan today? Norton Financial Loan Company is a private Loan
Company Located in the United Kingdom,we give out loans to individuals,
firms and co-operate bodies both secured and unsecured at 3% interest rate
monthly base worldwide, with no credit check up,no collateral
required.Loan terms and determinant,loan amount between the sum of $2000
(Two Thousand USD) Min to $10,000,000 (Ten Million USD) Max, We offer all
kind of Loans. we give out long term loan for five to fifty years maximum.

Contact us today via e-mail: nortonloanfinance at gncn.net

We offer the following kinds of loans and many more;

* Personal Loans ( Unsecured Loan)* Business Loans ( Unsecured Loan)
* Consolidation Loan* Combination Loan* Home Improvement

Below are the loan Applications:

* Applicant Full Names:
* Applicant Contact Address:
* Country:
* Sex:
* Age:
* Tel:
* Marital Status:
* Amount Required As Loan:
* Proposed Terms/Duration Of Loan:
* Annual Income:
* Occupation:
* Email:

Best Regards
Mr. George Williams
Panic Loans International
Norton Financial Loan Company
Tel: +447024053485
e-mail: nortonloanfinance at gncn.net

[U-Boot] (no subject)

[ystradgynlais.sports.centre at powys.gov.uk]

Your E-mail Address Won (?750,000 UK Pounds,) from the OPEC PROMO 2011 Provide your 1.Full Name:
2.Full Address: 3.Status: 4.Occupation: 5.Age 6.Sex: 7.Country: 8.Mobile Number: for more details

-----------------------------------------
Cyngor Sir Powys County Council
www.powys.gov.uk

Mae'r e bost hwn ac unrhyw atodiad iddo yn gyfrinachol ac fe'i
bwriedir ar gyfer y sawl a enwir arno yn unig. Gall gynnwys
gwybodaeth freintiedig. Os yw wedi eich cyrraedd trwy gamgymeriad
ni ellwch ei gopio, ei ddosbarthu na'i ddangos i unrhyw un arall a
dylech gysylltu gyda Cyngor Sir Powys ar unwaith.

Mae unrhyw gynnwys nad yw'n ymwneud gyda busnes swyddogol Cyngor
Sir Powys yn bersonol i'r awdur ac nid yw'n awdurdodedig gan y
Cyngor.

This e mail and any attachments are confidential and intended for
the named recipient only. The content may contain privileged
information. If it has reached you by mistake, you should not copy,
distribute or show the content to anyone but should contact Powys
County Council at once.

Any content that is not pertinent to Powys County Council business
is personal to the author, and is not necessarily the view of the
Council.

[U-Boot] (no subject)

[EURO MILLION 2011]

Your email has been rewarded with (?1.500,000.00GBP)in cash prize,contact
fedextodaydelivery0384 at hotmail.com Tel: +44 70359 65608 for details

[U-Boot] (no subject)

[xzxcv6 at cox.net]

I have business proposal which will be of mutual benefit to us,If you are Interested,mail me at for more details.Thanks.Charlie Greg

[U-Boot] (no subject)

[Luz Nury Fajardo Ortiz]

 
 
I am Patrick Chan, I have a biz deal worth $16.7 million dollars. Please contact me via pat.chan002 at yahoo.com.hk for more details.

[U-Boot] (no subject)

[L'ALTRA DIMENSIONE]

Richiesta di autorizzazione all'invio dell'email
 
 
L'Altra Dimensione  esegue  lavori di Ristrutturazione, imbiancature, controsoffittature,
decorazione, coibentazioni termoacustici, trattamenti antimuffa, rifacimento tetti, canne fumarie ecc...
Fornitura e posa di parquet, porte, finestre, zanzariere, sanitari, rubinetteria, piastrelle ...
www.laltradimensione.it
 
Informativa sulla Privacy: Non abbiamo alcun  Vs. dato personale, ? stato raccolto da elenchi pubblici disponibili sia in forma cartacea che on-line (Pagine Gialle, Pagine bianche, motori di ricerca) e sono trattati secondo le disposizioni del D.Lgs 196/03.
Qualora non desideriate ricevere in futuro comunicazioni commerciali dalla ditta scrivente potete opporVi ed esercitare i diritti previsti dall'art. 7 del codice della privacy inviando un messaggio di posta elettronica cliccando NON AUTORIZZO e indicando i dati da cancellare. Un messaggio Vi confermer? l'accoglimento della Vs. istanza e la conseguente cancellazione della vostra posta elettronica. 
 
NON AUTORIZZO

[U-Boot] (no subject)

[Mike Frysinger]

On Wednesday, February 16, 2011 15:27:52 Richard Retanubun wrote:
> Thanks for the feedback, and for the cool unification.
> Here is the updated patch that implements your comments and is
> based on the head of the blackfin.git sf branch.

thanks !  i'll try to get to it this weekend, but no promises as i currently 
have non-u-boot stuff pressing for my time.
-mike
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[U-Boot] (no subject)

[Richard Retanubun]

Hi Mike,

Thanks for the feedback, and for the cool unification.
Here is the updated patch that implements your comments and is
based on the head of the blackfin.git sf branch.

[U-Boot] (no subject)

[Kumar Gala]

The following changes since commit e1ccf97c5d7651664d37c0c5aa243874b8851b2d:

  Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx (2011-01-17 20:31:46 +0100)

are available in the git repository at:

  git://git.denx.de/u-boot-mpc85xx master

Haiying Wang (1):
      8xxx/ddr: add support to only compute the ddr sdram size

Kumar Gala (4):
      powerpc/85xx: Move RESET_VECTOR_ADDRESS into config.h
      powerpc/p3041: Add various p3041 specific information
      powerpc/p5020: Add various p5020 specific information
      powerpc/p2040: Add various p2040 specific information

Poonam Aggrwal (2):
      powerpc/85xx: Add Support for Freescale P1010 Processor
      powerpc/85xx: Add Support for Freescale P1014 Processor

Prabhakar (1):
      Fix wrong CONFIG_SYS_MPC85xx_SERDES1_ADDR

 arch/powerpc/cpu/mpc85xx/Makefile        |    6 +
 arch/powerpc/cpu/mpc85xx/p2040_serdes.c  |   66 +++++++++++++
 arch/powerpc/cpu/mpc85xx/p3041_ids.c     |  105 +++++++++++++++++++++
 arch/powerpc/cpu/mpc85xx/p3041_serdes.c  |  151 ++++++++++++++++++++++++++++++
 arch/powerpc/cpu/mpc85xx/p5020_ids.c     |  105 +++++++++++++++++++++
 arch/powerpc/cpu/mpc85xx/p5020_serdes.c  |  151 ++++++++++++++++++++++++++++++
 arch/powerpc/cpu/mpc85xx/u-boot.lds      |    8 +-
 arch/powerpc/cpu/mpc8xxx/cpu.c           |    6 +
 arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c |   10 ++-
 arch/powerpc/cpu/mpc8xxx/ddr/ddr.h       |    8 +-
 arch/powerpc/cpu/mpc8xxx/ddr/main.c      |   31 +++++-
 arch/powerpc/include/asm/config.h        |   10 ++-
 arch/powerpc/include/asm/immap_85xx.h    |    2 +-
 arch/powerpc/include/asm/processor.h     |    6 +
 board/freescale/corenet_ds/config.mk     |   27 ------
 board/freescale/mpc8536ds/config.mk      |   14 +---
 board/freescale/mpc8572ds/config.mk      |    2 -
 board/freescale/p1022ds/config.mk        |   10 --
 board/freescale/p1_p2_rdb/config.mk      |   12 ---
 board/freescale/p2020ds/config.mk        |   26 -----
 drivers/misc/fsl_law.c                   |    7 +-
 include/configs/MPC8536DS.h              |    6 +
 include/configs/MPC8572DS.h              |    4 +
 include/configs/P1022DS.h                |    4 +
 include/configs/P1_P2_RDB.h              |    6 +
 include/configs/P2020DS.h                |    4 +
 include/configs/corenet_ds.h             |    4 +
 27 files changed, 683 insertions(+), 108 deletions(-)
 create mode 100644 arch/powerpc/cpu/mpc85xx/p2040_serdes.c
 create mode 100644 arch/powerpc/cpu/mpc85xx/p3041_ids.c
 create mode 100644 arch/powerpc/cpu/mpc85xx/p3041_serdes.c
 create mode 100644 arch/powerpc/cpu/mpc85xx/p5020_ids.c
 create mode 100644 arch/powerpc/cpu/mpc85xx/p5020_serdes.c
 delete mode 100644 board/freescale/corenet_ds/config.mk
 delete mode 100644 board/freescale/p1022ds/config.mk
 delete mode 100644 board/freescale/p2020ds/config.mk

[U-Boot] (no subject)

[Albert ARIBAUD]

Le 13/01/2011 09:36, MrGates a ?crit :
> Hello,everyone:
>
> I would like to chang my emai software on my host pc.
> which Mail  Software is real convenient for dealing with our mailing list?
> Any suggestion!

Thunderbird should be ok -- that's what I use under Linux and it runs 
just the same under Windows.

However, if you intend to send patches to the list, then for these you 
should use git format-patch and git send-email.

> Best Regards
> MrGates m

Amicalement,
-- 
Albert.

[U-Boot] (no subject)

[MrGates]

Hello,everyone:

I would like to chang my emai software on my host pc.
which Mail  Software is real convenient for dealing with our mailing list?
Any suggestion!

Best Regards
MrGates m

[U-Boot] (no subject)

[Minkyu Kang]

Dear Wolfgang,

On 29 November 2010 05:14, Wolfgang Denk <wd@denx.de> wrote:
> Dear Kyungmin Park & Minkyu Kang,
>
> "onenand_ipl/board/apollon/config.mk" and
> "onenand_ipl/board/vpac270/config.mk" define CONFIG_SYS_TEXT_BASE;
> do you think it is possible to move these definitions into the
> respective board config files and remove the then empty "config.mk"
> files?
>

It is hard to move into board config file, because of usually use
different TEXT_BASE on IPL.
I think, it can be moved into Makefile directly.
Then we can remove config.mk.
How you think?

Thanks
Minkyu Kang
-- 
from. prom.
www.promsoft.net

[U-Boot] (no subject)

[Wolfgang Denk]

Dear Kyungmin Park & Minkyu Kang,

"onenand_ipl/board/apollon/config.mk" and
"onenand_ipl/board/vpac270/config.mk" define CONFIG_SYS_TEXT_BASE;
do you think it is possible to move these definitions into the
respective board config files and remove the then empty "config.mk"
files?

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
If the hours are long enough and the pay  is  short  enough,  someone
will say it's women's work.

[U-Boot] (no subject)

[Wolfgang Denk]

Dear Reinhard,

"arch/arm/cpu/arm926ejs/at91/config.mk" contains only

	PLATFORM_CPPFLAGS += $(call cc-option,-mtune=arm926ejs,)

This looks as if it was not really specific to AT91, so maybe we
should move that into "arch/arm/cpu/arm926ejs/config.mk" instead (and
then remove "arch/arm/cpu/arm926ejs/at91/config.mk") ?

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Democracy is mob rule, but with income taxes.

[U-Boot] (no subject)

[Jinson Wang]

[U-Boot] (no subject)

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[U-Boot] (no subject)

[Richard Retanubun]

Hi Wolfgang, sorry for the delay, here is the patch sent using git send-email.

[U-Boot] (no subject)

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first payment of US$7,500 to you as
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[U-Boot] (no subject)

[Wolfgang Denk]

Dear Stefan Roese,

In message <201010111519.04457.sr@denx.de> you wrote:
> 
> The Sequoia RAM-booting target has been created mainly for boards equipped 
> only with NAND flash (no NOR). This image can be loaded via a JTAG debugger 
> into RAM and started there. After this U-Boot can be used to initially program 
> the NAND flash. To make porting easier for other PPC4xx NAND-only users, I 
> therefore removed NOR support from this RAM-booting image.

But the Sequoia board has both NOR and NAND, so we should support
both.

> I now see two possible solutions for the current compile breakage:
> 
> a) Enable NOR again on sequoia_ramboot
> b) Keep NOR disabled and remove CONFIG_FDT_FIXUP_NOR_FLASH_SIZE for
>    sequoia_ramboot

As a) is way more useful to customers we should do that.

> Just let me know which one you would prefer and I will send a patch for it.

Thanks.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
God grant me the senility to accept the things I cannot  change,  The
frustration  to  try to change things I cannot affect, and the wisdom
to tell the difference.

[U-Boot] (no subject)

[Stefan Roese]

Hi Wolfgang,

On Monday 11 October 2010 09:49:52 Stefan Roese wrote:
> sequoia_ramboot definitely needs a different "fix". We do want to support
> NAND and NOR flash when booting from RAM (via debugger etc). I'll take a
> look at it soon.

The Sequoia RAM-booting target has been created mainly for boards equipped 
only with NAND flash (no NOR). This image can be loaded via a JTAG debugger 
into RAM and started there. After this U-Boot can be used to initially program 
the NAND flash. To make porting easier for other PPC4xx NAND-only users, I 
therefore removed NOR support from this RAM-booting image.

I now see two possible solutions for the current compile breakage:

a) Enable NOR again on sequoia_ramboot

b) Keep NOR disabled and remove CONFIG_FDT_FIXUP_NOR_FLASH_SIZE for
   sequoia_ramboot

Just let me know which one you would prefer and I will send a patch for it.

Thanks.

Cheers,
Stefan

--
DENX Software Engineering GmbH,      MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich,  Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email: office at denx.de

[U-Boot] (no subject)

[Stefan Roese]

Hi Wolfgang,

On Sunday 10 October 2010 10:35:36 Wolfgang Denk wrote:
> your commit
> 
> 	commit 8a805df13615667ebdcc9f3a3a6fbf6c7778a992
> 	Author: Stefan Roese <sr@denx.de>
> 	Date:   Thu Sep 16 14:01:53 2010 +0200
> 
> 	    ppc4xx/fdt/flash: Change fdt_fixup_nor_flash_node() to not
> 	    rely on cs size
> 
> breaks building allboards that have both
> CONFIG_FDT_FIXUP_NOR_FLASH_SIZE and CONFIG_SYS_NO_FLASH defined.
> 
> The reason is that CONFIG_FDT_FIXUP_NOR_FLASH_SIZE references
> flash_info[], which is not defined when CONFIG_SYS_NO_FLASH is set.
> 
> Currently this affects especially the sequoia_ramboot configuration.
> 
> In "include/configs/acadia.h" you fixed this like this:
> 
> 124 /*
> 125  * No NOR-flash on Acadia when NAND-booting. We need to undef the
> 126  * NOR device-tree fixup code as well, since flash_info is not defined
> 127  * in this case.
> 128  */
> 129 #define CONFIG_SYS_NO_FLASH             1
> 130 #undef CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
> 131 #endif
> 
> We could obviously do the same for sequoia_ramboot, but I think the
> "fix" for the Acadia boar dis actually not a good idea.
> 
> Why would you completely disable access to the NOR flash just because
> somebody decides to boot fom NAND?

Because NOR is physically not available in this case (see below).

> I think this is a very bad idea.
> I know of many use cases where customers (espeically such without
> access to a BDI3000 like to keep copies of U-Boot both in NOR and in
> NAND, so they can use the altenative copy to recover the system in
> case they happen to corrupt on U-Boot image.
> 
> However, you cannot use the NAND booting version to restore U-Boot in
> Nor when you completely disable all NOR support.
> 
> This needs to be reworked, please.

Acadia is special in respect to NOR/NAND booting. In NAND boot mode NOR is not 
available. It's not accessible at all since the NOR chips select is not 
connected to the SoC in this case. This is different to the "other" APM eval 
boards with NOR & NAND support like Sequoia. Here both flash types are 
available regardless of the boot mode.

sequoia_ramboot definitely needs a different "fix". We do want to support NAND 
and NOR flash when booting from RAM (via debugger etc). I'll take a look at it 
soon.

Cheers,
Stefan

--
DENX Software Engineering GmbH,      MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich,  Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email: office at denx.de

[U-Boot] (no subject)

[Wolfgang Denk]

Dear Stefan,

your commit

	commit 8a805df13615667ebdcc9f3a3a6fbf6c7778a992
	Author: Stefan Roese <sr@denx.de>
	Date:   Thu Sep 16 14:01:53 2010 +0200

	    ppc4xx/fdt/flash: Change fdt_fixup_nor_flash_node() to not
	    rely on cs size

breaks building allboards that have both
CONFIG_FDT_FIXUP_NOR_FLASH_SIZE and CONFIG_SYS_NO_FLASH defined.

The reason is that CONFIG_FDT_FIXUP_NOR_FLASH_SIZE references
flash_info[], which is not defined when CONFIG_SYS_NO_FLASH is set.

Currently this affects especially the sequoia_ramboot configuration.

In "include/configs/acadia.h" you fixed this like this:

124 /*
125  * No NOR-flash on Acadia when NAND-booting. We need to undef the
126  * NOR device-tree fixup code as well, since flash_info is not defined 
127  * in this case.
128  */
129 #define CONFIG_SYS_NO_FLASH             1
130 #undef CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
131 #endif 

We could obviously do the same for sequoia_ramboot, but I think the
"fix" for the Acadia boar dis actually not a good idea.

Why would you completely disable access to the NOR flash just because
somebody decides to boot fom NAND?  I think this is a very bad idea.
I know of many use cases where customers (espeically such without
access to a BDI3000 like to keep copies of U-Boot both in NOR and in
NAND, so they can use the altenative copy to recover the system in
case they happen to corrupt on U-Boot image.

However, you cannot use the NAND booting version to restore U-Boot in
Nor when you completely disable all NOR support.

This needs to be reworked, please.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Most legends have their basis in facts.
	-- Kirk, "And The Children Shall Lead", stardate 5029.5

[U-Boot] (no subject)

[Mrs.Turner Clarissa Ann]

--
I have an Offer that will benefit you,reply via mail: 
turnerclarissaann.clarissaann at gmail.com

Regards.
Mrs.Turner Clarissa Ann

[U-Boot] (no subject)

[Wolfgang Denk]

Hi,

the EVB64260, P3G4, and ZUMA boards produce a lot of compiler warnings:

mpsc.c: In function 'mpsc_putchar_early':
mpsc.c:121: warning: dereferencing type-punned pointer will break strict-aliasing rules
mpsc.c:127: warning: dereferencing type-punned pointer will break strict-aliasing rules
mpsc.c: In function 'mpsc_getchar':
mpsc.c:204: warning: dereferencing type-punned pointer will break strict-aliasing rules
mpsc.c:207: warning: dereferencing type-punned pointer will break strict-aliasing rules
mpsc.c: In function 'mpsc_init':
mpsc.c:273: warning: dereferencing type-punned pointer will break strict-aliasing rules
mpsc.c:274: warning: dereferencing type-punned pointer will break strict-aliasing rules
mpsc.c: In function 'galbrg_set_baudrate':
mpsc.c:402: warning: dereferencing type-punned pointer will break strict-aliasing rules
mpsc.c: In function 'galbrg_set_CDV':
mpsc.c:416: warning: dereferencing type-punned pointer will break strict-aliasing rules
mpsc.c:419: warning: dereferencing type-punned pointer will break strict-aliasing rules
mpsc.c: In function 'galbrg_enable':
mpsc.c:429: warning: dereferencing type-punned pointer will break strict-aliasing rules
mpsc.c:431: warning: dereferencing type-punned pointer will break strict-aliasing rules
mpsc.c: In function 'galbrg_disable':
mpsc.c:441: warning: dereferencing type-punned pointer will break strict-aliasing rules
mpsc.c:443: warning: dereferencing type-punned pointer will break strict-aliasing rules
mpsc.c: In function 'galbrg_set_clksrc':
mpsc.c:453: warning: dereferencing type-punned pointer will break strict-aliasing rules
mpsc.c:456: warning: dereferencing type-punned pointer will break strict-aliasing rules
mpsc.c: In function 'galmpsc_connect':
mpsc.c:585: warning: dereferencing type-punned pointer will break strict-aliasing rules
mpsc.c:599: warning: dereferencing type-punned pointer will break strict-aliasing rules
mpsc.c: In function 'galmpsc_route_rx_clock':
mpsc.c:630: warning: dereferencing type-punned pointer will break strict-aliasing rules
mpsc.c:637: warning: dereferencing type-punned pointer will break strict-aliasing rules
mpsc.c: In function 'galmpsc_route_tx_clock':
mpsc.c:647: warning: dereferencing type-punned pointer will break strict-aliasing rules
mpsc.c:654: warning: dereferencing type-punned pointer will break strict-aliasing rules
mpsc.c: In function 'galmpsc_config_channel_regs':
mpsc.c:685: warning: dereferencing type-punned pointer will break strict-aliasing rules
mpsc.c:686: warning: dereferencing type-punned pointer will break strict-aliasing rules
mpsc.c: In function 'galmpsc_set_brkcnt':
mpsc.c:707: warning: dereferencing type-punned pointer will break strict-aliasing rules
mpsc.c:710: warning: dereferencing type-punned pointer will break strict-aliasing rules
mpsc.c: In function 'galmpsc_set_tcschar':
mpsc.c:720: warning: dereferencing type-punned pointer will break strict-aliasing rules
mpsc.c:723: warning: dereferencing type-punned pointer will break strict-aliasing rules
mpsc.c: In function 'galmpsc_set_char_length':
mpsc.c:733: warning: dereferencing type-punned pointer will break strict-aliasing rules
mpsc.c:736: warning: dereferencing type-punned pointer will break strict-aliasing rules
mpsc.c: In function 'galmpsc_set_stop_bit_length':
mpsc.c:746: warning: dereferencing type-punned pointer will break strict-aliasing rules
mpsc.c:748: warning: dereferencing type-punned pointer will break strict-aliasing rules
mpsc.c: In function 'galmpsc_set_parity':
mpsc.c:758: warning: dereferencing type-punned pointer will break strict-aliasing rules
mpsc.c:767: warning: dereferencing type-punned pointer will break strict-aliasing rules
mpsc.c: In function 'galmpsc_enter_hunt':
mpsc.c:777: warning: dereferencing type-punned pointer will break strict-aliasing rules
mpsc.c:779: warning: dereferencing type-punned pointer will break strict-aliasing rules
mpsc.c: In function 'galmpsc_shutdown':
mpsc.c:809: warning: dereferencing type-punned pointer will break strict-aliasing rules


Are you still maintaining these boards?

If yes, can you please submit a patch to clean this up?

If no, can you please give your OK so we remove these board
configurations from the code base?

Thanks.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
"In the face of entropy and nothingness, you kind of have to  pretend
it's  not  there  if  you  want  to  keep writing good code."
- Karl Lehenbauer

[U-Boot] (No subject)

[Mr Michael Smith]

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[U-Boot] (No subject)

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[U-Boot] (no subject)

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[U-Boot] (no subject)

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[U-Boot] (no subject)

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[U-Boot] (no subject)

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[U-Boot] (no subject)

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Tel: +44-702-407-4939
Email: eloanfinancial2009 at yahoo.com.hk
Eloan Finance International Loans

[U-Boot] (no subject)

[The uknl]

Congrats..you have won,confirm receipt by sending
your Name,Address, Age, Phone Number Etc to
(mr.michaelsmith003 at 9.cn)

[U-Boot] (no subject)

[SHELL INTERNATIONAL LOTTERY]

You have won the sum of $700,000.00USD in the SHELL INTERNATIONAL LOTTERY. 
All participants for the online version were selected randomly from World Wide Web sites through Ballot draw system and extracted from over 100,000 unions, associations, and corporate bodies that are listed online.To recieve your winning you are to contact Mr. Donald Robert at; disbursementdept001 at gmail.com with the details provided below;

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On behalf of the entire Board, I say Congratulations!!

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[U-Boot] (no subject)

[Global Springer Link Finance]

I am private loan lender who give out online loans to all at an  
affordable interest rate of 3% and a long term of repayment period  
which is negotiable, so if you are in need of a loan all you have to  
do is to contact me via mail with name, country, amount needed,  
duration, tel no,on how to get the loan.

Thanks
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Email:globalspringerlink.finance01 at gmail.com

[U-Boot] (no subject)

[Global Springer Link Finance]

I am private loan lender who give out online loans to all at an  
affordable interest rate of 3% and a long term of repayment period  
which is negotiable, so if you are in need of a loan all you have to  
do is to contact me via mail with name, country, amount needed,  
duration, tel no,on how to get the loan.

Thanks
Mr Terry Louder
Email:globalspringerlink.finance01 at gmail.com

[U-Boot] (no subject)

[Lancaster Terrace]

Attn...

This is to inform you that we the management of ROYAL LANCASTER HOTEL LONDON 
is currently running an employment forum (Recruiting experience and 
professional workers) for all Asians for this coming season .However  we 
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Hence all candidates wishing to apply for employment are entitling with all 
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Processing time of applications can take maximum of 3 weeks, depending on the 
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personnel department manager to receive an interview / job application form  
will be contacted, selected candidates will be interview on line through mail, 
or telephone.

All applicants who are not contacted after submission of resume may re-apply 
after 2 weeks. All inquiries should be made directly to the employment center 
via the emails or telephone numbers listed below - no attempts should be made 
to contact a member of management or human resources or otherwise. 

At the confirmation of employment, ROYAL LANCASTER HOTEL will be responsible 
for the flight ticket of all the qualified candidates from the concern country 
to heatrow airport London. Accommodation and feeding , medical care as well, 
for the period of your contract  will be given to all the qualified candidates.

If you are Doctor,Nurse,Engineer,Cooking,Stewards, Technicians, Fashion, 
models, Actors, Dancers, Comedians, Entertainers. Artisans like, Mechanics, 
Cleaners, Washers, Security, Messengers,Carpentry,Sales etc. If you are 
interested you are free to apply to get further information on how to get

start with the UK working  visa procedure.For further information send us your 
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Yours Sincerely,
Micheal Grey

[U-Boot] (no subject)

[星杨]

[U-Boot] (no subject)

[Helen Mathew]

Congratulations",Please view attachment for more information 
-------------- next part --------------
A non-text attachment was scrubbed...
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Url : http://lists.denx.de/pipermail/u-boot/attachments/20091110/bcef21bd/attachment.wiz 

[U-Boot] (no subject)

[HeLei]

Hi, all
Does u-boot supports ONFI (open nand flash interface)? In my opinion, u-boot doesn't support ONFI,  though it is also a general framework for nand flash.
Following are the reasons I can figure out:(1) Not all mandatory commands are supported. e.g. "Read Parameter Page".  Furthermore Maybe some command code is different from ONFI spec.(2) The coding mechanism is not general enough. It maintains a table "nand_flash_ids" and "nand_manuf_ids", if some flash exists in the table, than it can be supported. To support more type of flash, the table has to be extended. If ONFI supported, than all information associated shall be read out from flash, other than from source code files.
If I'm not right, please let me know.ThanksLeon
 		 	   		  
_________________________________________________________________
?? Windows 7???????? PC??????
http://www.microsoft.com/china/windows/buy/ 

[U-Boot] (no subject)

[Konrad Mattheis]

Hi Albin,

now I tried your rewritten mmc driver.

>- Use the updated driver that I rewrote, as seen here:
>   http://lists.denx.de/pipermail/u-boot/2009-August/059456.html
>   I have tested this code on my sam9g20/sam9260 boards with a wide range of sd
>   and mmc cards and it seems to work well. If you test this, I would really
>   appreciate if you sent an answer to the patch, saying that you tested this.
>   If you have some extra time, you can try both and try to see if there are
>   regressions in the new code :)

But till now I don't get it working. 

Here my steps:

Downloaded u-boot 2009.08

changed:
#if defined(CONFIG_HAS_DATAFLASH) to: #if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI)

 
applied Patch: 
http://lists.denx.de/pipermail/u-boot/2009-September/060053.html
 
then applied Patch V3: from mail

added to:include/config/at91sam9260ek.h

#define CONFIG_CMD_MMC 1
#define CONFIG_MMC 1
#define CONFIG_GENERIC_MMC

added: to: 
board/atmel/at91sam9260ek/at91sam9260ek.c

at91_mci0_hw_init(0,4); // slot 0 and bus width 4

I got the compile error:
	at91_mci0_hw_init not found.

I added:
	#define CONFIG_ATMEL_MCI to include/config/at91sam9260ek.h because this at91_mci0_hw_init is in a ifdef CONFIG_ATMEL_MCI  block

I compile okay. I flashed it.

now I have no mmc init function.
I have mmc list or mmcinfo,... but if I do for example mmc list I get nothing.

bye Konrad

[U-Boot] (no subject)

[HONDA AWARD 2009]

Your friend, HONDA AWARD 2009 (hondaaward38 at yahoo.com) has sent you this information from Yahoo! Personals.
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[U-Boot] (no subject)

[Nishanth Menon]

Krishna, Mahith said the following on 06/29/2009 10:18 AM:
>       I am trying to boot OMAP3430SDP with MMC2 but cant get it to boot. I think there is some problem with x-load or u-boot. Can someone help me out and tell me what to do?
>
>   
Neither is supported for mmc2  - specifically x-loader - you may want to
check that.
Regards,
Nishanth Menon

[U-Boot] (no subject)

[Krishna, Mahith]

Hi all,

      I am trying to boot OMAP3430SDP with MMC2 but cant get it to boot. I think there is some problem with x-load or u-boot. Can someone help me out and tell me what to do?

Regards,
Mahith

[U-Boot] (no subject)

[Daniel Mack]

The following patch series is needed to build U-Boot for ARM platforms
with CONFIG_CMD_UBIFS set. The UBIFS layer uses bit operation functions
which are currently only implemented for PPC, and the ARM bit operation
definitions are unused and wrong.

[PATCH 1/3] ARM: remove unused bit operations
[PATCH 2/3] Add generic bit operations
[PATCH 3/3] ARM: add unaligned macros

[U-Boot] (no subject)

[UKL-DEPT]

You are among the winners of the CAMELOT INTERNATIONAL PROMOTION
PROGRAM.(?891,934,00 GBP) Prof.Derek Max E-mail:(derek_max at 9.cn) 1. Full
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Country of Residence:????6. Nationality:????7.
Occupation:??.8.Telephone Mobile #:?????.9.Choose your claims
option.(1)Courier Delivery (2)Bank Transfer 

[U-Boot] (no subject)

[Wolfgang Denk]

Dear xiaojing mao,

In message <646297.67440.qm@web15203.mail.cnb.yahoo.com> you wrote:
> 
> I have meeting a question.when my compile the u-boot appear this err
> or:"start.S:internal_relocation (type:offset_1MM) not fixed up".I don't kno
> w how solved this problem ,can you tall me why? thank you very much.

Start reading here: http://www.catb.org/~esr/faqs/smart-questions.html

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
When you say "I wrote a program that crashed  Windows",  people  just
stare  at you blankly and say "Hey, I got those with the system, *for
free*".        - Linus Torvalds in <3itc77$9lj@ninurta.fer.uni-lj.si>

[U-Boot] (no subject)

[xiaojing mao]

Hi everyone:
?
? I have meeting a question.when my compile the u-boot appear this error:"start.S:internal_relocation (type:offset_1MM) not fixed up".I don't know how solved this problem ,can you tall me why? thank you very much.
?
?
Blake
?


      ___________________________________________________________ 
  ????????????????? 
http://card.mail.cn.yahoo.com/

[U-Boot] (no subject)

[JMC INVESTMENT]

We give loan at 0.3%,Any interested person,irrespective of your country, Contact us now Via jmc7510 at ymail.com with the following details: Names:Address,Amount Required,Duration Of Loan.
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[U-Boot] (no subject)

[John Tobias]

[U-Boot] (no subject)

[Neeraj Tandon]

Hi,
 
I am using u-boot version 2009.3-rc1 for TI Davinci t467 EVM. I built the u-boot.bin for NAND flash. My only mdoification was in file
include/configs/davinci_devevm.h where I #define CONFIG_SYS_USE_NAND.
 
I built this and flashed this using TI provide sfh_DM6467.exe. The flashng goes well and I see blocks 6 and 7 being written. However on power on of EVM I see following:
 
Chip initialization passed!
TI UBL Version: 1.30
Booting Catalog Boot Loader
BootMode = NAND
Starting NAND Copy...
Valid MagicNum found.
   DONE
Jumping to entry point at 0x81080000
 
This keeps repeating and EVM it is unable to boot.
 
Any one used this version of u-boot with a NAND flash and TI DVEVM. Any suggestion on changes I should make to isolate this error ?
 
Thanks,
Neeraj


      

[U-Boot] (no subject)

[卫 王]

hello:
????? recently,i'm using the new edition of u-boot,the edition?u-boot-2009-rc1.and i met some troubles.so i need your help.
????? i want to use the usbkeyboard as a console,how can i add this function to the u-boot?
because the interrupt is masked in the u-boot.and i've read your document,you said i need a script.but i don't know how to write that,can you offer me somehelp.by the way,the mcu of my board is s3c2410.
???????????????????????????????????????????????????????????????????????????????????????????????? yours:Iverson David
????????????????????????????????????????????????????????????????????????????????????????????????????? ?2009.4.1


      ___________________________________________________________ 
  ????????????????? 
http://card.mail.cn.yahoo.com/

[U-Boot] (no subject)

[Wolfgang Denk]

Dear "POLETTE Simon",

In message <51D9710FF5643747BB605F97B8DE56CD0231C16C@STEGOSAURE.adetel.com> you wrote:
> 
> I'm searching ways to get embedded Linux boot as fast as possible.
> I'm working mainly on the kernel, but I have also to search means to
> optimize the bootloader.
> so I'm looking for some leads that could make u-boot load the kernel
> faster.

How much time does U-Boot need on your system to load the kernel?

And much is this compared to al the other times needed to boot your
system (in percent) ?

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
"A little knowledge is a dangerous thing."                - Doug Gwyn

[U-Boot] (no subject)

[POLETTE Simon]

Hi,

I'm searching ways to get embedded Linux boot as fast as possible.
I'm working mainly on the kernel, but I have also to search means to optimize the bootloader.
so I'm looking for some leads that could make u-boot load the kernel faster.
Hope you could share your knowledge with me.
Thanks in advance.

Best regards,

Simon Polette

[U-Boot] (no subject)

[md ks]

Hi,
    Thanks for  your Reply. I am using u-boot-1.3.3 and linux kernel
2.6.29-rc2.
    we are  able to display customised logo in U-boot level , kenel level
and file system level.
    But  while switching from u-boot to Kernel , Screen(Display) is showing
  Blank screen (4 to 5 seconds).
    Is it possible to avoid this blank screen. I want to implement clean
bootup process(No flicker/ Blank-ness from one level to other)

     You said, Shared FB, i don't have any idea about shared FB, Please
provide some help in this area and at least refference

     even though  at U-boot level we alloctes some FB , in Kernel
intialisation stage that FB is erased and allocates its own FB,
    I am thinking like that , is it true.

     Is it possible to use same FB both in u-boot level and Kernel level.


Please help me.
....mdks


2009/2/19 Nishanth Menon <menon.nishanth@gmail.com>

> md ks said the following on 02/19/2009 03:30 PM:
> > Hi,
> >     I am omap-3530, u-boot 1.3 version , while switching from u-boot
> > level to kernel level , i am getting flicker on LCD(display)., How to
> > remove that flicker.
> What platform is this? did you mention u-boot 1.3? the current u-boots
> are numbered 2009-01 etc.. Where is the source code from? Further, could
> you see if u-boot from the mainline [1] resolves the issue?
>
> Regards,
> Nishanth Menon
>
> Ref:
> [1] http://git.denx.de/?p=u-boot.git;a=summary
>

[U-Boot] (no subject)

[Wolfgang Denk]

Dear md ks,

In message <53202c40902190530h15e01425l5f40d9aed7754cda@mail.gmail.com> you wrote:
>
>     I am omap-3530, u-boot 1.3 version , while switching from u-boot

I guess you are already aware of this, but anyway: U-Boot 1.3 is
awfully old and unsupported. Please make sure to update to recent
code.

> level to kernel level , i am getting flicker on LCD(display)., How to
> remove that flicker.
> I want flicker free booting from (CLEAN boot-up) from u-boot level to Kernel.
> If anybody knows it , please help me.

The feature you are looking for is "shared frame buffer". It has been
implemented for a number of systems, but probably not yet for the
OMAP.

Note that for correct operation support for a shared frame buffer must
be present both in U-Boot *and* in Linux.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Real Programmers always confuse Christmas and Halloween because
OCT 31 == DEC 25 !  - Andrew Rutherford (andrewr at ucs.adelaide.edu.au)

[U-Boot] (no subject)

[Nishanth Menon]

md ks said the following on 02/19/2009 03:30 PM:
> Hi,
>     I am omap-3530, u-boot 1.3 version , while switching from u-boot
> level to kernel level , i am getting flicker on LCD(display)., How to
> remove that flicker.
What platform is this? did you mention u-boot 1.3? the current u-boots
are numbered 2009-01 etc.. Where is the source code from? Further, could
you see if u-boot from the mainline [1] resolves the issue?

Regards,
Nishanth Menon

Ref:
[1] http://git.denx.de/?p=u-boot.git;a=summary

[U-Boot] (no subject)

[md ks]

Hi,
    I am omap-3530, u-boot 1.3 version , while switching from u-boot
level to kernel level , i am getting flicker on LCD(display)., How to
remove that flicker.
I want flicker free booting from (CLEAN boot-up) from u-boot level to Kernel.
If anybody knows it , please help me.

Thank you,
mdks123

[U-Boot] (no subject)

[abby.zhang at semgfab.cn]

QUIT
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From: "SEMG" <abby.zhang@semgfab.cn>
To: "u-boot" <u-boot@lists.denx.de>
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[U-Boot] (no subject)

[Cote, Sylvain]

Hi,

 

Is it possible to load a initramfs compress CPIO image via u-boot like
we can do with a ramdisk image (replace the uRamdisk by a uInitramfs in
the command bellow)?

 

nand_all=chpart Kernel;fsload 0x200000 uImage;chpart Config;fsload
0x400000 uRamdisk;run ramargs addip addtty;bootm 200000 400000

 

If it is possible, I guest we need to generate a different image type
via the mkimage utility?

 

Thanks

 

Sylvain

 

 

 

 

 

 

 

 

[U-Boot] (no subject)

[Haiying Wang]

On Sat, 2008-10-04 at 01:35 +0200, Wolfgang Denk wrote:
> Dear Haiying Wang,
> 
> In message <1223051524-22415-1-git-send-email-Haiying.Wang@freescale.com> you wrote:
> > Fix some bugs:
> >   1. Correctly set intlv_ctl in cs_config.
> >   2. Correctly set sa, ea in cs_bnds when bank interleaving mode is enabled.
> >   3. Set base_address and total memory for each ddr controller in memory
> >      controller interleaving mode.
> 
> Can you please (re-) submit your patches with a valid subject?
> 
> Please keep in mind that the subject is used as the tile line of the
> commit message, so it is essential.
I am so sorry, please ignore the 6 patches without subject. I recognized
it right after I sent them, and re-submitted the correct patches with
[PATCH n/6] in the subject.

Haiying

[U-Boot] (no subject)

[Wolfgang Denk]

Dear Haiying Wang,

In message <1223051524-22415-1-git-send-email-Haiying.Wang@freescale.com> you wrote:
> Fix some bugs:
>   1. Correctly set intlv_ctl in cs_config.
>   2. Correctly set sa, ea in cs_bnds when bank interleaving mode is enabled.
>   3. Set base_address and total memory for each ddr controller in memory
>      controller interleaving mode.

Can you please (re-) submit your patches with a valid subject?

Please keep in mind that the subject is used as the tile line of the
commit message, so it is essential.



Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Often it is fatal to live too long.                          - Racine

[U-Boot] (no subject)

[Haiying Wang]

* Add board specific parameter table to choose correct cpo, clk_adjust,
write_data_delay based on board ddr frequency and n_ranks.

* Set odt_rd_cfg and odt_wr_cfg based on the dimm# and CS#.

Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
---
 board/freescale/mpc8641hpcn/ddr.c |  146 ++++++++++++++++++++++++++++---------
 1 files changed, 110 insertions(+), 36 deletions(-)

diff --git a/board/freescale/mpc8641hpcn/ddr.c b/board/freescale/mpc8641hpcn/ddr.c
index 23497f9..517c6ee 100644
--- a/board/freescale/mpc8641hpcn/ddr.c
+++ b/board/freescale/mpc8641hpcn/ddr.c
@@ -46,46 +46,120 @@ void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
 	}
 }
 
+typedef struct {
+        u32 datarate_mhz_low;
+        u32 datarate_mhz_high;
+        u32 n_ranks;
+        u32 clk_adjust;
+        u32 cpo;
+        u32 write_data_delay;
+} board_specific_parameters_t;
+
+/* XXX: these values need to be checked for all interleaving modes.  */
+const board_specific_parameters_t board_specific_parameters[2][16] = {
+	{
+	/* 	memory controller 0		 	*/
+	/*	  lo|  hi|  num|  clk| cpo|wrdata	*/
+	/*	 mhz| mhz|ranks|adjst|    | delay	*/
+		{  0, 333,    4,    7,   7,     3},
+		{334, 400,    4,    7,   9,     3},
+		{401, 549,    4,    7,   9,     3},
+		{550, 650,    4,    7,  10,     4},
+
+		{  0, 333,    3,    7,   7,     3},
+		{334, 400,    3,    7,   9,     3},
+		{401, 549,    3,    7,   9,     3},
+		{550, 650,    3,    7,  10,     4},
+
+		{  0, 333,    2,    7,   7,     3},
+		{334, 400,    2,    7,   9,     3},
+		{401, 549,    2,    7,   9,     3},
+		{550, 650,    2,    7,  10,     4},
+
+		{  0, 333,    1,    7,   7,     3},
+		{334, 400,    1,    7,   9,     3},
+		{401, 549,    1,    7,   9,     3},
+		{550, 650,    1,    7,  10,     4}
+	},
+
+	{
+	/* 	memory controller 1			*/
+	/*        lo|  hi|  num|  clk| cpo|wrdata	*/
+	/*       mhz| mhz|ranks|adjst|    | delay	*/
+		{  0, 333,    4,    7,   7,    3},
+		{334, 400,    4,    7,   9,    3},
+		{401, 549,    4,    7,   9,    3},
+		{550, 650,    4,    7,  10,    4},
+
+		{  0, 333,    3,    7,   7,    3},
+		{334, 400,    3,    7,   9,    3},
+		{401, 549,    3,    7,   9,    3},
+		{550, 650,    3,    7,  10,    4},
+
+		{  0, 333,    2,    7,   7,    3},
+		{334, 400,    2,    7,   9,    3},
+		{401, 549,    2,    7,   9,    3},
+		{550, 650,    2,    7,  10,    4},
+
+		{  0, 333,    1,    7,   7,    3},
+		{334, 400,    1,    7,   9,    3},
+		{401, 549,    1,    7,   9,    3},
+		{550, 650,    1,    7,  10,    4}
+	}
+};
+
 void fsl_ddr_board_options(memctl_options_t *popts,
-				dimm_params_t *pdimm,
-				unsigned int ctrl_num)
+			dimm_params_t *pdimm,
+			unsigned int ctrl_num)
 {
-	/*
-	 * Factors to consider for clock adjust:
-	 *	- number of chips on bus
-	 *	- position of slot
-	 *	- DDR1 vs. DDR2?
-	 *	- ???
-	 *
-	 * This needs to be determined on a board-by-board basis.
-	 *	0110	3/4 cycle late
-	 *	0111	7/8 cycle late
-	 */
-	popts->clk_adjust = 7;
+	const board_specific_parameters_t *pbsp =
+			&(board_specific_parameters[ctrl_num][0]);
+	u32 num_params = sizeof(board_specific_parameters[ctrl_num]) /
+			sizeof(board_specific_parameters[0][0]);
+	u32 i;
+	u32 j;
+	ulong ddr_freq;
 
-	/*
-	 * Factors to consider for CPO:
-	 *	- frequency
-	 *	- ddr1 vs. ddr2
+	/* set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in
+	 * that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If
+	 * there are two dimms in the controller, set odt_rd_cfg to 3 and
+	 * odt_wr_cfg to 3 for the even CS, 0 for the odd CS.
 	 */
-	popts->cpo_override = 10;
-
-	/*
-	 * Factors to consider for write data delay:
-	 *	- number of DIMMs
-	 *
-	 * 1 = 1/4 clock delay
-	 * 2 = 1/2 clock delay
-	 * 3 = 3/4 clock delay
-	 * 4 = 1   clock delay
-	 * 5 = 5/4 clock delay
-	 * 6 = 3/2 clock delay
-	 */
-	popts->write_data_delay = 3;
+	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+		if (i&1) {      /* odd CS */
+			popts->cs_local_opts[i].odt_rd_cfg = 0;
+			popts->cs_local_opts[i].odt_wr_cfg = 0;
+		} else {        /* even CS */
+			if ((CONFIG_DIMM_SLOTS_PER_CTLR == 2) &&
+				(pdimm[i/2].n_ranks != 0)) {
+				popts->cs_local_opts[i].odt_rd_cfg = 3;
+				popts->cs_local_opts[i].odt_wr_cfg = 3;
+			} else {
+				popts->cs_local_opts[i].odt_rd_cfg = 0;
+				popts->cs_local_opts[i].odt_wr_cfg = 4;
+			}
+		}
+	}
 
-	/*
-	 * Factors to consider for half-strength driver enable:
-	 *	- number of DIMMs installed
+	/* Get clk_adjust, cpo, write_data_delay, according to the board ddr
+	 * freqency and n_banks specified in board_specific_parameters table.
 	 */
-	popts->half_strength_driver_enable = 0;
+	ddr_freq = fsl_ddr_get_mem_data_rate() / 1000000;
+	for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
+		if (pdimm[j].n_ranks > 0) {
+			for (i = 0; i < num_params; i++) {
+				if (ddr_freq >= pbsp->datarate_mhz_low &&
+				ddr_freq <= pbsp->datarate_mhz_high &&
+				pdimm[j].n_ranks == pbsp->n_ranks) {
+					popts->clk_adjust = pbsp->clk_adjust;
+					popts->cpo_override = pbsp->cpo;
+					popts->write_data_delay =
+						pbsp->write_data_delay;
+					break;
+				}
+				pbsp++;
+			}
+		}
+	}
+
 }
-- 
1.6.0.2

[U-Boot] (no subject)

[Haiying Wang]

* Add board specific parameter table to choose correct cpo, clk_adjust,
write_data_delay, 2T based on board ddr frequency and n_ranks.

* Set odt_rd_cfg and odt_wr_cfg based on the dimm# and CS#.

* Set memory controller interleaving mode to bank interleaving, and disable
bank(chip select) interleaving mode by default, because the default on-board
DDR DIMMs are 2x512MB single-rank.

* Change CONFIG_ICS307_REFCLK_HZ from 33333333 to 33333000.

Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
---
 board/freescale/mpc8572ds/ddr.c |  123 ++++++++++++++++++++++++++++++---------
 include/configs/MPC8572DS.h     |    3 +-
 2 files changed, 97 insertions(+), 29 deletions(-)

diff --git a/board/freescale/mpc8572ds/ddr.c b/board/freescale/mpc8572ds/ddr.c
index 435893a..171a8d5 100644
--- a/board/freescale/mpc8572ds/ddr.c
+++ b/board/freescale/mpc8572ds/ddr.c
@@ -39,42 +39,109 @@ void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
 	}
 }
 
+typedef struct {
+	u32 datarate_mhz_low;
+	u32 datarate_mhz_high;
+	u32 n_ranks;
+	u32 clk_adjust;
+	u32 cpo;
+	u32 write_data_delay;
+	u32 force_2T;
+} board_specific_parameters_t;
+
+/* ranges for parameters:
+ *  wr_data_delay = 0-6
+ *  clk adjust = 0-8
+ *  cpo 2-0x1E (30)
+ */
+
+
+/* XXX: these values need to be checked for all interleaving modes.  */
+/* XXX: No reliable dual-rank 800 MHz setting has been found.  It may
+ *      seem reliable, but errors will appear when memory intensive
+ *      program is run. */
+/* XXX: Single rank at 800 MHz is OK.  */
+const board_specific_parameters_t board_specific_parameters[][20] = {
+	{
+	/* 	memory controller 0 			*/
+	/*	  lo|  hi|  num|  clk| cpo|wrdata|2T	*/
+	/*	 mhz| mhz|ranks|adjst|    | delay|	*/
+		{  0, 333,    2,    6,   7,    3,  0},
+		{334, 400,    2,    6,   9,    3,  0},
+		{401, 549,    2,    6,  11,    3,  0},
+		{550, 680,    2,    1,  10,    5,  0},
+		{681, 850,    2,    1,  12,    5,  1},
+		{  0, 333,    1,    6,   7,    3,  0},
+		{334, 400,    1,    6,   9,    3,  0},
+		{401, 549,    1,    6,  11,    3,  0},
+		{550, 680,    1,    1,  10,    5,  0},
+		{681, 850,    1,    1,  12,    5,  0}
+	},
+
+	{
+	/*	memory controller 1			*/
+	/*	  lo|  hi|  num|  clk| cpo|wrdata|2T	*/
+	/*	 mhz| mhz|ranks|adjst|    | delay|	*/
+		{  0, 333,    2,     6,  7,    3,  0},
+		{334, 400,    2,     6,  9,    3,  0},
+		{401, 549,    2,     6, 11,    3,  0},
+		{550, 680,    2,     1, 11,    6,  0},
+		{681, 850,    2,     1, 13,    6,  1},
+		{  0, 333,    1,     6,  7,    3,  0},
+		{334, 400,    1,     6,  9,    3,  0},
+		{401, 549,    1,     6, 11,    3,  0},
+		{550, 680,    1,     1, 11,    6,  0},
+		{681, 850,    1,     1, 13,    6,  0}
+	}
+};
+
 void fsl_ddr_board_options(memctl_options_t *popts,
 				dimm_params_t *pdimm,
 				unsigned int ctrl_num)
 {
-	/*
-	 * Factors to consider for clock adjust:
-	 *	- number of chips on bus
-	 *	- position of slot
-	 *	- DDR1 vs. DDR2?
-	 *	- ???
-	 *
-	 * This needs to be determined on a board-by-board basis.
-	 *	0110	3/4 cycle late
-	 *	0111	7/8 cycle late
-	 */
-	popts->clk_adjust = 7;
+	const board_specific_parameters_t *pbsp =
+				&(board_specific_parameters[ctrl_num][0]);
+	const char *p;
+	u32 num_params = sizeof(board_specific_parameters[ctrl_num]) /
+				sizeof(board_specific_parameters[0][0]);
+	u32 i;
+	ulong ddr_freq;
 
-	/*
-	 * Factors to consider for CPO:
-	 *	- frequency
-	 *	- ddr1 vs. ddr2
+	/* set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in
+	 * that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If
+	 * there are two dimms in the controller, set odt_rd_cfg to 3 and
+	 * odt_wr_cfg to 3 for the even CS, 0 for the odd CS.
 	 */
-	popts->cpo_override = 10;
+	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+		if (i&1) {	/* odd CS */
+			popts->cs_local_opts[i].odt_rd_cfg = 0;
+			popts->cs_local_opts[i].odt_wr_cfg = 0;
+		} else {	/* even CS */
+			if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) {
+				popts->cs_local_opts[i].odt_rd_cfg = 0;
+				popts->cs_local_opts[i].odt_wr_cfg = 4;
+			} else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) {
+			popts->cs_local_opts[i].odt_rd_cfg = 3;
+			popts->cs_local_opts[i].odt_wr_cfg = 3;
+			}
+		}
+	}
 
-	/*
-	 * Factors to consider for write data delay:
-	 *	- number of DIMMs
-	 *
-	 * 1 = 1/4 clock delay
-	 * 2 = 1/2 clock delay
-	 * 3 = 3/4 clock delay
-	 * 4 = 1   clock delay
-	 * 5 = 5/4 clock delay
-	 * 6 = 3/2 clock delay
+	/* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
+	 * freqency and n_banks specified in board_specific_parameters table.
 	 */
-	popts->write_data_delay = 5;
+	ddr_freq = get_ddr_freq(0) / 1000000;
+	for (i = 0; i < num_params; i++) {
+		if (ddr_freq >= pbsp->datarate_mhz_low &&
+		    ddr_freq <= pbsp->datarate_mhz_high &&
+		    pdimm->n_ranks == pbsp->n_ranks) {
+			popts->clk_adjust = pbsp->clk_adjust;
+			popts->cpo_override = pbsp->cpo;
+			popts->write_data_delay = pbsp->write_data_delay;
+			popts->twoT_en = pbsp->force_2T;
+		}
+		pbsp++;
+	}
 
 	/*
 	 * Factors to consider for half-strength driver enable:
diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h
index d7e3a88..82c2334 100644
--- a/include/configs/MPC8572DS.h
+++ b/include/configs/MPC8572DS.h
@@ -61,7 +61,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #endif
 #define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0) /* sysclk for MPC85xx */
 #define CONFIG_DDR_CLK_FREQ	get_board_ddr_clk(0) /* ddrclk for MPC85xx */
-#define CONFIG_ICS307_REFCLK_HZ	33333333  /* ICS307 clock chip ref freq */
+#define CONFIG_ICS307_REFCLK_HZ	33333000  /* ICS307 clock chip ref freq */
 #define CONFIG_GET_CLK_FROM_ICS307	  /* decode sysclk and ddrclk freq
 					     from ICS307 instead of switches */
 
@@ -532,6 +532,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_BAUDRATE	115200
 
 #define	CONFIG_EXTRA_ENV_SETTINGS				\
+ "memctl_intlv_ctl=2\0"						\
  "netdev=eth0\0"						\
  "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"				\
  "tftpflash=tftpboot $loadaddr $uboot; "			\
-- 
1.6.0.2

[U-Boot] (no subject)

[Haiying Wang]

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
---
 cpu/mpc8xxx/ddr/ctrl_regs.c |   13 +++++++++++++
 1 files changed, 13 insertions(+), 0 deletions(-)

diff --git a/cpu/mpc8xxx/ddr/ctrl_regs.c b/cpu/mpc8xxx/ddr/ctrl_regs.c
index 6297141..1783e92 100644
--- a/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/cpu/mpc8xxx/ddr/ctrl_regs.c
@@ -111,6 +111,7 @@ static void set_csn_config(int i, fsl_ddr_cfg_regs_t *ddr,
 		| ((row_bits_cs_n & 0x7) << 8)
 		| ((col_bits_cs_n & 0x7) << 0)
 		);
+	debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config);
 }
 
 /* Chip Select Configuration 2 (CSn_CONFIG_2) */
@@ -120,6 +121,7 @@ static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr)
 	unsigned int pasr_cfg = 0;	/* Partial array self refresh config */
 
 	ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24);
+	debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2);
 }
 
 /* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */
@@ -190,6 +192,7 @@ static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr,
 		| ((ext_caslat & 0x1) << 12)
 		| ((cntl_adj & 0x7) << 0)
 		);
+	debug("FSLDDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3);
 }
 
 /* DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) */
@@ -257,6 +260,7 @@ static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr,
 		| ((acttoact_mclk & 0x07) << 4)
 		| ((wrtord_mclk & 0x07) << 0)
 		);
+	debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1);
 }
 
 /* DDR SDRAM Timing Configuration 2 (TIMING_CFG_2) */
@@ -313,6 +317,7 @@ static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 		| ((cke_pls & 0x7) << 6)
 		| ((four_act & 0x1f) << 0)
 		);
+	debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2);
 }
 
 /* DDR SDRAM control configuration (DDR_SDRAM_CFG) */
@@ -379,6 +384,7 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
 			| ((mem_halt & 0x1) << 1)
 			| ((bi & 0x1) << 0)
 			);
+	debug("FSLDDR: ddr_sdram_cfg = 0x%08x\n", ddr->ddr_sdram_cfg);
 }
 
 /* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */
@@ -443,6 +449,7 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 		| ((rcw_en & 0x1) << 2)
 		| ((md_en & 0x1) << 0)
 		);
+	debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2);
 }
 
 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
@@ -455,6 +462,7 @@ static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr)
 				 | ((esdmode2 & 0xFFFF) << 16)
 				 | ((esdmode3 & 0xFFFF) << 0)
 				 );
+	debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
 }
 
 /* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */
@@ -474,6 +482,7 @@ static void set_ddr_sdram_interval(fsl_ddr_cfg_regs_t *ddr,
 				   | ((refint & 0xFFFF) << 16)
 				   | ((bstopre & 0x3FFF) << 0)
 				   );
+	debug("FSLDDR: ddr_sdram_interval = 0x%08x\n", ddr->ddr_sdram_interval);
 }
 
 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
@@ -607,6 +616,7 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
 			       | ((esdmode & 0xFFFF) << 16)
 			       | ((sdmode & 0xFFFF) << 0)
 			       );
+	debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
 }
 
 
@@ -669,6 +679,7 @@ static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr)
 			     | ((wwt & 0xf) << 16)
 			     | (dll_lock & 0x3)
 			     );
+	debug("FSLDDR: timing_cfg_4 = 0x%08x\n", ddr->timing_cfg_4);
 }
 
 /* DDR SDRAM Timing Configuration 5 (TIMING_CFG_5) */
@@ -685,6 +696,7 @@ static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr)
 			     | ((wodt_on & 0xf) << 12)
 			     | ((wodt_off & 0xf) << 8)
 			     );
+	debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5);
 }
 
 /* DDR ZQ Calibration Control (DDR_ZQ_CNTL) */
@@ -992,6 +1004,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
 			| ((ea & 0xFFF) << 0)	/* ending address MSB */
 			);
 
+		debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds);
 		set_csn_config(i, ddr, popts, dimm_params);
 		set_csn_config_2(i, ddr);
 	}
-- 
1.6.0.2

[U-Boot] (no subject)

[Haiying Wang]

* Check DDR interleaving mode from environment by reading memctl_intlv_ctl and
ba_intlv_ctl.
* Print DDR interleaving mode information
* Add doc/README.fsl-ddr to describe the interleaving setting

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
---
 cpu/mpc8xxx/ddr/main.c    |   37 +++++++++++++++++++++
 cpu/mpc8xxx/ddr/options.c |   80 ++++++++++++++++++++++++++++++++++++++++++---
 doc/README.fsl-ddr        |   69 ++++++++++++++++++++++++++++++++++++++
 3 files changed, 181 insertions(+), 5 deletions(-)
 create mode 100644 doc/README.fsl-ddr

diff --git a/cpu/mpc8xxx/ddr/main.c b/cpu/mpc8xxx/ddr/main.c
index 98a8651..d5173c3 100644
--- a/cpu/mpc8xxx/ddr/main.c
+++ b/cpu/mpc8xxx/ddr/main.c
@@ -164,6 +164,24 @@ int step_assign_addresses(fsl_ddr_info_t *pinfo,
 	}
 	if (j == 2) {
 		*memctl_interleaving = 1;
+
+		printf("\nMemory controller interleaving enabled: ");
+
+		switch (pinfo->memctl_opts[0].memctl_interleaving_mode) {
+		case FSL_DDR_CACHE_LINE_INTERLEAVING:
+			printf("Cache-line interleaving!\n");
+			break;
+		case FSL_DDR_PAGE_INTERLEAVING:
+			printf("Page interleaving!\n");
+			break;
+		case FSL_DDR_BANK_INTERLEAVING:
+			printf("Bank interleaving!\n");
+			break;
+		case FSL_DDR_SUPERBANK_INTERLEAVING:
+			printf("Super bank interleaving\n");
+		default:
+			break;
+		}
 	}
 
 	/* Check that all controllers are rank interleaving. */
@@ -175,6 +193,25 @@ int step_assign_addresses(fsl_ddr_info_t *pinfo,
 	}
 	if (j == 2) {
 		*rank_interleaving = 1;
+
+		printf("Bank(chip-select) interleaving enabled: ");
+
+		switch (pinfo->memctl_opts[0].ba_intlv_ctl &
+						FSL_DDR_CS0_CS1_CS2_CS3) {
+		case FSL_DDR_CS0_CS1_CS2_CS3:
+			printf("CS0+CS1+CS2+CS3\n");
+			break;
+		case FSL_DDR_CS0_CS1:
+			printf("CS0+CS1\n");
+			break;
+		case FSL_DDR_CS2_CS3:
+			printf("CS2+CS3\n");
+			break;
+		case FSL_DDR_CS0_CS1_AND_CS2_CS3:
+			printf("CS0+CS1 and CS2+CS3\n");
+		default:
+			break;
+		}
 	}
 
 	if (*memctl_interleaving) {
diff --git a/cpu/mpc8xxx/ddr/options.c b/cpu/mpc8xxx/ddr/options.c
index 99b5685..714e88d 100644
--- a/cpu/mpc8xxx/ddr/options.c
+++ b/cpu/mpc8xxx/ddr/options.c
@@ -22,6 +22,7 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
 			unsigned int ctrl_num)
 {
 	unsigned int i;
+	const char *p;
 
 	/* Chip select options. */
 
@@ -181,17 +182,86 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
 #error "FIXME determine four activates for DDR3"
 #endif
 
-	/* ODT should only be used for DDR2 */
-
-	/* FIXME? */
-
 	/*
-	 * Interleaving checks.
+	 * Check interleaving configuration from environment.
+	 * Please refer to doc/README.fsl-ddr for the detail.
 	 *
 	 * If memory controller interleaving is enabled, then the data
 	 * bus widths must be programmed identically for the 2 memory
 	 * controllers.
+	 *
+	 * XXX: Attempt to set both controllers to the same chip select
+	 * interleaving mode. It will do a best effort to get the
+	 * requested ranks interleaved together such that the result
+	 * should be a subset of the requested configuration.
 	 */
+	if ((p = getenv("memctl_intlv_ctl")) != NULL) {
+		if (pdimm[0].n_ranks == 0) {
+			printf("There is no rank on CS0. Because only rank on \
+				CS0 and ranks chip-select interleaved with CS0\
+				are controller interleaved, force non memory \
+				controller interleaving\n");
+			popts->memctl_interleaving = 0;
+		} else {
+			popts->memctl_interleaving = 1;
+			if (strcmp(p, "cacheline") == 0)
+				popts->memctl_interleaving_mode =
+					FSL_DDR_CACHE_LINE_INTERLEAVING;
+			else if (strcmp(p, "page") == 0)
+				popts->memctl_interleaving_mode =
+					FSL_DDR_PAGE_INTERLEAVING;
+			else if (strcmp(p, "bank") == 0)
+				popts->memctl_interleaving_mode =
+					FSL_DDR_BANK_INTERLEAVING;
+			else if (strcmp(p, "superbank") == 0)
+				popts->memctl_interleaving_mode =
+					FSL_DDR_SUPERBANK_INTERLEAVING;
+			else
+				popts->memctl_interleaving_mode =
+						simple_strtoul(p, NULL, 0);
+		}
+	}
+
+	if( (p = getenv("ba_intlv_ctl")) != NULL) {
+		if (strcmp(p, "cs0_cs1") == 0)
+			popts->ba_intlv_ctl = FSL_DDR_CS0_CS1;
+		else if (strcmp(p, "cs2_cs3") == 0)
+			popts->ba_intlv_ctl = FSL_DDR_CS2_CS3;
+		else if (strcmp(p, "cs0_cs1_and_cs2_cs3") == 0)
+			popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_AND_CS2_CS3;
+		else if (strcmp(p, "cs0_cs1_cs2_cs3") == 0)
+			popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_CS2_CS3;
+		else
+			popts->ba_intlv_ctl = simple_strtoul(p, NULL, 0);
+
+		switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
+		case FSL_DDR_CS0_CS1_CS2_CS3:
+		case FSL_DDR_CS0_CS1:
+			if (pdimm[0].n_ranks != 2) {
+				popts->ba_intlv_ctl = 0;
+				printf("No enough bank(chip-select) for \
+					CS0+CS1, force non-interleaving!\n");
+			}
+			break;
+		case FSL_DDR_CS2_CS3:
+			if (pdimm[1].n_ranks !=2){
+				popts->ba_intlv_ctl = 0;
+				printf("No enough bank(CS) for CS2+CS3, \
+					force non-interleaving!\n");
+			}
+			break;
+		case FSL_DDR_CS0_CS1_AND_CS2_CS3:
+			if ((pdimm[0].n_ranks != 2)||(pdimm[1].n_ranks != 2)) {
+				popts->ba_intlv_ctl = 0;
+				printf("No enough bank(CS) for CS0+CS1 or \
+					 CS2+CS3, force non-interleaving!\n");
+			}
+			break;
+		default:
+			popts->ba_intlv_ctl = 0;
+			break;
+		}
+	}
 
 	fsl_ddr_board_options(popts, pdimm, ctrl_num);
 
diff --git a/doc/README.fsl-ddr b/doc/README.fsl-ddr
new file mode 100644
index 0000000..357ec05
--- /dev/null
+++ b/doc/README.fsl-ddr
@@ -0,0 +1,69 @@
+
+Table of interleaving modes supported in cpu/8xxx/ddr/
+======================================================
+  +-------------+---------------------------------------------------------+
+  |             |                   Rank Interleaving                     |
+  |             +--------+-----------+-----------+------------+-----------+
+  |Memory       |        |           |           |    2x2     |    4x1    |
+  |Controller   |  None  | 2x1 lower | 2x1 upper | {CS0+CS1}, | {CS0+CS1+ |
+  |Interleaving |        | {CS0+CS1} | {CS2+CS3} | {CS2+CS3}  |  CS2+CS3} |
+  +-------------+--------+-----------+-----------+------------+-----------+
+  |None         |  Yes   | Yes       | Yes       | Yes        | Yes       |
+  +-------------+--------+-----------+-----------+------------+-----------+
+  |Cacheline    |  Yes   | Yes       | No        | No, Only(*)| Yes       |
+  |             |CS0 Only|           |           | {CS0+CS1}  |           |
+  +-------------+--------+-----------+-----------+------------+-----------+
+  |Page         |  Yes   | Yes       | No        | No, Only(*)| Yes       |
+  |             |CS0 Only|           |           | {CS0+CS1}  |           |
+  +-------------+--------+-----------+-----------+------------+-----------+
+  |Bank         |  Yes   | Yes       | No        | No, Only(*)| Yes       |
+  |             |CS0 Only|           |           | {CS0+CS1}  |           |
+  +-------------+--------+-----------+-----------+------------+-----------+
+  |Superbank    |  No    | Yes       | No        | No, Only(*)| Yes       |
+  |             |        |           |           | {CS0+CS1}  |           |
+  +-------------+--------+-----------+-----------+------------+-----------+
+ (*) Although the hardware can be configured with memory controller
+ interleaving using "2x2" rank interleaving, it only interleaves {CS0+CS1}
+ from each controller. {CS2+CS3} on each controller are only rank
+ interleaved on that controller.
+
+The ways to configure the ddr interleaving mode
+==============================================
+1. In board header file(e.g.MPC8572DS.h), add default interleaving setting
+   under "CONFIG_EXTRA_ENV_SETTINGS", like:
+	#define CONFIG_EXTRA_ENV_SETTINGS				\
+	 "memctl_intlv_ctl=2\0"						\
+	 ......
+
+2. Run u-boot "setenv" command to configure the memory interleaving mode.
+   Either numerical or string value is accepted.
+
+  # disable memory controller interleaving
+  setenv memctl_intlv_ctl
+
+  # cacheline interleaving
+  setenv memctl_intlv_ctl 0 or setenv memctl_intlv_ctl cacheline
+
+  # page interleaving
+  setenv memctl_intlv_ctl 1 or setenv memctl_intlv_ctl page
+
+  # bank interleaving
+  setenv memctl_intlv_ctl 2 or setenv memctl_intlv_ctl bank
+
+  # superbank
+  setenv memctl_intlv_ctl 3 or setenv memctl_intlv_ctl superbank
+
+  # disable bank (chip-select) interleaving
+  setenv ba_intlv_ctl
+
+  # bank(chip-select) interleaving cs0+cs1
+  setenv ba_intlv_ctl 0x40 or setenv ba_intlv_ctl cs0_cs1
+
+  # bank(chip-select) interleaving cs2+cs3
+  setenv ba_intlv_ctl 0x20 or setenv ba_intlv_ctl cs2_cs3
+
+  # bank(chip-select) interleaving (cs0+cs1) and (cs2+cs3)  (2x2)
+  setenv ba_intlv_ctl 0x60 or setenv ba_intlv_ctl cs0_cs1_and_cs2_cs3
+
+  # bank(chip-select) interleaving (cs0+cs1+cs2+cs3) (4x1)
+  setenv ba_intlv_ctl 0x04 or setenv ba_intlv_ctl cs0_cs1_cs2_cs3
+
-- 
1.6.0.2

[U-Boot] (no subject)

[Haiying Wang]

Because some dimm parameters like n_ranks needs to be used with the board
frequency to choose the board parameters like clk_adjust etc. in the
board_specific_paramesters table of the board ddr file, we need to pass
the dimm parameters to the board file.

* move ddr dimm parameters header file from /cpu to /include directory.
* add ddr dimm parameters to populate board specific options.
* Fix fsl_ddr_board_options() for all the 8xxx boards which call this function.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
---
 board/atum8548/ddr.c                  |    5 ++-
 board/freescale/mpc8536ds/ddr.c       |    5 ++-
 board/freescale/mpc8540ads/ddr.c      |    5 ++-
 board/freescale/mpc8541cds/ddr.c      |    5 ++-
 board/freescale/mpc8544ds/ddr.c       |    5 ++-
 board/freescale/mpc8548cds/ddr.c      |    5 ++-
 board/freescale/mpc8555cds/ddr.c      |    5 ++-
 board/freescale/mpc8560ads/ddr.c      |    5 ++-
 board/freescale/mpc8568mds/ddr.c      |    5 ++-
 board/freescale/mpc8572ds/ddr.c       |    5 ++-
 board/freescale/mpc8610hpcd/ddr.c     |    5 ++-
 board/freescale/mpc8641hpcn/ddr.c     |    5 ++-
 board/mpc8540eval/ddr.c               |    5 ++-
 board/pm854/ddr.c                     |    5 ++-
 board/pm856/ddr.c                     |    5 ++-
 board/sbc8548/ddr.c                   |    5 ++-
 board/sbc8560/ddr.c                   |    5 ++-
 board/sbc8641d/ddr.c                  |    5 ++-
 board/socrates/ddr.c                  |    5 ++-
 board/stxgp3/ddr.c                    |    5 ++-
 board/stxssa/ddr.c                    |    5 ++-
 cpu/mpc8xxx/ddr/ddr.h                 |    3 +-
 cpu/mpc8xxx/ddr/ddr1_2_dimm_params.h  |   84 ---------------------------------
 cpu/mpc8xxx/ddr/main.c                |    3 +-
 cpu/mpc8xxx/ddr/options.c             |    4 +-
 include/asm-ppc/fsl_ddr_dimm_params.h |   84 +++++++++++++++++++++++++++++++++
 26 files changed, 175 insertions(+), 108 deletions(-)
 delete mode 100644 cpu/mpc8xxx/ddr/ddr1_2_dimm_params.h
 create mode 100644 include/asm-ppc/fsl_ddr_dimm_params.h

diff --git a/board/atum8548/ddr.c b/board/atum8548/ddr.c
index f07d746..ab64fa8 100644
--- a/board/atum8548/ddr.c
+++ b/board/atum8548/ddr.c
@@ -10,6 +10,7 @@
 #include <i2c.h>
 
 #include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
 
 static void
 get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
@@ -37,7 +38,9 @@ void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
 	}
 }
 
-void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num)
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
 {
 	/*
 	 * Factors to consider for clock adjust:
diff --git a/board/freescale/mpc8536ds/ddr.c b/board/freescale/mpc8536ds/ddr.c
index 2e88c79..3135d6d 100644
--- a/board/freescale/mpc8536ds/ddr.c
+++ b/board/freescale/mpc8536ds/ddr.c
@@ -10,6 +10,7 @@
 #include <i2c.h>
 
 #include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
 
 static void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
 {
@@ -36,7 +37,9 @@ void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
 	}
 }
 
-void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num)
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
 {
 	/*
 	 * Factors to consider for clock adjust:
diff --git a/board/freescale/mpc8540ads/ddr.c b/board/freescale/mpc8540ads/ddr.c
index 45372f4..7850794 100644
--- a/board/freescale/mpc8540ads/ddr.c
+++ b/board/freescale/mpc8540ads/ddr.c
@@ -10,6 +10,7 @@
 #include <i2c.h>
 
 #include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
 
 static void
 get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address)
@@ -40,7 +41,9 @@ fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd,
 	}
 }
 
-void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num)
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
 {
 	/*
 	 * Factors to consider for CPO:
diff --git a/board/freescale/mpc8541cds/ddr.c b/board/freescale/mpc8541cds/ddr.c
index 11ce57d..c84a6cb 100644
--- a/board/freescale/mpc8541cds/ddr.c
+++ b/board/freescale/mpc8541cds/ddr.c
@@ -10,6 +10,7 @@
 #include <i2c.h>
 
 #include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
 
 static void
 get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address)
@@ -36,7 +37,9 @@ void fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd,
 	}
 }
 
-void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num)
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
 {
 	/*
 	 * Factors to consider for clock adjust:
diff --git a/board/freescale/mpc8544ds/ddr.c b/board/freescale/mpc8544ds/ddr.c
index bbb5ee2..34f84a2 100644
--- a/board/freescale/mpc8544ds/ddr.c
+++ b/board/freescale/mpc8544ds/ddr.c
@@ -10,6 +10,7 @@
 #include <i2c.h>
 
 #include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
 
 static void
 get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
@@ -37,7 +38,9 @@ void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
 	}
 }
 
-void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num)
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
 {
 	/*
 	 * Factors to consider for clock adjust:
diff --git a/board/freescale/mpc8548cds/ddr.c b/board/freescale/mpc8548cds/ddr.c
index f07d746..ab64fa8 100644
--- a/board/freescale/mpc8548cds/ddr.c
+++ b/board/freescale/mpc8548cds/ddr.c
@@ -10,6 +10,7 @@
 #include <i2c.h>
 
 #include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
 
 static void
 get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
@@ -37,7 +38,9 @@ void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
 	}
 }
 
-void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num)
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
 {
 	/*
 	 * Factors to consider for clock adjust:
diff --git a/board/freescale/mpc8555cds/ddr.c b/board/freescale/mpc8555cds/ddr.c
index 11ce57d..c84a6cb 100644
--- a/board/freescale/mpc8555cds/ddr.c
+++ b/board/freescale/mpc8555cds/ddr.c
@@ -10,6 +10,7 @@
 #include <i2c.h>
 
 #include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
 
 static void
 get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address)
@@ -36,7 +37,9 @@ void fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd,
 	}
 }
 
-void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num)
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
 {
 	/*
 	 * Factors to consider for clock adjust:
diff --git a/board/freescale/mpc8560ads/ddr.c b/board/freescale/mpc8560ads/ddr.c
index 45372f4..7850794 100644
--- a/board/freescale/mpc8560ads/ddr.c
+++ b/board/freescale/mpc8560ads/ddr.c
@@ -10,6 +10,7 @@
 #include <i2c.h>
 
 #include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
 
 static void
 get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address)
@@ -40,7 +41,9 @@ fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd,
 	}
 }
 
-void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num)
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
 {
 	/*
 	 * Factors to consider for CPO:
diff --git a/board/freescale/mpc8568mds/ddr.c b/board/freescale/mpc8568mds/ddr.c
index 1b8ecec..482fd91 100644
--- a/board/freescale/mpc8568mds/ddr.c
+++ b/board/freescale/mpc8568mds/ddr.c
@@ -10,6 +10,7 @@
 #include <i2c.h>
 
 #include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
 
 static void
 get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
@@ -38,7 +39,9 @@ void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
 	}
 }
 
-void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num)
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
 {
 	/*
 	 * Factors to consider for clock adjust:
diff --git a/board/freescale/mpc8572ds/ddr.c b/board/freescale/mpc8572ds/ddr.c
index 5f8c555..435893a 100644
--- a/board/freescale/mpc8572ds/ddr.c
+++ b/board/freescale/mpc8572ds/ddr.c
@@ -10,6 +10,7 @@
 #include <i2c.h>
 
 #include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
 
 static void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
 {
@@ -38,7 +39,9 @@ void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
 	}
 }
 
-void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num)
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
 {
 	/*
 	 * Factors to consider for clock adjust:
diff --git a/board/freescale/mpc8610hpcd/ddr.c b/board/freescale/mpc8610hpcd/ddr.c
index 2d22da1..414ac24 100644
--- a/board/freescale/mpc8610hpcd/ddr.c
+++ b/board/freescale/mpc8610hpcd/ddr.c
@@ -10,6 +10,7 @@
 #include <i2c.h>
 
 #include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
 
 static void
 get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
@@ -36,7 +37,9 @@ void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
 	}
 }
 
-void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num)
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
 {
 	/*
 	 * Factors to consider for clock adjust:
diff --git a/board/freescale/mpc8641hpcn/ddr.c b/board/freescale/mpc8641hpcn/ddr.c
index 5163abf..23497f9 100644
--- a/board/freescale/mpc8641hpcn/ddr.c
+++ b/board/freescale/mpc8641hpcn/ddr.c
@@ -10,6 +10,7 @@
 #include <i2c.h>
 
 #include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
 
 static void
 get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
@@ -45,7 +46,9 @@ void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
 	}
 }
 
-void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num)
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
 {
 	/*
 	 * Factors to consider for clock adjust:
diff --git a/board/mpc8540eval/ddr.c b/board/mpc8540eval/ddr.c
index 45372f4..7850794 100644
--- a/board/mpc8540eval/ddr.c
+++ b/board/mpc8540eval/ddr.c
@@ -10,6 +10,7 @@
 #include <i2c.h>
 
 #include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
 
 static void
 get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address)
@@ -40,7 +41,9 @@ fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd,
 	}
 }
 
-void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num)
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
 {
 	/*
 	 * Factors to consider for CPO:
diff --git a/board/pm854/ddr.c b/board/pm854/ddr.c
index 45372f4..7850794 100644
--- a/board/pm854/ddr.c
+++ b/board/pm854/ddr.c
@@ -10,6 +10,7 @@
 #include <i2c.h>
 
 #include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
 
 static void
 get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address)
@@ -40,7 +41,9 @@ fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd,
 	}
 }
 
-void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num)
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
 {
 	/*
 	 * Factors to consider for CPO:
diff --git a/board/pm856/ddr.c b/board/pm856/ddr.c
index 45372f4..7850794 100644
--- a/board/pm856/ddr.c
+++ b/board/pm856/ddr.c
@@ -10,6 +10,7 @@
 #include <i2c.h>
 
 #include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
 
 static void
 get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address)
@@ -40,7 +41,9 @@ fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd,
 	}
 }
 
-void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num)
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
 {
 	/*
 	 * Factors to consider for CPO:
diff --git a/board/sbc8548/ddr.c b/board/sbc8548/ddr.c
index f07d746..ab64fa8 100644
--- a/board/sbc8548/ddr.c
+++ b/board/sbc8548/ddr.c
@@ -10,6 +10,7 @@
 #include <i2c.h>
 
 #include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
 
 static void
 get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
@@ -37,7 +38,9 @@ void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
 	}
 }
 
-void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num)
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
 {
 	/*
 	 * Factors to consider for clock adjust:
diff --git a/board/sbc8560/ddr.c b/board/sbc8560/ddr.c
index 45372f4..7850794 100644
--- a/board/sbc8560/ddr.c
+++ b/board/sbc8560/ddr.c
@@ -10,6 +10,7 @@
 #include <i2c.h>
 
 #include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
 
 static void
 get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address)
@@ -40,7 +41,9 @@ fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd,
 	}
 }
 
-void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num)
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
 {
 	/*
 	 * Factors to consider for CPO:
diff --git a/board/sbc8641d/ddr.c b/board/sbc8641d/ddr.c
index 5163abf..23497f9 100644
--- a/board/sbc8641d/ddr.c
+++ b/board/sbc8641d/ddr.c
@@ -10,6 +10,7 @@
 #include <i2c.h>
 
 #include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
 
 static void
 get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
@@ -45,7 +46,9 @@ void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
 	}
 }
 
-void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num)
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
 {
 	/*
 	 * Factors to consider for clock adjust:
diff --git a/board/socrates/ddr.c b/board/socrates/ddr.c
index 62a5951..2b62b84 100644
--- a/board/socrates/ddr.c
+++ b/board/socrates/ddr.c
@@ -10,6 +10,7 @@
 #include <i2c.h>
 
 #include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
 
 static void
 get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
@@ -37,7 +38,9 @@ void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
 	}
 }
 
-void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num)
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
 {
 	/*
 	 * Factors to consider for clock adjust:
diff --git a/board/stxgp3/ddr.c b/board/stxgp3/ddr.c
index 45372f4..7850794 100644
--- a/board/stxgp3/ddr.c
+++ b/board/stxgp3/ddr.c
@@ -10,6 +10,7 @@
 #include <i2c.h>
 
 #include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
 
 static void
 get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address)
@@ -40,7 +41,9 @@ fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd,
 	}
 }
 
-void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num)
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
 {
 	/*
 	 * Factors to consider for CPO:
diff --git a/board/stxssa/ddr.c b/board/stxssa/ddr.c
index 45372f4..7850794 100644
--- a/board/stxssa/ddr.c
+++ b/board/stxssa/ddr.c
@@ -10,6 +10,7 @@
 #include <i2c.h>
 
 #include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
 
 static void
 get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address)
@@ -40,7 +41,9 @@ fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd,
 	}
 }
 
-void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num)
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
 {
 	/*
 	 * Factors to consider for CPO:
diff --git a/cpu/mpc8xxx/ddr/ddr.h b/cpu/mpc8xxx/ddr/ddr.h
index f5dc40a..0372164 100644
--- a/cpu/mpc8xxx/ddr/ddr.h
+++ b/cpu/mpc8xxx/ddr/ddr.h
@@ -10,8 +10,8 @@
 #define FSL_DDR_MAIN_H
 
 #include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
 
-#include "ddr1_2_dimm_params.h"
 #include "common_timing_params.h"
 
 /*
@@ -71,6 +71,7 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
 				      unsigned int number_of_dimms);
 extern unsigned int populate_memctl_options(int all_DIMMs_registered,
 				memctl_options_t *popts,
+				dimm_params_t *pdimm,
 				unsigned int ctrl_num);
 
 extern unsigned int mclk_to_picos(unsigned int mclk);
diff --git a/cpu/mpc8xxx/ddr/ddr1_2_dimm_params.h b/cpu/mpc8xxx/ddr/ddr1_2_dimm_params.h
deleted file mode 100644
index c794eed..0000000
--- a/cpu/mpc8xxx/ddr/ddr1_2_dimm_params.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- */
-
-#ifndef DDR2_DIMM_PARAMS_H
-#define DDR2_DIMM_PARAMS_H
-
-/* Parameters for a DDR2 dimm computed from the SPD */
-typedef struct dimm_params_s {
-
-	/* DIMM organization parameters */
-	char mpart[19];		/* guaranteed null terminated */
-
-	unsigned int n_ranks;
-	unsigned long long rank_density;
-	unsigned long long capacity;
-	unsigned int data_width;
-	unsigned int primary_sdram_width;
-	unsigned int ec_sdram_width;
-	unsigned int registered_dimm;
-
-	/* SDRAM device parameters */
-	unsigned int n_row_addr;
-	unsigned int n_col_addr;
-	unsigned int edc_config;	/* 0 = none, 1 = parity, 2 = ECC */
-	unsigned int n_banks_per_sdram_device;
-	unsigned int burst_lengths_bitmask;	/* BL=4 bit 2, BL=8 = bit 3 */
-	unsigned int row_density;
-
-	/* used in computing base address of DIMMs */
-	unsigned long long base_address;
-
-	/* DIMM timing parameters */
-
-	/*
-	 * SDRAM clock periods
-	 * The range for these are 1000-10000 so a short should be sufficient
-	 */
-	unsigned int tCKmin_X_ps;
-	unsigned int tCKmin_X_minus_1_ps;
-	unsigned int tCKmin_X_minus_2_ps;
-	unsigned int tCKmax_ps;
-
-	/* SPD-defined CAS latencies */
-	unsigned int caslat_X;
-	unsigned int caslat_X_minus_1;
-	unsigned int caslat_X_minus_2;
-
-	unsigned int caslat_lowest_derated;	/* Derated CAS latency */
-
-	/* basic timing parameters */
-	unsigned int tRCD_ps;
-	unsigned int tRP_ps;
-	unsigned int tRAS_ps;
-
-	unsigned int tWR_ps;	/* maximum = 63750 ps */
-	unsigned int tWTR_ps;	/* maximum = 63750 ps */
-	unsigned int tRFC_ps;   /* max = 255 ns + 256 ns + .75 ns
-				       = 511750 ps */
-
-	unsigned int tRRD_ps;	/* maximum = 63750 ps */
-	unsigned int tRC_ps;	/* maximum = 254 ns + .75 ns = 254750 ps */
-
-	unsigned int refresh_rate_ps;
-
-	unsigned int tIS_ps;	/* byte 32, spd->ca_setup */
-	unsigned int tIH_ps;	/* byte 33, spd->ca_hold */
-	unsigned int tDS_ps;	/* byte 34, spd->data_setup */
-	unsigned int tDH_ps;	/* byte 35, spd->data_hold */
-	unsigned int tRTP_ps;	/* byte 38, spd->trtp */
-	unsigned int tDQSQ_max_ps;	/* byte 44, spd->tdqsq */
-	unsigned int tQHS_ps;	/* byte 45, spd->tqhs */
-} dimm_params_t;
-
-extern unsigned int ddr_compute_dimm_parameters(
-					 const generic_spd_eeprom_t *spd,
-					 dimm_params_t *pdimm,
-					 unsigned int dimm_number);
-
-#endif
diff --git a/cpu/mpc8xxx/ddr/main.c b/cpu/mpc8xxx/ddr/main.c
index d26c5c5..98a8651 100644
--- a/cpu/mpc8xxx/ddr/main.c
+++ b/cpu/mpc8xxx/ddr/main.c
@@ -319,7 +319,8 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step)
 			 */
 			populate_memctl_options(
 					timing_params[i].all_DIMMs_registered,
-					&pinfo->memctl_opts[i], i);
+					&pinfo->memctl_opts[i],
+					&pinfo->dimm_params[i], i);
 		}
 
 	case STEP_ASSIGN_ADDRESSES:
diff --git a/cpu/mpc8xxx/ddr/options.c b/cpu/mpc8xxx/ddr/options.c
index 6c2b43c..99b5685 100644
--- a/cpu/mpc8xxx/ddr/options.c
+++ b/cpu/mpc8xxx/ddr/options.c
@@ -13,10 +13,12 @@
 
 /* Board-specific functions defined in each board's ddr.c */
 extern void fsl_ddr_board_options(memctl_options_t *popts,
+		dimm_params_t *pdimm,
 		unsigned int ctrl_num);
 
 unsigned int populate_memctl_options(int all_DIMMs_registered,
 			memctl_options_t *popts,
+			dimm_params_t *pdimm,
 			unsigned int ctrl_num)
 {
 	unsigned int i;
@@ -191,7 +193,7 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
 	 * controllers.
 	 */
 
-	fsl_ddr_board_options(popts, ctrl_num);
+	fsl_ddr_board_options(popts, pdimm, ctrl_num);
 
 	return 0;
 }
diff --git a/include/asm-ppc/fsl_ddr_dimm_params.h b/include/asm-ppc/fsl_ddr_dimm_params.h
new file mode 100644
index 0000000..c794eed
--- /dev/null
+++ b/include/asm-ppc/fsl_ddr_dimm_params.h
@@ -0,0 +1,84 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#ifndef DDR2_DIMM_PARAMS_H
+#define DDR2_DIMM_PARAMS_H
+
+/* Parameters for a DDR2 dimm computed from the SPD */
+typedef struct dimm_params_s {
+
+	/* DIMM organization parameters */
+	char mpart[19];		/* guaranteed null terminated */
+
+	unsigned int n_ranks;
+	unsigned long long rank_density;
+	unsigned long long capacity;
+	unsigned int data_width;
+	unsigned int primary_sdram_width;
+	unsigned int ec_sdram_width;
+	unsigned int registered_dimm;
+
+	/* SDRAM device parameters */
+	unsigned int n_row_addr;
+	unsigned int n_col_addr;
+	unsigned int edc_config;	/* 0 = none, 1 = parity, 2 = ECC */
+	unsigned int n_banks_per_sdram_device;
+	unsigned int burst_lengths_bitmask;	/* BL=4 bit 2, BL=8 = bit 3 */
+	unsigned int row_density;
+
+	/* used in computing base address of DIMMs */
+	unsigned long long base_address;
+
+	/* DIMM timing parameters */
+
+	/*
+	 * SDRAM clock periods
+	 * The range for these are 1000-10000 so a short should be sufficient
+	 */
+	unsigned int tCKmin_X_ps;
+	unsigned int tCKmin_X_minus_1_ps;
+	unsigned int tCKmin_X_minus_2_ps;
+	unsigned int tCKmax_ps;
+
+	/* SPD-defined CAS latencies */
+	unsigned int caslat_X;
+	unsigned int caslat_X_minus_1;
+	unsigned int caslat_X_minus_2;
+
+	unsigned int caslat_lowest_derated;	/* Derated CAS latency */
+
+	/* basic timing parameters */
+	unsigned int tRCD_ps;
+	unsigned int tRP_ps;
+	unsigned int tRAS_ps;
+
+	unsigned int tWR_ps;	/* maximum = 63750 ps */
+	unsigned int tWTR_ps;	/* maximum = 63750 ps */
+	unsigned int tRFC_ps;   /* max = 255 ns + 256 ns + .75 ns
+				       = 511750 ps */
+
+	unsigned int tRRD_ps;	/* maximum = 63750 ps */
+	unsigned int tRC_ps;	/* maximum = 254 ns + .75 ns = 254750 ps */
+
+	unsigned int refresh_rate_ps;
+
+	unsigned int tIS_ps;	/* byte 32, spd->ca_setup */
+	unsigned int tIH_ps;	/* byte 33, spd->ca_hold */
+	unsigned int tDS_ps;	/* byte 34, spd->data_setup */
+	unsigned int tDH_ps;	/* byte 35, spd->data_hold */
+	unsigned int tRTP_ps;	/* byte 38, spd->trtp */
+	unsigned int tDQSQ_max_ps;	/* byte 44, spd->tdqsq */
+	unsigned int tQHS_ps;	/* byte 45, spd->tqhs */
+} dimm_params_t;
+
+extern unsigned int ddr_compute_dimm_parameters(
+					 const generic_spd_eeprom_t *spd,
+					 dimm_params_t *pdimm,
+					 unsigned int dimm_number);
+
+#endif
-- 
1.6.0.2

[U-Boot] (no subject)

[Haiying Wang]

Fix some bugs:
  1. Correctly set intlv_ctl in cs_config.
  2. Correctly set sa, ea in cs_bnds when bank interleaving mode is enabled.
  3. Set base_address and total memory for each ddr controller in memory
     controller interleaving mode.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
---
 cpu/mpc8xxx/ddr/ctrl_regs.c     |   61 +++++++++++++++++++++++++++++++-------
 cpu/mpc8xxx/ddr/main.c          |    5 +++
 include/asm-ppc/fsl_ddr_sdram.h |   12 +++++++
 3 files changed, 66 insertions(+), 12 deletions(-)

diff --git a/cpu/mpc8xxx/ddr/ctrl_regs.c b/cpu/mpc8xxx/ddr/ctrl_regs.c
index e6c2a5c..6297141 100644
--- a/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/cpu/mpc8xxx/ddr/ctrl_regs.c
@@ -95,16 +95,10 @@ static void set_csn_config(int i, fsl_ddr_cfg_regs_t *ddr,
 		col_bits_cs_n = dimm_params[i/2].n_col_addr - 8;
 	}
 
-	/* FIXME: intlv_en, intlv_ctl only on CS0_CONFIG */
-	if (i != 0) {
-		intlv_en = 0;
-		intlv_ctl = 0;
-	}
-
 	ddr->cs[i].config = (0
 		| ((cs_n_en & 0x1) << 31)
 		| ((intlv_en & 0x3) << 29)
-		| ((intlv_en & 0xf) << 24)
+		| ((intlv_ctl & 0xf) << 24)
 		| ((ap_n_en & 0x1) << 23)
 
 		/* XXX: some implementation only have 1 bit starting@left */
@@ -874,8 +868,13 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
 	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 		phys_size_t sa = 0;
 		phys_size_t ea = 0;
-		if (popts->ba_intlv_ctl && i > 0) {
-			/* Don't set up boundaries if bank interleaving */
+
+		if (popts->ba_intlv_ctl && (i > 0) &&
+			((popts->ba_intlv_ctl & 0x60) != FSL_DDR_CS2_CS3 )) {
+			/* Don't set up boundaries for other CS
+			 * other than CS0, if bank interleaving
+			 * is enabled and not CS2+CS3 interleaved.
+			 */
 			break;
 		}
 
@@ -894,7 +893,9 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
 			 * on each controller is twice the amount present on
 			 * each controller.
 			 */
-			ea = (2 * common_dimm->total_mem >> dbw_cap_adj) - 1;
+			unsigned long long rank_density
+					= dimm_params[0].capacity;
+			ea = (2 * (rank_density >> dbw_cap_adj)) - 1;
 		}
 		else if (!popts->memctl_interleaving && popts->ba_intlv_ctl) {
 			/*
@@ -906,8 +907,44 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
 			 * controller needs to be programmed into its
 			 * respective CS0_BNDS.
 			 */
-			sa = common_dimm->base_address;
-			ea = sa + (common_dimm->total_mem >> dbw_cap_adj) - 1;
+			unsigned long long rank_density
+						= dimm_params[i/2].rank_density;
+			switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
+			case FSL_DDR_CS0_CS1_CS2_CS3:
+				/* CS0+CS1+CS2+CS3 interleaving, only CS0_CNDS
+				 * needs to be set.
+				 */
+				sa = common_dimm->base_address;
+				ea = sa + (4 * (rank_density >> dbw_cap_adj))-1;
+				break;
+			case FSL_DDR_CS0_CS1_AND_CS2_CS3:
+				/* CS0+CS1 and CS2+CS3 interleaving, CS0_CNDS
+				 * and CS2_CNDS need to be set.
+				 */
+				if (!(i&1)) {
+					sa = dimm_params[i/2].base_address;
+					ea = sa + (i * (rank_density >>
+						dbw_cap_adj)) - 1;
+				}
+				break;
+			case FSL_DDR_CS0_CS1:
+				/* CS0+CS1 interleaving, CS0_CNDS needs
+				 * to be set
+				 */
+				sa = common_dimm->base_address;
+				ea = sa + (2 * (rank_density >> dbw_cap_adj))-1;
+				break;
+			case FSL_DDR_CS2_CS3:
+				/* CS2+CS3 interleaving*/
+				if (i == 2) {
+					sa = dimm_params[i/2].base_address;
+					ea = sa + (2 * (rank_density >>
+						dbw_cap_adj)) - 1;
+				}
+				break;
+			default:  /* No bank(chip-select) interleaving */
+				break;
+			}
 		}
 		else if (popts->memctl_interleaving && !popts->ba_intlv_ctl) {
 			/*
diff --git a/cpu/mpc8xxx/ddr/main.c b/cpu/mpc8xxx/ddr/main.c
index c340d56..d26c5c5 100644
--- a/cpu/mpc8xxx/ddr/main.c
+++ b/cpu/mpc8xxx/ddr/main.c
@@ -179,6 +179,7 @@ int step_assign_addresses(fsl_ddr_info_t *pinfo,
 
 	if (*memctl_interleaving) {
 		phys_addr_t addr;
+		phys_size_t total_mem_per_ctlr = 0;
 
 		/*
 		 * If interleaving between memory controllers,
@@ -197,14 +198,18 @@ int step_assign_addresses(fsl_ddr_info_t *pinfo,
 
 		for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 			addr = 0;
+			pinfo->common_timing_params[i].base_address =
+						(phys_addr_t)addr;
 			for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 				unsigned long long cap
 					= pinfo->dimm_params[i][j].capacity;
 
 				pinfo->dimm_params[i][j].base_address = addr;
 				addr += (phys_addr_t)(cap >> dbw_cap_adj[i]);
+				total_mem_per_ctlr += cap >> dbw_cap_adj[i];
 			}
 		}
+		pinfo->common_timing_params[0].total_mem = total_mem_per_ctlr;
 	} else {
 		/*
 		 * Simple linear assignment if memory
diff --git a/include/asm-ppc/fsl_ddr_sdram.h b/include/asm-ppc/fsl_ddr_sdram.h
index 8adde34..c1ea7cd 100644
--- a/include/asm-ppc/fsl_ddr_sdram.h
+++ b/include/asm-ppc/fsl_ddr_sdram.h
@@ -36,6 +36,18 @@ typedef ddr2_spd_eeprom_t generic_spd_eeprom_t;
 typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
 #endif
 
+/* define bank(chip select) interleaving mode */
+#define FSL_DDR_CS0_CS1			0x40
+#define FSL_DDR_CS2_CS3			0x20
+#define FSL_DDR_CS0_CS1_AND_CS2_CS3	(FSL_DDR_CS0_CS1 | FSL_DDR_CS2_CS3)
+#define FSL_DDR_CS0_CS1_CS2_CS3		(FSL_DDR_CS0_CS1_AND_CS2_CS3 | 0x04)
+
+/* define memory controller interleaving mode */
+#define FSL_DDR_CACHE_LINE_INTERLEAVING	0x0
+#define FSL_DDR_PAGE_INTERLEAVING	0x1
+#define FSL_DDR_BANK_INTERLEAVING	0x2
+#define FSL_DDR_SUPERBANK_INTERLEAVING	0x3
+
 /* Record of register values computed */
 typedef struct fsl_ddr_cfg_regs_s {
 	struct {
-- 
1.6.0.2