From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55603) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aQxrh-00007C-0m for qemu-devel@nongnu.org; Wed, 03 Feb 2016 08:53:06 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aQxrg-0006go-2K for qemu-devel@nongnu.org; Wed, 03 Feb 2016 08:53:00 -0500 From: Peter Maydell Date: Wed, 3 Feb 2016 13:38:37 +0000 Message-Id: <1454506721-11843-4-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1454506721-11843-1-git-send-email-peter.maydell@linaro.org> References: <1454506721-11843-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH 3/7] target-arm: Use access_trap_aa32s_el1() for SCR and MVBAR List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , qemu-arm@nongnu.org, patches@linaro.org The registers MVBAR and SCR should have the behaviour of trapping to EL3 if accessed from Secure EL1, but we were incorrectly implementing them to UNDEF (which would trap to EL1). Fix this by using the new access_trap_aa32s_el1() access function. Signed-off-by: Peter Maydell --- target-arm/helper.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 8b96b80..d85b04f 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -3547,7 +3547,8 @@ static const ARMCPRegInfo el3_cp_reginfo[] = { .resetvalue = 0, .writefn = scr_write }, { .name = "SCR", .type = ARM_CP_ALIAS, .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0, - .access = PL3_RW, .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3), + .access = PL1_RW, .accessfn = access_trap_aa32s_el1, + .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3), .writefn = scr_write }, { .name = "MDCR_EL3", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 3, .opc2 = 1, @@ -3569,7 +3570,8 @@ static const ARMCPRegInfo el3_cp_reginfo[] = { .access = PL3_W | PL1_R, .resetvalue = 0, .fieldoffset = offsetof(CPUARMState, cp15.nsacr) }, { .name = "MVBAR", .cp = 15, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1, - .access = PL3_RW, .writefn = vbar_write, .resetvalue = 0, + .access = PL1_RW, .accessfn = access_trap_aa32s_el1, + .writefn = vbar_write, .resetvalue = 0, .fieldoffset = offsetof(CPUARMState, cp15.mvbar) }, { .name = "SCTLR_EL3", .state = ARM_CP_STATE_AA64, .type = ARM_CP_ALIAS, /* reset handled by AArch32 view */ -- 1.9.1