From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40220) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aRhWH-00027Q-2n for qemu-devel@nongnu.org; Fri, 05 Feb 2016 09:37:58 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aRhWG-00065R-9E for qemu-devel@nongnu.org; Fri, 05 Feb 2016 09:37:57 -0500 From: Peter Maydell Date: Fri, 5 Feb 2016 14:37:46 +0000 Message-Id: <1454683067-16001-3-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1454683067-16001-1-git-send-email-peter.maydell@linaro.org> References: <1454683067-16001-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH 2/3] target-arm: Fix IL bit reported for Thumb coprocessor traps List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, patches@linaro.org All Thumb coprocessor instructions are 32 bits, so the IL bit in the syndrome register should be set. Pass false to the syn_* function's is_16bit argument rather than s->thumb so we report the correct IL bit. Signed-off-by: Peter Maydell --- target-arm/translate.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target-arm/translate.c b/target-arm/translate.c index 3ec758a..10792e8 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -7184,19 +7184,19 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn) case 14: if (is64) { syndrome = syn_cp14_rrt_trap(1, 0xe, opc1, crm, rt, rt2, - isread, s->thumb); + isread, false); } else { syndrome = syn_cp14_rt_trap(1, 0xe, opc1, opc2, crn, crm, - rt, isread, s->thumb); + rt, isread, false); } break; case 15: if (is64) { syndrome = syn_cp15_rrt_trap(1, 0xe, opc1, crm, rt, rt2, - isread, s->thumb); + isread, false); } else { syndrome = syn_cp15_rt_trap(1, 0xe, opc1, opc2, crn, crm, - rt, isread, s->thumb); + rt, isread, false); } break; default: -- 1.9.1