From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753487AbcBKDwH (ORCPT ); Wed, 10 Feb 2016 22:52:07 -0500 Received: from mail-bl2on0084.outbound.protection.outlook.com ([65.55.169.84]:61879 "EHLO na01-bl2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1753402AbcBKDwC (ORCPT ); Wed, 10 Feb 2016 22:52:02 -0500 Authentication-Results: lixom.net; dkim=none (message not signed) header.d=none;lixom.net; dmarc=none action=none header.from=amd.com; From: Suravee Suthikulpanit To: , , , , , , CC: , , , , , , , Suravee Suthikulpanit Subject: [PATCH V3 03/12] dtb: amd: Fix DMA ranges of smb0 and pcie0 Date: Wed, 10 Feb 2016 21:51:02 -0600 Message-ID: <1455162671-16044-4-git-send-email-Suravee.Suthikulpanit@amd.com> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1455162671-16044-1-git-send-email-Suravee.Suthikulpanit@amd.com> References: <1455162671-16044-1-git-send-email-Suravee.Suthikulpanit@amd.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [124.121.8.20] X-ClientProxiedBy: KL1PR02CA0013.apcprd02.prod.outlook.com (25.165.15.23) To BLUPR12MB0436.namprd12.prod.outlook.com (25.162.92.141) X-MS-Office365-Filtering-Correlation-Id: 53775658-71b3-4eff-254e-08d33296b095 X-Microsoft-Exchange-Diagnostics: 1;BLUPR12MB0436;2:n8Ulo1FhumKzWQgLZDzvFRXVHjg2UuRhHvj2B6rWfX22BskII1mSsi9XHNagUl1thZF0DuQc25opXWVg4OEzQo4HYRwybpiQeVNgOxEIQyAbm/BQGJquWeufi0Y1XetUTEp4Hy+2uPjtUvXLeGf3wLJoWMhQeifl1jCenSV4mb86MHmshOVUjDx1evUMZxL/;3:YIFUuIsgcg5RXE8hUW64O3LiaOqpBNZXzTgooJfvIM/SSsH4BCT0v/+gOCtjNwUIAoepbXSIa+Cgy5KNrk0VZKQ6bZmDpoJ+XxM4yn+GFS9OK6wpd9FQPuOTkSC5XdBf;25:AfhTYmhf4rSscbynTIinXwPXzcm0C7zohmRytuOANnDp+eCjEvjZj/XFoUwCj9DW9YkHsyOZTegs9MLSxin/ypj8N0MyV76aw/HniPsX7nDdE6NhYLDGiCdQHrxmpreFxOpdmW9v55x3UznfZU5e1mJOWFHaegBGYwTxdbZtlr2ptiZQaFcZt6doYJffU7SH/w/n3AO8As+DhSZok3S0DGreMjGqgFiMgmr3R5GSshyHsdHrQtZ1/LgHtLUWOMoRx3ZX+/Cpi0kmGkDlwmzjDQvz38/0dobGQrfSlYXQkcjdg4egtWlv9gzUNStYz9F2 X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:BLUPR12MB0436; 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Therefore, this patch fixes the smb0 and pcie0 dma-range properties. Signed-off-by: Suravee Suthikulpanit --- arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi b/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi index fdd0c96..5c73117 100644 --- a/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi +++ b/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi @@ -55,8 +55,12 @@ #size-cells = <2>; ranges; - /* DDR range is 40-bit addressing */ - dma-ranges = <0x80 0x0 0x80 0x0 0x7f 0xffffffff>; + /* + * dma-ranges is 40-bit address space containing: + * - GICv2m MSI register is at 0xe0080000 + * - DRAM range [0x8000000000 to 0xffffffffff] + */ + dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; /include/ "amd-seattle-clks.dtsi" @@ -159,7 +163,7 @@ <0x1000 0x0 0x0 0x4 &gic0 0x0 0x0 0x0 0x123 0x1>; dma-coherent; - dma-ranges = <0x43000000 0x80 0x0 0x80 0x0 0x7f 0xffffffff>; + dma-ranges = <0x43000000 0x0 0x0 0x0 0x0 0x100 0x0>; ranges = /* I/O Memory (size=64K) */ <0x01000000 0x00 0x00000000 0x00 0xefff0000 0x00 0x00010000>, -- 2.5.0 From mboxrd@z Thu Jan 1 00:00:00 1970 From: Suravee Suthikulpanit Subject: [PATCH V3 03/12] dtb: amd: Fix DMA ranges of smb0 and pcie0 Date: Wed, 10 Feb 2016 21:51:02 -0600 Message-ID: <1455162671-16044-4-git-send-email-Suravee.Suthikulpanit@amd.com> References: <1455162671-16044-1-git-send-email-Suravee.Suthikulpanit@amd.com> Mime-Version: 1.0 Content-Type: text/plain Return-path: In-Reply-To: <1455162671-16044-1-git-send-email-Suravee.Suthikulpanit@amd.com> Sender: linux-kernel-owner@vger.kernel.org To: olof@lixom.net, robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, arnd@arndb.de Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, arm@kernel.org, brijeshkumar.singh@amd.com, thomas.lendacky@amd.com, leo.duran@amd.com, Suravee Suthikulpanit List-Id: devicetree@vger.kernel.org From: Suravee Suthikulpanit Since GICv2m MSI frame is also considered DMA-able, we should also include this range in the dma-range DT property as well. Therefore, this patch fixes the smb0 and pcie0 dma-range properties. Signed-off-by: Suravee Suthikulpanit --- arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi b/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi index fdd0c96..5c73117 100644 --- a/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi +++ b/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi @@ -55,8 +55,12 @@ #size-cells = <2>; ranges; - /* DDR range is 40-bit addressing */ - dma-ranges = <0x80 0x0 0x80 0x0 0x7f 0xffffffff>; + /* + * dma-ranges is 40-bit address space containing: + * - GICv2m MSI register is at 0xe0080000 + * - DRAM range [0x8000000000 to 0xffffffffff] + */ + dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; /include/ "amd-seattle-clks.dtsi" @@ -159,7 +163,7 @@ <0x1000 0x0 0x0 0x4 &gic0 0x0 0x0 0x0 0x123 0x1>; dma-coherent; - dma-ranges = <0x43000000 0x80 0x0 0x80 0x0 0x7f 0xffffffff>; + dma-ranges = <0x43000000 0x0 0x0 0x0 0x0 0x100 0x0>; ranges = /* I/O Memory (size=64K) */ <0x01000000 0x00 0x00000000 0x00 0xefff0000 0x00 0x00010000>, -- 2.5.0 From mboxrd@z Thu Jan 1 00:00:00 1970 From: Suravee.Suthikulpanit@amd.com (Suravee Suthikulpanit) Date: Wed, 10 Feb 2016 21:51:02 -0600 Subject: [PATCH V3 03/12] dtb: amd: Fix DMA ranges of smb0 and pcie0 In-Reply-To: <1455162671-16044-1-git-send-email-Suravee.Suthikulpanit@amd.com> References: <1455162671-16044-1-git-send-email-Suravee.Suthikulpanit@amd.com> Message-ID: <1455162671-16044-4-git-send-email-Suravee.Suthikulpanit@amd.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org From: Suravee Suthikulpanit Since GICv2m MSI frame is also considered DMA-able, we should also include this range in the dma-range DT property as well. Therefore, this patch fixes the smb0 and pcie0 dma-range properties. Signed-off-by: Suravee Suthikulpanit --- arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi b/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi index fdd0c96..5c73117 100644 --- a/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi +++ b/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi @@ -55,8 +55,12 @@ #size-cells = <2>; ranges; - /* DDR range is 40-bit addressing */ - dma-ranges = <0x80 0x0 0x80 0x0 0x7f 0xffffffff>; + /* + * dma-ranges is 40-bit address space containing: + * - GICv2m MSI register is at 0xe0080000 + * - DRAM range [0x8000000000 to 0xffffffffff] + */ + dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; /include/ "amd-seattle-clks.dtsi" @@ -159,7 +163,7 @@ <0x1000 0x0 0x0 0x4 &gic0 0x0 0x0 0x0 0x123 0x1>; dma-coherent; - dma-ranges = <0x43000000 0x80 0x0 0x80 0x0 0x7f 0xffffffff>; + dma-ranges = <0x43000000 0x0 0x0 0x0 0x0 0x100 0x0>; ranges = /* I/O Memory (size=64K) */ <0x01000000 0x00 0x00000000 0x00 0xefff0000 0x00 0x00010000>, -- 2.5.0