[PATCH] drm/i915: Use SWF06 to figure out max cdclk for BDW

[ville.syrjala@linux.intel.com]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Bspec tells us that we can allow cdclk up to 540Mhz on BDW ULX, or
up to 675 MHz on ULT, bu only if extra cooling is provided. There
don't seem to be any strap or VBT bits to tells us this however.

But I did spot something potentially relevant in
VBIOS_GOP_Driver_SWF_Registers.pdf. Apparently VBIOS/GOP can pass
the max cdclk frequeny in SWF06 to the driver. Let's assume the firmware
knows what its doing and trust the max cdclk in SWF06 if it's higher
than the basic limit specified in Bspec. To avoid regressing anything
let's ignore SWF06 if it indicates a lower limit than Bspec.

Cc: Clint Taylor <clinton.a.taylor@intel.com>
Cc: "Thulasimani, Sivakumar" <sivakumar.thulasimani@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---

I'm not at all sure if this is the right way to go about it. Sivakumar,
since you seem to have some ideas on this maybe you can have a look.
I'm not aware of any complaints so far that people can't get the cdclk
as high is they should on specific machines, so not sure if this is really
even needed.

The other open question is what we should do if the VBIOS limit is
lower than what we'd expect based on BSpec. Should we still trust it?
Sadly we can't verify the SWF06 cdclk value in any way since it
only has two bits and we have four possible cdclk values.

 drivers/gpu/drm/i915/intel_display.c | 60 ++++++++++++++++++++++++++++--------
 1 file changed, 47 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 836bbdc239b6..1d70f6bf2934 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5407,21 +5407,55 @@ static void intel_update_max_cdclk(struct drm_device *dev)
 			dev_priv->max_cdclk_freq = 450000;
 		else
 			dev_priv->max_cdclk_freq = 337500;
-	} else if (IS_BROADWELL(dev))  {
+	} else if (IS_BROADWELL(dev)) {
+		int bios_max_cdclk_freq, max_cdclk_freq;
+
 		/*
-		 * FIXME with extra cooling we can allow
-		 * 540 MHz for ULX and 675 Mhz for ULT.
-		 * How can we know if extra cooling is
-		 * available? PCI ID, VTB, something else?
+		 * With extra cooling we can allow 540 MHz for
+		 * ULX and 675 Mhz for ULT. Assume VBIOS/GOP
+		 * passes that information in SWF06.
 		 */
-		if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
-			dev_priv->max_cdclk_freq = 450000;
-		else if (IS_BDW_ULX(dev))
-			dev_priv->max_cdclk_freq = 450000;
-		else if (IS_BDW_ULT(dev))
-			dev_priv->max_cdclk_freq = 540000;
-		else
-			dev_priv->max_cdclk_freq = 675000;
+		switch (I915_READ(SWF_ILK(0x06)) & 0x3) {
+		case 0:
+			bios_max_cdclk_freq = 450000;
+			break;
+		case 1:
+			bios_max_cdclk_freq = 540000;
+			break;
+		case 2:
+			bios_max_cdclk_freq = 337500;
+			break;
+		case 3:
+			bios_max_cdclk_freq = 675000;
+			break;
+		}
+
+		if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) {
+			if (WARN_ON(bios_max_cdclk_freq != 450000))
+				bios_max_cdclk_freq = 450000;
+			max_cdclk_freq = 450000;
+		} else if (IS_BDW_ULX(dev_priv)) {
+			if (WARN_ON(bios_max_cdclk_freq > 540000))
+				bios_max_cdclk_freq = 540000;
+			max_cdclk_freq = 450000;
+		} else if (IS_BDW_ULT(dev_priv)) {
+			max_cdclk_freq = 540000;
+		} else {
+			max_cdclk_freq = 675000;
+		}
+
+		if (bios_max_cdclk_freq > max_cdclk_freq) {
+			DRM_DEBUG_KMS("VBIOS/GOP max cdclk (%d kHz) higher than basic limit (%d kHz), "
+				      "assuming extra cooling is present\n",
+				      bios_max_cdclk_freq, max_cdclk_freq);
+			max_cdclk_freq = bios_max_cdclk_freq;
+		} else if (bios_max_cdclk_freq < max_cdclk_freq) {
+			DRM_DEBUG_KMS("VBIOS/GOP max cdclk (%d kHz) lower than basic limit (%d kHz), "
+				      "ignoring it\n",
+				      bios_max_cdclk_freq, max_cdclk_freq);
+		}
+
+		dev_priv->max_cdclk_freq = max_cdclk_freq;
 	} else if (IS_CHERRYVIEW(dev)) {
 		dev_priv->max_cdclk_freq = 320000;
 	} else if (IS_VALLEYVIEW(dev)) {
-- 
2.4.10

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