From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37147) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aYuge-0004YK-56 for qemu-devel@nongnu.org; Thu, 25 Feb 2016 07:06:28 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aYugc-0008DL-21 for qemu-devel@nongnu.org; Thu, 25 Feb 2016 07:06:28 -0500 Received: from mail.uni-paderborn.de ([131.234.142.9]:48290) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aYugb-0008Ac-Sa for qemu-devel@nongnu.org; Thu, 25 Feb 2016 07:06:25 -0500 From: Bastian Koppelmann Date: Thu, 25 Feb 2016 13:06:08 +0100 Message-Id: <1456401973-29673-2-git-send-email-kbastian@mail.uni-paderborn.de> In-Reply-To: <1456401973-29673-1-git-send-email-kbastian@mail.uni-paderborn.de> References: <1456401973-29673-1-git-send-email-kbastian@mail.uni-paderborn.de> Subject: [Qemu-devel] [PULL 1/6] target-tricore: fix save_context_upper using env->PSW List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org If the cached bits for C, V, SV, AV, or SAV were set, they would not be saved during the context save since env->PSW was stored instead of properly reading them using psw_read(). Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann --- target-tricore/op_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target-tricore/op_helper.c b/target-tricore/op_helper.c index 3aa6326..796fe67 100644 --- a/target-tricore/op_helper.c +++ b/target-tricore/op_helper.c @@ -2279,7 +2279,7 @@ static bool cdc_zero(target_ulong *psw) static void save_context_upper(CPUTriCoreState *env, int ea) { cpu_stl_data(env, ea, env->PCXI); - cpu_stl_data(env, ea+4, env->PSW); + cpu_stl_data(env, ea+4, psw_read(env)); cpu_stl_data(env, ea+8, env->gpr_a[10]); cpu_stl_data(env, ea+12, env->gpr_a[11]); cpu_stl_data(env, ea+16, env->gpr_d[8]); -- 2.7.1