From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39843) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1afVno-0008Sx-Qd for qemu-devel@nongnu.org; Mon, 14 Mar 2016 12:57:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1afVnl-0004tL-K5 for qemu-devel@nongnu.org; Mon, 14 Mar 2016 12:57:08 -0400 Received: from e06smtp08.uk.ibm.com ([195.75.94.104]:45994) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1afVnl-0004sm-AT for qemu-devel@nongnu.org; Mon, 14 Mar 2016 12:57:05 -0400 Received: from localhost by e06smtp08.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Mon, 14 Mar 2016 16:57:04 -0000 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Mon, 14 Mar 2016 17:56:23 +0100 Message-Id: <1457974600-13828-1-git-send-email-clg@fr.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [PATCH 00/17] ppc: preparing pnv landing List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: David Gibson Cc: Thomas Huth , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, qemu-devel@nongnu.org Hello, This is a first mini-serie of patches adding support for new ppc SPRs. They were taken from Ben's larger patchset adding the ppc powernv platform and they should already be useful for the pseries guest migration. Initial patches come from : https://github.com/ozbenh/qemu/commits/powernv The changes are mostly due to the rebase on Dave's 2.6 branch: https://github.com/dgibson/qemu/commits/ppc-for-2.6 A couple more are bisect and checkpatch fixes and finally some patches were merge to reduce the noise. The patchset is also available here: https://github.com/legoater/qemu/commits/for-2.6 It was quickly tested with a pseries guest using KVM and TCG. Thanks, C. Benjamin Herrenschmidt (17): ppc: Update SPR definitions ppc: Add macros to register hypervisor mode SPRs ppc: Add a bunch of hypervisor SPRs to Book3s ppc: Add number of threads per core to the processor definition ppc: Fix hreg_store_msr() so that non-HV mode cannot alter MSR:HV ppc: Create cpu_ppc_set_papr() helper ppc: Better figure out if processor has HV mode ppc: Add placeholder SPRs for DPDES and DHDES on P8 ppc: SPURR & PURR are HV writeable and privileged ppc: Add dummy SPR_IC for POWER8 ppc: Initialize AMOR in PAPR mode ppc: Fix writing to AMR/UAMOR ppc: Add POWER8 IAMR register ppc: Add dummy write to VTB ppc: Add dummy POWER8 MPPR register ppc: Add dummy CIABR SPR ppc: A couple more dummy POWER8 Book4 regs hw/ppc/spapr.c | 11 +- target-ppc/cpu-qom.h | 1 + target-ppc/cpu.h | 68 ++++++- target-ppc/excp_helper.c | 8 +- target-ppc/helper_regs.h | 4 +- target-ppc/translate.c | 30 +-- target-ppc/translate_init.c | 461 ++++++++++++++++++++++++++++++++++++++++---- 7 files changed, 510 insertions(+), 73 deletions(-) -- 2.1.4