From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43885) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1afVxo-0000cJ-CV for qemu-devel@nongnu.org; Mon, 14 Mar 2016 13:07:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1afVxj-0008RP-Cc for qemu-devel@nongnu.org; Mon, 14 Mar 2016 13:07:28 -0400 Received: from e06smtp10.uk.ibm.com ([195.75.94.106]:58688) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1afVxj-0008QX-1a for qemu-devel@nongnu.org; Mon, 14 Mar 2016 13:07:23 -0400 Received: from localhost by e06smtp10.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Mon, 14 Mar 2016 16:57:08 -0000 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Mon, 14 Mar 2016 17:56:27 +0100 Message-Id: <1457974600-13828-5-git-send-email-clg@fr.ibm.com> In-Reply-To: <1457974600-13828-1-git-send-email-clg@fr.ibm.com> References: <1457974600-13828-1-git-send-email-clg@fr.ibm.com> Subject: [Qemu-devel] [PATCH 04/17] ppc: Add number of threads per core to the processor definition List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: David Gibson Cc: Thomas Huth , qemu-ppc@nongnu.org, qemu-devel@nongnu.org From: Benjamin Herrenschmidt Also use it to clamp the max SMT mode and ensure that the cpu_dt_id are offset by that value in order to preserve consistency with the HW implementations. Signed-off-by: Benjamin Herrenschmidt --- target-ppc/cpu-qom.h | 1 + target-ppc/translate_init.c | 11 ++++++++++- 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/target-ppc/cpu-qom.h b/target-ppc/cpu-qom.h index 7d5e2b36a997..735981309c5b 100644 --- a/target-ppc/cpu-qom.h +++ b/target-ppc/cpu-qom.h @@ -68,6 +68,7 @@ typedef struct PowerPCCPUClass { uint32_t flags; int bfd_mach; uint32_t l1_dcache_size, l1_icache_size; + uint32_t threads_per_core; #if defined(TARGET_PPC64) const struct ppc_segment_page_sizes *sps; #endif diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index 43c6e524a6bc..46dabe58783a 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -8231,6 +8231,7 @@ POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data) POWERPC_FLAG_BUS_CLK; pcc->l1_dcache_size = 0x8000; pcc->l1_icache_size = 0x10000; + pcc->threads_per_core = 2; } static void powerpc_get_compat(Object *obj, Visitor *v, const char *name, @@ -8408,6 +8409,7 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) pcc->l1_dcache_size = 0x8000; pcc->l1_icache_size = 0x8000; pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr; + pcc->threads_per_core = 4; } static void init_proc_POWER8(CPUPPCState *env) @@ -8492,6 +8494,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) pcc->l1_dcache_size = 0x8000; pcc->l1_icache_size = 0x8000; pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr; + pcc->threads_per_core = 8; } #endif /* defined (TARGET_PPC64) */ @@ -9195,6 +9198,12 @@ static void ppc_cpu_realizefn(DeviceState *dev, Error **errp) #endif #if !defined(CONFIG_USER_ONLY) + if (pcc->threads_per_core == 0) { + pcc->threads_per_core = 1; + } + if (max_smt > pcc->threads_per_core) { + max_smt = pcc->threads_per_core; + } if (smp_threads > max_smt) { error_setg(errp, "Cannot support more than %d threads on PPC with %s", max_smt, kvm_enabled() ? "KVM" : "TCG"); @@ -9215,7 +9224,7 @@ static void ppc_cpu_realizefn(DeviceState *dev, Error **errp) } #if !defined(CONFIG_USER_ONLY) - cpu->cpu_dt_id = (cs->cpu_index / smp_threads) * max_smt + cpu->cpu_dt_id = (cs->cpu_index / smp_threads) * pcc->threads_per_core + (cs->cpu_index % smp_threads); #endif -- 2.1.4