From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39898) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1afVnq-0008TM-Oj for qemu-devel@nongnu.org; Mon, 14 Mar 2016 12:57:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1afVnp-0004vR-Ix for qemu-devel@nongnu.org; Mon, 14 Mar 2016 12:57:10 -0400 Received: from e06smtp08.uk.ibm.com ([195.75.94.104]:46021) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1afVnp-0004v3-Ad for qemu-devel@nongnu.org; Mon, 14 Mar 2016 12:57:09 -0400 Received: from localhost by e06smtp08.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Mon, 14 Mar 2016 16:57:08 -0000 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Mon, 14 Mar 2016 17:56:30 +0100 Message-Id: <1457974600-13828-8-git-send-email-clg@fr.ibm.com> In-Reply-To: <1457974600-13828-1-git-send-email-clg@fr.ibm.com> References: <1457974600-13828-1-git-send-email-clg@fr.ibm.com> Subject: [Qemu-devel] [PATCH 07/17] ppc: Better figure out if processor has HV mode List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: David Gibson Cc: Thomas Huth , qemu-ppc@nongnu.org, qemu-devel@nongnu.org From: Benjamin Herrenschmidt We use an env. flag which is set to the initial value of MSR_HVB in the msr_mask. We also adjust the POWER8 mask to set SHV. Also use this to adjust ctx.hv so that it is *set* when the processor doesn't have an HV mode (970 with Apple mode for example), thus enabling hypervisor instructions/SPRs. Signed-off-by: Benjamin Herrenschmidt Reviewed-by: David Gibson --- target-ppc/cpu.h | 4 ++++ target-ppc/translate.c | 4 +++- target-ppc/translate_init.c | 19 +++++++++++++++---- 3 files changed, 22 insertions(+), 5 deletions(-) diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index a7da0d3e95a9..02aed6427ade 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -1153,6 +1153,10 @@ struct CPUPPCState { hwaddr mpic_iack; /* true when the external proxy facility mode is enabled */ bool mpic_proxy; + /* set when the processor has an HV mode, thus HV priv + * instructions and SPRs are diallowed if MSR:HV is 0 + */ + bool has_hv_mode; #endif /* Those resources are used only during code translation */ diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 327f3259b4be..11801ded62d2 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -11456,8 +11456,10 @@ void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb) ctx.exception = POWERPC_EXCP_NONE; ctx.spr_cb = env->spr_cb; ctx.pr = msr_pr; - ctx.hv = !msr_pr && msr_hv; ctx.mem_idx = env->mmu_idx; +#if !defined(CONFIG_USER_ONLY) + ctx.hv = msr_hv || !env->has_hv_mode; +#endif ctx.insns_flags = env->insns_flags; ctx.insns_flags2 = env->insns_flags2; ctx.access_type = -1; diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index 093ef036320d..59a68de0bce8 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -8463,6 +8463,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | PPC2_TM; pcc->msr_mask = (1ull << MSR_SF) | + (1ull << MSR_SHV) | (1ull << MSR_TM) | (1ull << MSR_VR) | (1ull << MSR_VSX) | @@ -9876,10 +9877,7 @@ static void ppc_cpu_reset(CPUState *s) pcc->parent_reset(s); msr = (target_ulong)0; - if (0) { - /* XXX: find a suitable condition to enable the hypervisor mode */ - msr |= (target_ulong)MSR_HVB; - } + msr |= (target_ulong)MSR_HVB; msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */ msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */ msr |= (target_ulong)1 << MSR_EP; @@ -9980,6 +9978,19 @@ static void ppc_cpu_initfn(Object *obj) env->bfd_mach = pcc->bfd_mach; env->check_pow = pcc->check_pow; + /* Mark HV mode as supported if the CPU has an MSR_HV bit + * in the msr_mask. The mask can later be cleared by PAPR + * mode but the hv mode support will remain, thus enforcing + * that we cannot use priv. instructions in guest in PAPR + * mode. For 970 we currently simply don't set HV in msr_mask + * thus simulating an "Apple mode" 970. If we ever want to + * support 970 HV mode, we'll have to add a processor attribute + * of some sort. + */ +#if !defined(CONFIG_USER_ONLY) + env->has_hv_mode = !!(env->msr_mask & MSR_HVB); +#endif + #if defined(TARGET_PPC64) if (pcc->sps) { env->sps = *pcc->sps; -- 2.1.4