From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57180) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1afwGa-0000Fy-Ix for qemu-devel@nongnu.org; Tue, 15 Mar 2016 17:12:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1afwGX-0000T1-B9 for qemu-devel@nongnu.org; Tue, 15 Mar 2016 17:12:36 -0400 Message-ID: <1458076308.3107.46.camel@kernel.crashing.org> From: Benjamin Herrenschmidt Date: Wed, 16 Mar 2016 08:11:48 +1100 In-Reply-To: <20160315094545.GD9032@voom> References: <1457974600-13828-1-git-send-email-clg@fr.ibm.com> <1457974600-13828-5-git-send-email-clg@fr.ibm.com> <20160315094545.GD9032@voom> Content-Type: text/plain; charset="UTF-8" Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH 04/17] ppc: Add number of threads per core to the processor definition List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: David Gibson , =?ISO-8859-1?Q?C=E9dric?= Le Goater Cc: Thomas Huth , qemu-ppc@nongnu.org, qemu-devel@nongnu.org On Tue, 2016-03-15 at 20:45 +1100, David Gibson wrote: > On Mon, Mar 14, 2016 at 05:56:27PM +0100, C=C3=A9dric Le Goater wrote: > >=20 > > From: Benjamin Herrenschmidt > >=20 > > Also use it to clamp the max SMT mode and ensure that the cpu_dt_id > > are offset by that value in order to preserve consistency with the > > HW implementations. > I think this can change change CPU ids, and therefore break migration > on some existing setups.=C2=A0=C2=A0So it will need some rework to appl= y at > all, and will certainly want to wait until after 2.6 Our migration is so bloody damn fragile ... grrr. We will need it for powernv though, there are many things especially in OPAL that rely on the consistent numbering. In fact, it will have to go further and number the cores based on their equivalent HW numbers at some point for SCOMs to work, which means a slightly discontiguous numbering scheme (no core 0 for example). At least if we want to model some of the EX XSCOMs. Cheers, Ben. > >=20 > >=20 > > Signed-off-by: Benjamin Herrenschmidt > > --- > > =C2=A0target-ppc/cpu-qom.h=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0|=C2=A0=C2=A01 + > > =C2=A0target-ppc/translate_init.c | 11 ++++++++++- > > =C2=A02 files changed, 11 insertions(+), 1 deletion(-) > >=20 > > diff --git a/target-ppc/cpu-qom.h b/target-ppc/cpu-qom.h > > index 7d5e2b36a997..735981309c5b 100644 > > --- a/target-ppc/cpu-qom.h > > +++ b/target-ppc/cpu-qom.h > > @@ -68,6 +68,7 @@ typedef struct PowerPCCPUClass { > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0uint32_t flags; > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0int bfd_mach; > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0uint32_t l1_dcache_size, l1_icache_size= ; > > +=C2=A0=C2=A0=C2=A0=C2=A0uint32_t threads_per_core; > > =C2=A0#if defined(TARGET_PPC64) > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0const struct ppc_segment_page_sizes *sp= s; > > =C2=A0#endif > > diff --git a/target-ppc/translate_init.c b/target- > > ppc/translate_init.c > > index 43c6e524a6bc..46dabe58783a 100644 > > --- a/target-ppc/translate_init.c > > +++ b/target-ppc/translate_init.c > > @@ -8231,6 +8231,7 @@ POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void > > *data) > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0POWERPC_FLAG_BUS_CLK; > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0pcc->l1_dcache_size =3D 0x8000; > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0pcc->l1_icache_size =3D 0x10000; > > +=C2=A0=C2=A0=C2=A0=C2=A0pcc->threads_per_core =3D 2; > > =C2=A0} > > =C2=A0 > > =C2=A0static void powerpc_get_compat(Object *obj, Visitor *v, const c= har > > *name, > > @@ -8408,6 +8409,7 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void > > *data) > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0pcc->l1_dcache_size =3D 0x8000; > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0pcc->l1_icache_size =3D 0x8000; > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0pcc->interrupts_big_endian =3D > > ppc_cpu_interrupts_big_endian_lpcr; > > +=C2=A0=C2=A0=C2=A0=C2=A0pcc->threads_per_core =3D 4; > > =C2=A0} > > =C2=A0 > > =C2=A0static void init_proc_POWER8(CPUPPCState *env) > > @@ -8492,6 +8494,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void > > *data) > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0pcc->l1_dcache_size =3D 0x8000; > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0pcc->l1_icache_size =3D 0x8000; > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0pcc->interrupts_big_endian =3D > > ppc_cpu_interrupts_big_endian_lpcr; > > +=C2=A0=C2=A0=C2=A0=C2=A0pcc->threads_per_core =3D 8; > > =C2=A0} > > =C2=A0#endif /* defined (TARGET_PPC64) */ > > =C2=A0 > > @@ -9195,6 +9198,12 @@ static void ppc_cpu_realizefn(DeviceState > > *dev, Error **errp) > > =C2=A0#endif > > =C2=A0 > > =C2=A0#if !defined(CONFIG_USER_ONLY) > > +=C2=A0=C2=A0=C2=A0=C2=A0if (pcc->threads_per_core =3D=3D 0) { > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0pcc->threads_per_cor= e =3D 1; > > +=C2=A0=C2=A0=C2=A0=C2=A0} > > +=C2=A0=C2=A0=C2=A0=C2=A0if (max_smt > pcc->threads_per_core) { > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0max_smt =3D pcc->thr= eads_per_core; > > +=C2=A0=C2=A0=C2=A0=C2=A0} > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0if (smp_threads > max_smt) { > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0error_setg(errp= , "Cannot support more than %d threads on > > PPC with %s", > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0max_smt, kvm_enabled()= ? "KVM" : "TCG"); > > @@ -9215,7 +9224,7 @@ static void ppc_cpu_realizefn(DeviceState > > *dev, Error **errp) > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0} > > =C2=A0 > > =C2=A0#if !defined(CONFIG_USER_ONLY) > > -=C2=A0=C2=A0=C2=A0=C2=A0cpu->cpu_dt_id =3D (cs->cpu_index / smp_thre= ads) * max_smt > > +=C2=A0=C2=A0=C2=A0=C2=A0cpu->cpu_dt_id =3D (cs->cpu_index / smp_thre= ads) * pcc- > > >threads_per_core > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0+ (cs->cpu_inde= x % smp_threads); > > =C2=A0#endif > > =C2=A0