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* [PATCH 0/3] ARM: AMx3xx: misc clock fixes
@ 2016-03-16 19:54 ` Tero Kristo
  0 siblings, 0 replies; 35+ messages in thread
From: Tero Kristo @ 2016-03-16 19:54 UTC (permalink / raw)
  To: linux-omap, linux-clk, mturquette, sboyd, tony; +Cc: linux-arm-kernel

Hi,

These patches add DPLL max rate support on AMx3xx SoCs, and add
support for clkout1 clock on AM43xx. Targeted for 4.7 merge window.

-Tero

^ permalink raw reply	[flat|nested] 35+ messages in thread

* [PATCH 0/3] ARM: AMx3xx: misc clock fixes
@ 2016-03-16 19:54 ` Tero Kristo
  0 siblings, 0 replies; 35+ messages in thread
From: Tero Kristo @ 2016-03-16 19:54 UTC (permalink / raw)
  To: linux-omap, linux-clk, mturquette, sboyd, tony; +Cc: linux-arm-kernel

Hi,

These patches add DPLL max rate support on AMx3xx SoCs, and add
support for clkout1 clock on AM43xx. Targeted for 4.7 merge window.

-Tero


^ permalink raw reply	[flat|nested] 35+ messages in thread

* [PATCH 0/3] ARM: AMx3xx: misc clock fixes
@ 2016-03-16 19:54 ` Tero Kristo
  0 siblings, 0 replies; 35+ messages in thread
From: Tero Kristo @ 2016-03-16 19:54 UTC (permalink / raw)
  To: linux-arm-kernel

Hi,

These patches add DPLL max rate support on AMx3xx SoCs, and add
support for clkout1 clock on AM43xx. Targeted for 4.7 merge window.

-Tero

^ permalink raw reply	[flat|nested] 35+ messages in thread

* [PATCH 1/3] clk: ti: dpll: add support for specifying max rate for DPLLs
  2016-03-16 19:54 ` Tero Kristo
  (?)
@ 2016-03-16 19:54   ` Tero Kristo
  -1 siblings, 0 replies; 35+ messages in thread
From: Tero Kristo @ 2016-03-16 19:54 UTC (permalink / raw)
  To: linux-omap, linux-clk, mturquette, sboyd, tony
  Cc: linux-arm-kernel, Nishanth Menon, Tomi Valkeinen, Lokesh Vutla

DPLLs typically have a maximum rate they can support, and this varies
from DPLL to DPLL. Add support of the maximum rate value to the DPLL
data struct, and also add check for this in the DPLL round_rate function.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Cc: Nishanth Menon <nm@ti.com>
Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
---
 drivers/clk/ti/clkt_dpll.c |    3 +++
 include/linux/clk/ti.h     |    2 ++
 2 files changed, 5 insertions(+)

diff --git a/drivers/clk/ti/clkt_dpll.c b/drivers/clk/ti/clkt_dpll.c
index b5cc6f6..7d97b07 100644
--- a/drivers/clk/ti/clkt_dpll.c
+++ b/drivers/clk/ti/clkt_dpll.c
@@ -301,6 +301,9 @@ long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
 
 	dd = clk->dpll_data;
 
+	if (dd->max_rate && target_rate > dd->max_rate)
+		target_rate = dd->max_rate;
+
 	ref_rate = clk_get_rate(dd->clk_ref);
 	clk_name = clk_hw_get_name(hw);
 	pr_debug("clock: %s: starting DPLL round_rate, target rate %lu\n",
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index 9a63860..1a48ee2 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -37,6 +37,7 @@
  * @last_rounded_n: cache of the last N result of omap2_dpll_round_rate()
  * @min_divider: minimum valid non-bypass divider value (actual)
  * @max_divider: maximum valid non-bypass divider value (actual)
+ * @max_rate: maximum clock rate for the DPLL
  * @modes: possible values of @enable_mask
  * @autoidle_reg: register containing the DPLL autoidle mode bitfield
  * @idlest_reg: register containing the DPLL idle status bitfield
@@ -81,6 +82,7 @@ struct dpll_data {
 	u8			last_rounded_n;
 	u8			min_divider;
 	u16			max_divider;
+	unsigned long		max_rate;
 	u8			modes;
 	void __iomem		*autoidle_reg;
 	void __iomem		*idlest_reg;
-- 
1.7.9.5

^ permalink raw reply related	[flat|nested] 35+ messages in thread

* [PATCH 1/3] clk: ti: dpll: add support for specifying max rate for DPLLs
@ 2016-03-16 19:54   ` Tero Kristo
  0 siblings, 0 replies; 35+ messages in thread
From: Tero Kristo @ 2016-03-16 19:54 UTC (permalink / raw)
  To: linux-omap, linux-clk, mturquette, sboyd, tony
  Cc: linux-arm-kernel, Nishanth Menon, Tomi Valkeinen, Lokesh Vutla

DPLLs typically have a maximum rate they can support, and this varies
from DPLL to DPLL. Add support of the maximum rate value to the DPLL
data struct, and also add check for this in the DPLL round_rate function.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Cc: Nishanth Menon <nm@ti.com>
Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
---
 drivers/clk/ti/clkt_dpll.c |    3 +++
 include/linux/clk/ti.h     |    2 ++
 2 files changed, 5 insertions(+)

diff --git a/drivers/clk/ti/clkt_dpll.c b/drivers/clk/ti/clkt_dpll.c
index b5cc6f6..7d97b07 100644
--- a/drivers/clk/ti/clkt_dpll.c
+++ b/drivers/clk/ti/clkt_dpll.c
@@ -301,6 +301,9 @@ long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
 
 	dd = clk->dpll_data;
 
+	if (dd->max_rate && target_rate > dd->max_rate)
+		target_rate = dd->max_rate;
+
 	ref_rate = clk_get_rate(dd->clk_ref);
 	clk_name = clk_hw_get_name(hw);
 	pr_debug("clock: %s: starting DPLL round_rate, target rate %lu\n",
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index 9a63860..1a48ee2 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -37,6 +37,7 @@
  * @last_rounded_n: cache of the last N result of omap2_dpll_round_rate()
  * @min_divider: minimum valid non-bypass divider value (actual)
  * @max_divider: maximum valid non-bypass divider value (actual)
+ * @max_rate: maximum clock rate for the DPLL
  * @modes: possible values of @enable_mask
  * @autoidle_reg: register containing the DPLL autoidle mode bitfield
  * @idlest_reg: register containing the DPLL idle status bitfield
@@ -81,6 +82,7 @@ struct dpll_data {
 	u8			last_rounded_n;
 	u8			min_divider;
 	u16			max_divider;
+	unsigned long		max_rate;
 	u8			modes;
 	void __iomem		*autoidle_reg;
 	void __iomem		*idlest_reg;
-- 
1.7.9.5


^ permalink raw reply related	[flat|nested] 35+ messages in thread

* [PATCH 1/3] clk: ti: dpll: add support for specifying max rate for DPLLs
@ 2016-03-16 19:54   ` Tero Kristo
  0 siblings, 0 replies; 35+ messages in thread
From: Tero Kristo @ 2016-03-16 19:54 UTC (permalink / raw)
  To: linux-arm-kernel

DPLLs typically have a maximum rate they can support, and this varies
from DPLL to DPLL. Add support of the maximum rate value to the DPLL
data struct, and also add check for this in the DPLL round_rate function.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Cc: Nishanth Menon <nm@ti.com>
Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
---
 drivers/clk/ti/clkt_dpll.c |    3 +++
 include/linux/clk/ti.h     |    2 ++
 2 files changed, 5 insertions(+)

diff --git a/drivers/clk/ti/clkt_dpll.c b/drivers/clk/ti/clkt_dpll.c
index b5cc6f6..7d97b07 100644
--- a/drivers/clk/ti/clkt_dpll.c
+++ b/drivers/clk/ti/clkt_dpll.c
@@ -301,6 +301,9 @@ long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
 
 	dd = clk->dpll_data;
 
+	if (dd->max_rate && target_rate > dd->max_rate)
+		target_rate = dd->max_rate;
+
 	ref_rate = clk_get_rate(dd->clk_ref);
 	clk_name = clk_hw_get_name(hw);
 	pr_debug("clock: %s: starting DPLL round_rate, target rate %lu\n",
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index 9a63860..1a48ee2 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -37,6 +37,7 @@
  * @last_rounded_n: cache of the last N result of omap2_dpll_round_rate()
  * @min_divider: minimum valid non-bypass divider value (actual)
  * @max_divider: maximum valid non-bypass divider value (actual)
+ * @max_rate: maximum clock rate for the DPLL
  * @modes: possible values of @enable_mask
  * @autoidle_reg: register containing the DPLL autoidle mode bitfield
  * @idlest_reg: register containing the DPLL idle status bitfield
@@ -81,6 +82,7 @@ struct dpll_data {
 	u8			last_rounded_n;
 	u8			min_divider;
 	u16			max_divider;
+	unsigned long		max_rate;
 	u8			modes;
 	void __iomem		*autoidle_reg;
 	void __iomem		*idlest_reg;
-- 
1.7.9.5

^ permalink raw reply related	[flat|nested] 35+ messages in thread

* [PATCH 2/3] clk: ti: amx3xx: limit the maximum frequency of DPLLs based on spec
  2016-03-16 19:54 ` Tero Kristo
  (?)
@ 2016-03-16 19:54   ` Tero Kristo
  -1 siblings, 0 replies; 35+ messages in thread
From: Tero Kristo @ 2016-03-16 19:54 UTC (permalink / raw)
  To: linux-omap, linux-clk, mturquette, sboyd, tony
  Cc: linux-arm-kernel, Nishanth Menon, Tomi Valkeinen, Lokesh Vutla

AM33xx/AM43xx devices use the same DPLL IP blocks, which only support
maximum rate of 1GHz [1] for the default and 2GHz for the low-jitter type
DPLLs [2]. Reflect this limitation in the DPLL init code by adding the
max-rate parameter based on the DPLL types.

[1] Functional, integration & test specification for GS70 ADPLLS, Rev 1.0-01
[2] Functional, integration & test specification for GS70 ADPLLLJ, Rev 0.8-02

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Cc: Nishanth Menon <nm@ti.com>
Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
---
 drivers/clk/ti/dpll.c |    5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/clk/ti/dpll.c b/drivers/clk/ti/dpll.c
index 5519b38..4caadb9 100644
--- a/drivers/clk/ti/dpll.c
+++ b/drivers/clk/ti/dpll.c
@@ -642,6 +642,7 @@ static void __init of_ti_am3_no_gate_dpll_setup(struct device_node *node)
 		.max_multiplier = 2047,
 		.max_divider = 128,
 		.min_divider = 1,
+		.max_rate = 1000000000,
 		.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 	};
 
@@ -661,6 +662,7 @@ static void __init of_ti_am3_jtype_dpll_setup(struct device_node *node)
 		.max_divider = 256,
 		.min_divider = 2,
 		.flags = DPLL_J_TYPE,
+		.max_rate = 2000000000,
 		.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 	};
 
@@ -679,6 +681,7 @@ static void __init of_ti_am3_no_gate_jtype_dpll_setup(struct device_node *node)
 		.max_multiplier = 2047,
 		.max_divider = 128,
 		.min_divider = 1,
+		.max_rate = 2000000000,
 		.flags = DPLL_J_TYPE,
 		.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 	};
@@ -699,6 +702,7 @@ static void __init of_ti_am3_dpll_setup(struct device_node *node)
 		.max_multiplier = 2047,
 		.max_divider = 128,
 		.min_divider = 1,
+		.max_rate = 1000000000,
 		.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 	};
 
@@ -716,6 +720,7 @@ static void __init of_ti_am3_core_dpll_setup(struct device_node *node)
 		.max_multiplier = 2047,
 		.max_divider = 128,
 		.min_divider = 1,
+		.max_rate = 1000000000,
 		.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 	};
 
-- 
1.7.9.5

^ permalink raw reply related	[flat|nested] 35+ messages in thread

* [PATCH 2/3] clk: ti: amx3xx: limit the maximum frequency of DPLLs based on spec
@ 2016-03-16 19:54   ` Tero Kristo
  0 siblings, 0 replies; 35+ messages in thread
From: Tero Kristo @ 2016-03-16 19:54 UTC (permalink / raw)
  To: linux-omap, linux-clk, mturquette, sboyd, tony
  Cc: linux-arm-kernel, Nishanth Menon, Tomi Valkeinen, Lokesh Vutla

AM33xx/AM43xx devices use the same DPLL IP blocks, which only support
maximum rate of 1GHz [1] for the default and 2GHz for the low-jitter type
DPLLs [2]. Reflect this limitation in the DPLL init code by adding the
max-rate parameter based on the DPLL types.

[1] Functional, integration & test specification for GS70 ADPLLS, Rev 1.0-01
[2] Functional, integration & test specification for GS70 ADPLLLJ, Rev 0.8-02

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Cc: Nishanth Menon <nm@ti.com>
Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
---
 drivers/clk/ti/dpll.c |    5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/clk/ti/dpll.c b/drivers/clk/ti/dpll.c
index 5519b38..4caadb9 100644
--- a/drivers/clk/ti/dpll.c
+++ b/drivers/clk/ti/dpll.c
@@ -642,6 +642,7 @@ static void __init of_ti_am3_no_gate_dpll_setup(struct device_node *node)
 		.max_multiplier = 2047,
 		.max_divider = 128,
 		.min_divider = 1,
+		.max_rate = 1000000000,
 		.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 	};
 
@@ -661,6 +662,7 @@ static void __init of_ti_am3_jtype_dpll_setup(struct device_node *node)
 		.max_divider = 256,
 		.min_divider = 2,
 		.flags = DPLL_J_TYPE,
+		.max_rate = 2000000000,
 		.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 	};
 
@@ -679,6 +681,7 @@ static void __init of_ti_am3_no_gate_jtype_dpll_setup(struct device_node *node)
 		.max_multiplier = 2047,
 		.max_divider = 128,
 		.min_divider = 1,
+		.max_rate = 2000000000,
 		.flags = DPLL_J_TYPE,
 		.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 	};
@@ -699,6 +702,7 @@ static void __init of_ti_am3_dpll_setup(struct device_node *node)
 		.max_multiplier = 2047,
 		.max_divider = 128,
 		.min_divider = 1,
+		.max_rate = 1000000000,
 		.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 	};
 
@@ -716,6 +720,7 @@ static void __init of_ti_am3_core_dpll_setup(struct device_node *node)
 		.max_multiplier = 2047,
 		.max_divider = 128,
 		.min_divider = 1,
+		.max_rate = 1000000000,
 		.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 	};
 
-- 
1.7.9.5


^ permalink raw reply related	[flat|nested] 35+ messages in thread

* [PATCH 2/3] clk: ti: amx3xx: limit the maximum frequency of DPLLs based on spec
@ 2016-03-16 19:54   ` Tero Kristo
  0 siblings, 0 replies; 35+ messages in thread
From: Tero Kristo @ 2016-03-16 19:54 UTC (permalink / raw)
  To: linux-arm-kernel

AM33xx/AM43xx devices use the same DPLL IP blocks, which only support
maximum rate of 1GHz [1] for the default and 2GHz for the low-jitter type
DPLLs [2]. Reflect this limitation in the DPLL init code by adding the
max-rate parameter based on the DPLL types.

[1] Functional, integration & test specification for GS70 ADPLLS, Rev 1.0-01
[2] Functional, integration & test specification for GS70 ADPLLLJ, Rev 0.8-02

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Cc: Nishanth Menon <nm@ti.com>
Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
---
 drivers/clk/ti/dpll.c |    5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/clk/ti/dpll.c b/drivers/clk/ti/dpll.c
index 5519b38..4caadb9 100644
--- a/drivers/clk/ti/dpll.c
+++ b/drivers/clk/ti/dpll.c
@@ -642,6 +642,7 @@ static void __init of_ti_am3_no_gate_dpll_setup(struct device_node *node)
 		.max_multiplier = 2047,
 		.max_divider = 128,
 		.min_divider = 1,
+		.max_rate = 1000000000,
 		.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 	};
 
@@ -661,6 +662,7 @@ static void __init of_ti_am3_jtype_dpll_setup(struct device_node *node)
 		.max_divider = 256,
 		.min_divider = 2,
 		.flags = DPLL_J_TYPE,
+		.max_rate = 2000000000,
 		.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 	};
 
@@ -679,6 +681,7 @@ static void __init of_ti_am3_no_gate_jtype_dpll_setup(struct device_node *node)
 		.max_multiplier = 2047,
 		.max_divider = 128,
 		.min_divider = 1,
+		.max_rate = 2000000000,
 		.flags = DPLL_J_TYPE,
 		.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 	};
@@ -699,6 +702,7 @@ static void __init of_ti_am3_dpll_setup(struct device_node *node)
 		.max_multiplier = 2047,
 		.max_divider = 128,
 		.min_divider = 1,
+		.max_rate = 1000000000,
 		.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 	};
 
@@ -716,6 +720,7 @@ static void __init of_ti_am3_core_dpll_setup(struct device_node *node)
 		.max_multiplier = 2047,
 		.max_divider = 128,
 		.min_divider = 1,
+		.max_rate = 1000000000,
 		.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 	};
 
-- 
1.7.9.5

^ permalink raw reply related	[flat|nested] 35+ messages in thread

* [PATCH 3/3] ARM: dts: am43xx: add support for clkout1 clock
  2016-03-16 19:54 ` Tero Kristo
  (?)
@ 2016-03-16 19:54   ` Tero Kristo
  -1 siblings, 0 replies; 35+ messages in thread
From: Tero Kristo @ 2016-03-16 19:54 UTC (permalink / raw)
  To: linux-omap, linux-clk, mturquette, sboyd, tony; +Cc: linux-arm-kernel

clkout1 clock node and its generation tree was missing. Add this based
on the data on TRM and PRCM functional spec.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Tested-by: Benoit Parrot <bparrot@ti.com>
---
 arch/arm/boot/dts/am43xx-clocks.dtsi |   54 ++++++++++++++++++++++++++++++++++
 1 file changed, 54 insertions(+)

diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi b/arch/arm/boot/dts/am43xx-clocks.dtsi
index a38af2b..f16ffb5 100644
--- a/arch/arm/boot/dts/am43xx-clocks.dtsi
+++ b/arch/arm/boot/dts/am43xx-clocks.dtsi
@@ -771,4 +771,58 @@
 		ti,bit-shift = <8>;
 		reg = <0x8a68>;
 	};
+
+	clkout1_osc_div_ck: clkout1_osc_div_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&sys_clkin_ck>;
+		ti,bit-shift = <20>;
+		ti,max-div = <4>;
+		reg = <0x4100>;
+	};
+
+	clkout1_src2_mux_ck: clkout1_src2_mux_ck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&clk_rc32k_ck>, <&sysclk_div>, <&dpll_ddr_m2_ck>,
+			 <&dpll_per_m2_ck>, <&dpll_disp_m2_ck>,
+			 <&dpll_mpu_m2_ck>;
+		reg = <0x4100>;
+	};
+
+	clkout1_src2_pre_div_ck: clkout1_src2_pre_div_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&clkout1_src2_mux_ck>;
+		ti,bit-shift = <4>;
+		ti,max-div = <8>;
+		reg = <0x4100>;
+	};
+
+	clkout1_src2_post_div_ck: clkout1_src2_post_div_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&clkout1_src2_pre_div_ck>;
+		ti,bit-shift = <8>;
+		ti,max-div = <32>;
+		ti,index-power-of-two;
+		reg = <0x4100>;
+	};
+
+	clkout1_mux_ck: clkout1_mux_ck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&clkout1_osc_div_ck>, <&clk_rc32k_ck>,
+			 <&clkout1_src2_post_div_ck>, <&dpll_extdev_m2_ck>;
+		ti,bit-shift = <16>;
+		reg = <0x4100>;
+	};
+
+	clkout1_ck: clkout1_ck {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&clkout1_mux_ck>;
+		ti,bit-shift = <23>;
+		reg = <0x4100>;
+	};
 };
-- 
1.7.9.5

^ permalink raw reply related	[flat|nested] 35+ messages in thread

* [PATCH 3/3] ARM: dts: am43xx: add support for clkout1 clock
@ 2016-03-16 19:54   ` Tero Kristo
  0 siblings, 0 replies; 35+ messages in thread
From: Tero Kristo @ 2016-03-16 19:54 UTC (permalink / raw)
  To: linux-omap, linux-clk, mturquette, sboyd, tony; +Cc: linux-arm-kernel

clkout1 clock node and its generation tree was missing. Add this based
on the data on TRM and PRCM functional spec.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Tested-by: Benoit Parrot <bparrot@ti.com>
---
 arch/arm/boot/dts/am43xx-clocks.dtsi |   54 ++++++++++++++++++++++++++++++++++
 1 file changed, 54 insertions(+)

diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi b/arch/arm/boot/dts/am43xx-clocks.dtsi
index a38af2b..f16ffb5 100644
--- a/arch/arm/boot/dts/am43xx-clocks.dtsi
+++ b/arch/arm/boot/dts/am43xx-clocks.dtsi
@@ -771,4 +771,58 @@
 		ti,bit-shift = <8>;
 		reg = <0x8a68>;
 	};
+
+	clkout1_osc_div_ck: clkout1_osc_div_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&sys_clkin_ck>;
+		ti,bit-shift = <20>;
+		ti,max-div = <4>;
+		reg = <0x4100>;
+	};
+
+	clkout1_src2_mux_ck: clkout1_src2_mux_ck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&clk_rc32k_ck>, <&sysclk_div>, <&dpll_ddr_m2_ck>,
+			 <&dpll_per_m2_ck>, <&dpll_disp_m2_ck>,
+			 <&dpll_mpu_m2_ck>;
+		reg = <0x4100>;
+	};
+
+	clkout1_src2_pre_div_ck: clkout1_src2_pre_div_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&clkout1_src2_mux_ck>;
+		ti,bit-shift = <4>;
+		ti,max-div = <8>;
+		reg = <0x4100>;
+	};
+
+	clkout1_src2_post_div_ck: clkout1_src2_post_div_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&clkout1_src2_pre_div_ck>;
+		ti,bit-shift = <8>;
+		ti,max-div = <32>;
+		ti,index-power-of-two;
+		reg = <0x4100>;
+	};
+
+	clkout1_mux_ck: clkout1_mux_ck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&clkout1_osc_div_ck>, <&clk_rc32k_ck>,
+			 <&clkout1_src2_post_div_ck>, <&dpll_extdev_m2_ck>;
+		ti,bit-shift = <16>;
+		reg = <0x4100>;
+	};
+
+	clkout1_ck: clkout1_ck {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&clkout1_mux_ck>;
+		ti,bit-shift = <23>;
+		reg = <0x4100>;
+	};
 };
-- 
1.7.9.5


^ permalink raw reply related	[flat|nested] 35+ messages in thread

* [PATCH 3/3] ARM: dts: am43xx: add support for clkout1 clock
@ 2016-03-16 19:54   ` Tero Kristo
  0 siblings, 0 replies; 35+ messages in thread
From: Tero Kristo @ 2016-03-16 19:54 UTC (permalink / raw)
  To: linux-arm-kernel

clkout1 clock node and its generation tree was missing. Add this based
on the data on TRM and PRCM functional spec.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Tested-by: Benoit Parrot <bparrot@ti.com>
---
 arch/arm/boot/dts/am43xx-clocks.dtsi |   54 ++++++++++++++++++++++++++++++++++
 1 file changed, 54 insertions(+)

diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi b/arch/arm/boot/dts/am43xx-clocks.dtsi
index a38af2b..f16ffb5 100644
--- a/arch/arm/boot/dts/am43xx-clocks.dtsi
+++ b/arch/arm/boot/dts/am43xx-clocks.dtsi
@@ -771,4 +771,58 @@
 		ti,bit-shift = <8>;
 		reg = <0x8a68>;
 	};
+
+	clkout1_osc_div_ck: clkout1_osc_div_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&sys_clkin_ck>;
+		ti,bit-shift = <20>;
+		ti,max-div = <4>;
+		reg = <0x4100>;
+	};
+
+	clkout1_src2_mux_ck: clkout1_src2_mux_ck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&clk_rc32k_ck>, <&sysclk_div>, <&dpll_ddr_m2_ck>,
+			 <&dpll_per_m2_ck>, <&dpll_disp_m2_ck>,
+			 <&dpll_mpu_m2_ck>;
+		reg = <0x4100>;
+	};
+
+	clkout1_src2_pre_div_ck: clkout1_src2_pre_div_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&clkout1_src2_mux_ck>;
+		ti,bit-shift = <4>;
+		ti,max-div = <8>;
+		reg = <0x4100>;
+	};
+
+	clkout1_src2_post_div_ck: clkout1_src2_post_div_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&clkout1_src2_pre_div_ck>;
+		ti,bit-shift = <8>;
+		ti,max-div = <32>;
+		ti,index-power-of-two;
+		reg = <0x4100>;
+	};
+
+	clkout1_mux_ck: clkout1_mux_ck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&clkout1_osc_div_ck>, <&clk_rc32k_ck>,
+			 <&clkout1_src2_post_div_ck>, <&dpll_extdev_m2_ck>;
+		ti,bit-shift = <16>;
+		reg = <0x4100>;
+	};
+
+	clkout1_ck: clkout1_ck {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&clkout1_mux_ck>;
+		ti,bit-shift = <23>;
+		reg = <0x4100>;
+	};
 };
-- 
1.7.9.5

^ permalink raw reply related	[flat|nested] 35+ messages in thread

* Re: [PATCH 0/3] ARM: AMx3xx: misc clock fixes
  2016-03-16 19:54 ` Tero Kristo
  (?)
@ 2016-03-16 22:33   ` Nishanth Menon
  -1 siblings, 0 replies; 35+ messages in thread
From: Nishanth Menon @ 2016-03-16 22:33 UTC (permalink / raw)
  To: Tero Kristo, linux-omap, linux-clk, mturquette, sboyd, tony
  Cc: linux-arm-kernel

On 03/16/2016 02:54 PM, Tero Kristo wrote:
> Hi,
> 
> These patches add DPLL max rate support on AMx3xx SoCs, and add
> support for clkout1 clock on AM43xx. Targeted for 4.7 merge window.


This series looks good to me:
Reviewed-by: Nishanth Menon <nm@ti.com>


-- 
Regards,
Nishanth Menon

^ permalink raw reply	[flat|nested] 35+ messages in thread

* Re: [PATCH 0/3] ARM: AMx3xx: misc clock fixes
@ 2016-03-16 22:33   ` Nishanth Menon
  0 siblings, 0 replies; 35+ messages in thread
From: Nishanth Menon @ 2016-03-16 22:33 UTC (permalink / raw)
  To: Tero Kristo, linux-omap, linux-clk, mturquette, sboyd, tony
  Cc: linux-arm-kernel

On 03/16/2016 02:54 PM, Tero Kristo wrote:
> Hi,
> 
> These patches add DPLL max rate support on AMx3xx SoCs, and add
> support for clkout1 clock on AM43xx. Targeted for 4.7 merge window.


This series looks good to me:
Reviewed-by: Nishanth Menon <nm@ti.com>


-- 
Regards,
Nishanth Menon

^ permalink raw reply	[flat|nested] 35+ messages in thread

* [PATCH 0/3] ARM: AMx3xx: misc clock fixes
@ 2016-03-16 22:33   ` Nishanth Menon
  0 siblings, 0 replies; 35+ messages in thread
From: Nishanth Menon @ 2016-03-16 22:33 UTC (permalink / raw)
  To: linux-arm-kernel

On 03/16/2016 02:54 PM, Tero Kristo wrote:
> Hi,
> 
> These patches add DPLL max rate support on AMx3xx SoCs, and add
> support for clkout1 clock on AM43xx. Targeted for 4.7 merge window.


This series looks good to me:
Reviewed-by: Nishanth Menon <nm@ti.com>


-- 
Regards,
Nishanth Menon

^ permalink raw reply	[flat|nested] 35+ messages in thread

* Re: [PATCH 1/3] clk: ti: dpll: add support for specifying max rate for DPLLs
  2016-03-16 19:54   ` Tero Kristo
@ 2016-04-01 19:27     ` Stephen Boyd
  -1 siblings, 0 replies; 35+ messages in thread
From: Stephen Boyd @ 2016-04-01 19:27 UTC (permalink / raw)
  To: Tero Kristo
  Cc: linux-omap, linux-clk, mturquette, tony, linux-arm-kernel,
	Nishanth Menon, Tomi Valkeinen, Lokesh Vutla

On 03/16, Tero Kristo wrote:
> DPLLs typically have a maximum rate they can support, and this varies
> from DPLL to DPLL. Add support of the maximum rate value to the DPLL
> data struct, and also add check for this in the DPLL round_rate function.
> 
> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> Cc: Nishanth Menon <nm@ti.com>
> Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
> Cc: Lokesh Vutla <lokeshvutla@ti.com>
> ---

Acked-by: Stephen Boyd <sboyd@codeaurora.org>

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

^ permalink raw reply	[flat|nested] 35+ messages in thread

* [PATCH 1/3] clk: ti: dpll: add support for specifying max rate for DPLLs
@ 2016-04-01 19:27     ` Stephen Boyd
  0 siblings, 0 replies; 35+ messages in thread
From: Stephen Boyd @ 2016-04-01 19:27 UTC (permalink / raw)
  To: linux-arm-kernel

On 03/16, Tero Kristo wrote:
> DPLLs typically have a maximum rate they can support, and this varies
> from DPLL to DPLL. Add support of the maximum rate value to the DPLL
> data struct, and also add check for this in the DPLL round_rate function.
> 
> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> Cc: Nishanth Menon <nm@ti.com>
> Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
> Cc: Lokesh Vutla <lokeshvutla@ti.com>
> ---

Acked-by: Stephen Boyd <sboyd@codeaurora.org>

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

^ permalink raw reply	[flat|nested] 35+ messages in thread

* Re: [PATCH 2/3] clk: ti: amx3xx: limit the maximum frequency of DPLLs based on spec
  2016-03-16 19:54   ` Tero Kristo
@ 2016-04-01 19:28     ` Stephen Boyd
  -1 siblings, 0 replies; 35+ messages in thread
From: Stephen Boyd @ 2016-04-01 19:28 UTC (permalink / raw)
  To: Tero Kristo
  Cc: linux-omap, linux-clk, mturquette, tony, linux-arm-kernel,
	Nishanth Menon, Tomi Valkeinen, Lokesh Vutla

On 03/16, Tero Kristo wrote:
> AM33xx/AM43xx devices use the same DPLL IP blocks, which only support
> maximum rate of 1GHz [1] for the default and 2GHz for the low-jitter type
> DPLLs [2]. Reflect this limitation in the DPLL init code by adding the
> max-rate parameter based on the DPLL types.
> 
> [1] Functional, integration & test specification for GS70 ADPLLS, Rev 1.0-01
> [2] Functional, integration & test specification for GS70 ADPLLLJ, Rev 0.8-02
> 
> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> Cc: Nishanth Menon <nm@ti.com>
> Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
> Cc: Lokesh Vutla <lokeshvutla@ti.com>
> ---

Acked-by: Stephen Boyd <sboyd@codeaurora.org>

Or I can apply these two targeting 4.7 if you like.

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

^ permalink raw reply	[flat|nested] 35+ messages in thread

* [PATCH 2/3] clk: ti: amx3xx: limit the maximum frequency of DPLLs based on spec
@ 2016-04-01 19:28     ` Stephen Boyd
  0 siblings, 0 replies; 35+ messages in thread
From: Stephen Boyd @ 2016-04-01 19:28 UTC (permalink / raw)
  To: linux-arm-kernel

On 03/16, Tero Kristo wrote:
> AM33xx/AM43xx devices use the same DPLL IP blocks, which only support
> maximum rate of 1GHz [1] for the default and 2GHz for the low-jitter type
> DPLLs [2]. Reflect this limitation in the DPLL init code by adding the
> max-rate parameter based on the DPLL types.
> 
> [1] Functional, integration & test specification for GS70 ADPLLS, Rev 1.0-01
> [2] Functional, integration & test specification for GS70 ADPLLLJ, Rev 0.8-02
> 
> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> Cc: Nishanth Menon <nm@ti.com>
> Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
> Cc: Lokesh Vutla <lokeshvutla@ti.com>
> ---

Acked-by: Stephen Boyd <sboyd@codeaurora.org>

Or I can apply these two targeting 4.7 if you like.

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

^ permalink raw reply	[flat|nested] 35+ messages in thread

* Re: [PATCH 3/3] ARM: dts: am43xx: add support for clkout1 clock
  2016-03-16 19:54   ` Tero Kristo
@ 2016-04-12 21:05     ` Tony Lindgren
  -1 siblings, 0 replies; 35+ messages in thread
From: Tony Lindgren @ 2016-04-12 21:05 UTC (permalink / raw)
  To: Tero Kristo; +Cc: linux-omap, linux-clk, mturquette, sboyd, linux-arm-kernel

* Tero Kristo <t-kristo@ti.com> [160316 12:55]:
> clkout1 clock node and its generation tree was missing. Add this based
> on the data on TRM and PRCM functional spec.

Can I pick this one separately?

Tony

^ permalink raw reply	[flat|nested] 35+ messages in thread

* [PATCH 3/3] ARM: dts: am43xx: add support for clkout1 clock
@ 2016-04-12 21:05     ` Tony Lindgren
  0 siblings, 0 replies; 35+ messages in thread
From: Tony Lindgren @ 2016-04-12 21:05 UTC (permalink / raw)
  To: linux-arm-kernel

* Tero Kristo <t-kristo@ti.com> [160316 12:55]:
> clkout1 clock node and its generation tree was missing. Add this based
> on the data on TRM and PRCM functional spec.

Can I pick this one separately?

Tony

^ permalink raw reply	[flat|nested] 35+ messages in thread

* Re: [PATCH 2/3] clk: ti: amx3xx: limit the maximum frequency of DPLLs based on spec
  2016-04-01 19:28     ` Stephen Boyd
  (?)
@ 2016-04-13 12:51       ` Tero Kristo
  -1 siblings, 0 replies; 35+ messages in thread
From: Tero Kristo @ 2016-04-13 12:51 UTC (permalink / raw)
  To: Stephen Boyd
  Cc: linux-omap, linux-clk, mturquette, tony, linux-arm-kernel,
	Nishanth Menon, Tomi Valkeinen, Lokesh Vutla

On 04/01/2016 10:28 PM, Stephen Boyd wrote:
> On 03/16, Tero Kristo wrote:
>> AM33xx/AM43xx devices use the same DPLL IP blocks, which only support
>> maximum rate of 1GHz [1] for the default and 2GHz for the low-jitter type
>> DPLLs [2]. Reflect this limitation in the DPLL init code by adding the
>> max-rate parameter based on the DPLL types.
>>
>> [1] Functional, integration & test specification for GS70 ADPLLS, Rev 1.0-01
>> [2] Functional, integration & test specification for GS70 ADPLLLJ, Rev 0.8-02
>>
>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>> Cc: Nishanth Menon <nm@ti.com>
>> Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
>> Cc: Lokesh Vutla <lokeshvutla@ti.com>
>> ---
>
> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
>
> Or I can apply these two targeting 4.7 if you like.

Yea I am fine with this. Want to pick up the old patch from Grygorii also?

-Tero

^ permalink raw reply	[flat|nested] 35+ messages in thread

* Re: [PATCH 2/3] clk: ti: amx3xx: limit the maximum frequency of DPLLs based on spec
@ 2016-04-13 12:51       ` Tero Kristo
  0 siblings, 0 replies; 35+ messages in thread
From: Tero Kristo @ 2016-04-13 12:51 UTC (permalink / raw)
  To: Stephen Boyd
  Cc: linux-omap, linux-clk, mturquette, tony, linux-arm-kernel,
	Nishanth Menon, Tomi Valkeinen, Lokesh Vutla

On 04/01/2016 10:28 PM, Stephen Boyd wrote:
> On 03/16, Tero Kristo wrote:
>> AM33xx/AM43xx devices use the same DPLL IP blocks, which only support
>> maximum rate of 1GHz [1] for the default and 2GHz for the low-jitter type
>> DPLLs [2]. Reflect this limitation in the DPLL init code by adding the
>> max-rate parameter based on the DPLL types.
>>
>> [1] Functional, integration & test specification for GS70 ADPLLS, Rev 1.0-01
>> [2] Functional, integration & test specification for GS70 ADPLLLJ, Rev 0.8-02
>>
>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>> Cc: Nishanth Menon <nm@ti.com>
>> Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
>> Cc: Lokesh Vutla <lokeshvutla@ti.com>
>> ---
>
> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
>
> Or I can apply these two targeting 4.7 if you like.

Yea I am fine with this. Want to pick up the old patch from Grygorii also?

-Tero


^ permalink raw reply	[flat|nested] 35+ messages in thread

* [PATCH 2/3] clk: ti: amx3xx: limit the maximum frequency of DPLLs based on spec
@ 2016-04-13 12:51       ` Tero Kristo
  0 siblings, 0 replies; 35+ messages in thread
From: Tero Kristo @ 2016-04-13 12:51 UTC (permalink / raw)
  To: linux-arm-kernel

On 04/01/2016 10:28 PM, Stephen Boyd wrote:
> On 03/16, Tero Kristo wrote:
>> AM33xx/AM43xx devices use the same DPLL IP blocks, which only support
>> maximum rate of 1GHz [1] for the default and 2GHz for the low-jitter type
>> DPLLs [2]. Reflect this limitation in the DPLL init code by adding the
>> max-rate parameter based on the DPLL types.
>>
>> [1] Functional, integration & test specification for GS70 ADPLLS, Rev 1.0-01
>> [2] Functional, integration & test specification for GS70 ADPLLLJ, Rev 0.8-02
>>
>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>> Cc: Nishanth Menon <nm@ti.com>
>> Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
>> Cc: Lokesh Vutla <lokeshvutla@ti.com>
>> ---
>
> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
>
> Or I can apply these two targeting 4.7 if you like.

Yea I am fine with this. Want to pick up the old patch from Grygorii also?

-Tero

^ permalink raw reply	[flat|nested] 35+ messages in thread

* Re: [PATCH 3/3] ARM: dts: am43xx: add support for clkout1 clock
  2016-04-12 21:05     ` Tony Lindgren
  (?)
@ 2016-04-13 12:52       ` Tero Kristo
  -1 siblings, 0 replies; 35+ messages in thread
From: Tero Kristo @ 2016-04-13 12:52 UTC (permalink / raw)
  To: Tony Lindgren; +Cc: linux-omap, linux-clk, mturquette, sboyd, linux-arm-kernel

On 04/13/2016 12:05 AM, Tony Lindgren wrote:
> * Tero Kristo <t-kristo@ti.com> [160316 12:55]:
>> clkout1 clock node and its generation tree was missing. Add this based
>> on the data on TRM and PRCM functional spec.
>
> Can I pick this one separately?

Yes it has no dependencies towards the other patches.

-Tero

>
> Tony
>

^ permalink raw reply	[flat|nested] 35+ messages in thread

* Re: [PATCH 3/3] ARM: dts: am43xx: add support for clkout1 clock
@ 2016-04-13 12:52       ` Tero Kristo
  0 siblings, 0 replies; 35+ messages in thread
From: Tero Kristo @ 2016-04-13 12:52 UTC (permalink / raw)
  To: Tony Lindgren; +Cc: linux-omap, linux-clk, mturquette, sboyd, linux-arm-kernel

On 04/13/2016 12:05 AM, Tony Lindgren wrote:
> * Tero Kristo <t-kristo@ti.com> [160316 12:55]:
>> clkout1 clock node and its generation tree was missing. Add this based
>> on the data on TRM and PRCM functional spec.
>
> Can I pick this one separately?

Yes it has no dependencies towards the other patches.

-Tero

>
> Tony
>


^ permalink raw reply	[flat|nested] 35+ messages in thread

* [PATCH 3/3] ARM: dts: am43xx: add support for clkout1 clock
@ 2016-04-13 12:52       ` Tero Kristo
  0 siblings, 0 replies; 35+ messages in thread
From: Tero Kristo @ 2016-04-13 12:52 UTC (permalink / raw)
  To: linux-arm-kernel

On 04/13/2016 12:05 AM, Tony Lindgren wrote:
> * Tero Kristo <t-kristo@ti.com> [160316 12:55]:
>> clkout1 clock node and its generation tree was missing. Add this based
>> on the data on TRM and PRCM functional spec.
>
> Can I pick this one separately?

Yes it has no dependencies towards the other patches.

-Tero

>
> Tony
>

^ permalink raw reply	[flat|nested] 35+ messages in thread

* Re: [PATCH 3/3] ARM: dts: am43xx: add support for clkout1 clock
  2016-04-13 12:52       ` Tero Kristo
@ 2016-04-13 19:07         ` Tony Lindgren
  -1 siblings, 0 replies; 35+ messages in thread
From: Tony Lindgren @ 2016-04-13 19:07 UTC (permalink / raw)
  To: Tero Kristo; +Cc: linux-omap, linux-clk, mturquette, sboyd, linux-arm-kernel

* Tero Kristo <t-kristo@ti.com> [160413 05:53]:
> On 04/13/2016 12:05 AM, Tony Lindgren wrote:
> >* Tero Kristo <t-kristo@ti.com> [160316 12:55]:
> >>clkout1 clock node and its generation tree was missing. Add this based
> >>on the data on TRM and PRCM functional spec.
> >
> >Can I pick this one separately?
> 
> Yes it has no dependencies towards the other patches.

OK applying into omap-for-v4.7/dt thanks.

Tony

^ permalink raw reply	[flat|nested] 35+ messages in thread

* [PATCH 3/3] ARM: dts: am43xx: add support for clkout1 clock
@ 2016-04-13 19:07         ` Tony Lindgren
  0 siblings, 0 replies; 35+ messages in thread
From: Tony Lindgren @ 2016-04-13 19:07 UTC (permalink / raw)
  To: linux-arm-kernel

* Tero Kristo <t-kristo@ti.com> [160413 05:53]:
> On 04/13/2016 12:05 AM, Tony Lindgren wrote:
> >* Tero Kristo <t-kristo@ti.com> [160316 12:55]:
> >>clkout1 clock node and its generation tree was missing. Add this based
> >>on the data on TRM and PRCM functional spec.
> >
> >Can I pick this one separately?
> 
> Yes it has no dependencies towards the other patches.

OK applying into omap-for-v4.7/dt thanks.

Tony

^ permalink raw reply	[flat|nested] 35+ messages in thread

* Re: [PATCH 2/3] clk: ti: amx3xx: limit the maximum frequency of DPLLs based on spec
  2016-04-13 12:51       ` Tero Kristo
@ 2016-04-16  0:23         ` Stephen Boyd
  -1 siblings, 0 replies; 35+ messages in thread
From: Stephen Boyd @ 2016-04-16  0:23 UTC (permalink / raw)
  To: Tero Kristo
  Cc: linux-omap, linux-clk, mturquette, tony, linux-arm-kernel,
	Nishanth Menon, Tomi Valkeinen, Lokesh Vutla

On 04/13, Tero Kristo wrote:
> On 04/01/2016 10:28 PM, Stephen Boyd wrote:
> >On 03/16, Tero Kristo wrote:
> >>AM33xx/AM43xx devices use the same DPLL IP blocks, which only support
> >>maximum rate of 1GHz [1] for the default and 2GHz for the low-jitter type
> >>DPLLs [2]. Reflect this limitation in the DPLL init code by adding the
> >>max-rate parameter based on the DPLL types.
> >>
> >>[1] Functional, integration & test specification for GS70 ADPLLS, Rev 1.0-01
> >>[2] Functional, integration & test specification for GS70 ADPLLLJ, Rev 0.8-02
> >>
> >>Signed-off-by: Tero Kristo <t-kristo@ti.com>
> >>Cc: Nishanth Menon <nm@ti.com>
> >>Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
> >>Cc: Lokesh Vutla <lokeshvutla@ti.com>
> >>---
> >
> >Acked-by: Stephen Boyd <sboyd@codeaurora.org>
> >
> >Or I can apply these two targeting 4.7 if you like.
> 
> Yea I am fine with this. Want to pick up the old patch from Grygorii also?
> 

Ok let me find these two!

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

^ permalink raw reply	[flat|nested] 35+ messages in thread

* [PATCH 2/3] clk: ti: amx3xx: limit the maximum frequency of DPLLs based on spec
@ 2016-04-16  0:23         ` Stephen Boyd
  0 siblings, 0 replies; 35+ messages in thread
From: Stephen Boyd @ 2016-04-16  0:23 UTC (permalink / raw)
  To: linux-arm-kernel

On 04/13, Tero Kristo wrote:
> On 04/01/2016 10:28 PM, Stephen Boyd wrote:
> >On 03/16, Tero Kristo wrote:
> >>AM33xx/AM43xx devices use the same DPLL IP blocks, which only support
> >>maximum rate of 1GHz [1] for the default and 2GHz for the low-jitter type
> >>DPLLs [2]. Reflect this limitation in the DPLL init code by adding the
> >>max-rate parameter based on the DPLL types.
> >>
> >>[1] Functional, integration & test specification for GS70 ADPLLS, Rev 1.0-01
> >>[2] Functional, integration & test specification for GS70 ADPLLLJ, Rev 0.8-02
> >>
> >>Signed-off-by: Tero Kristo <t-kristo@ti.com>
> >>Cc: Nishanth Menon <nm@ti.com>
> >>Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
> >>Cc: Lokesh Vutla <lokeshvutla@ti.com>
> >>---
> >
> >Acked-by: Stephen Boyd <sboyd@codeaurora.org>
> >
> >Or I can apply these two targeting 4.7 if you like.
> 
> Yea I am fine with this. Want to pick up the old patch from Grygorii also?
> 

Ok let me find these two!

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

^ permalink raw reply	[flat|nested] 35+ messages in thread

* Re: [PATCH 1/3] clk: ti: dpll: add support for specifying max rate for DPLLs
  2016-03-16 19:54   ` Tero Kristo
@ 2016-04-16  0:26     ` Stephen Boyd
  -1 siblings, 0 replies; 35+ messages in thread
From: Stephen Boyd @ 2016-04-16  0:26 UTC (permalink / raw)
  To: Tero Kristo
  Cc: linux-omap, linux-clk, mturquette, tony, linux-arm-kernel,
	Nishanth Menon, Tomi Valkeinen, Lokesh Vutla

On 03/16, Tero Kristo wrote:
> DPLLs typically have a maximum rate they can support, and this varies
> from DPLL to DPLL. Add support of the maximum rate value to the DPLL
> data struct, and also add check for this in the DPLL round_rate function.
> 
> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> Cc: Nishanth Menon <nm@ti.com>
> Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
> Cc: Lokesh Vutla <lokeshvutla@ti.com>
> ---

Applied to clk-next with some munging for clk_hw_get_rate()

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

^ permalink raw reply	[flat|nested] 35+ messages in thread

* [PATCH 1/3] clk: ti: dpll: add support for specifying max rate for DPLLs
@ 2016-04-16  0:26     ` Stephen Boyd
  0 siblings, 0 replies; 35+ messages in thread
From: Stephen Boyd @ 2016-04-16  0:26 UTC (permalink / raw)
  To: linux-arm-kernel

On 03/16, Tero Kristo wrote:
> DPLLs typically have a maximum rate they can support, and this varies
> from DPLL to DPLL. Add support of the maximum rate value to the DPLL
> data struct, and also add check for this in the DPLL round_rate function.
> 
> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> Cc: Nishanth Menon <nm@ti.com>
> Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
> Cc: Lokesh Vutla <lokeshvutla@ti.com>
> ---

Applied to clk-next with some munging for clk_hw_get_rate()

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

^ permalink raw reply	[flat|nested] 35+ messages in thread

* Re: [PATCH 2/3] clk: ti: amx3xx: limit the maximum frequency of DPLLs based on spec
  2016-03-16 19:54   ` Tero Kristo
@ 2016-04-16  0:27     ` Stephen Boyd
  -1 siblings, 0 replies; 35+ messages in thread
From: Stephen Boyd @ 2016-04-16  0:27 UTC (permalink / raw)
  To: Tero Kristo
  Cc: linux-omap, linux-clk, mturquette, tony, linux-arm-kernel,
	Nishanth Menon, Tomi Valkeinen, Lokesh Vutla

On 03/16, Tero Kristo wrote:
> AM33xx/AM43xx devices use the same DPLL IP blocks, which only support
> maximum rate of 1GHz [1] for the default and 2GHz for the low-jitter type
> DPLLs [2]. Reflect this limitation in the DPLL init code by adding the
> max-rate parameter based on the DPLL types.
> 
> [1] Functional, integration & test specification for GS70 ADPLLS, Rev 1.0-01
> [2] Functional, integration & test specification for GS70 ADPLLLJ, Rev 0.8-02
> 
> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> Cc: Nishanth Menon <nm@ti.com>
> Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
> Cc: Lokesh Vutla <lokeshvutla@ti.com>
> ---

Applied to clk-next

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

^ permalink raw reply	[flat|nested] 35+ messages in thread

* [PATCH 2/3] clk: ti: amx3xx: limit the maximum frequency of DPLLs based on spec
@ 2016-04-16  0:27     ` Stephen Boyd
  0 siblings, 0 replies; 35+ messages in thread
From: Stephen Boyd @ 2016-04-16  0:27 UTC (permalink / raw)
  To: linux-arm-kernel

On 03/16, Tero Kristo wrote:
> AM33xx/AM43xx devices use the same DPLL IP blocks, which only support
> maximum rate of 1GHz [1] for the default and 2GHz for the low-jitter type
> DPLLs [2]. Reflect this limitation in the DPLL init code by adding the
> max-rate parameter based on the DPLL types.
> 
> [1] Functional, integration & test specification for GS70 ADPLLS, Rev 1.0-01
> [2] Functional, integration & test specification for GS70 ADPLLLJ, Rev 0.8-02
> 
> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> Cc: Nishanth Menon <nm@ti.com>
> Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
> Cc: Lokesh Vutla <lokeshvutla@ti.com>
> ---

Applied to clk-next

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

^ permalink raw reply	[flat|nested] 35+ messages in thread

end of thread, other threads:[~2016-04-16  0:27 UTC | newest]

Thread overview: 35+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-03-16 19:54 [PATCH 0/3] ARM: AMx3xx: misc clock fixes Tero Kristo
2016-03-16 19:54 ` Tero Kristo
2016-03-16 19:54 ` Tero Kristo
2016-03-16 19:54 ` [PATCH 1/3] clk: ti: dpll: add support for specifying max rate for DPLLs Tero Kristo
2016-03-16 19:54   ` Tero Kristo
2016-03-16 19:54   ` Tero Kristo
2016-04-01 19:27   ` Stephen Boyd
2016-04-01 19:27     ` Stephen Boyd
2016-04-16  0:26   ` Stephen Boyd
2016-04-16  0:26     ` Stephen Boyd
2016-03-16 19:54 ` [PATCH 2/3] clk: ti: amx3xx: limit the maximum frequency of DPLLs based on spec Tero Kristo
2016-03-16 19:54   ` Tero Kristo
2016-03-16 19:54   ` Tero Kristo
2016-04-01 19:28   ` Stephen Boyd
2016-04-01 19:28     ` Stephen Boyd
2016-04-13 12:51     ` Tero Kristo
2016-04-13 12:51       ` Tero Kristo
2016-04-13 12:51       ` Tero Kristo
2016-04-16  0:23       ` Stephen Boyd
2016-04-16  0:23         ` Stephen Boyd
2016-04-16  0:27   ` Stephen Boyd
2016-04-16  0:27     ` Stephen Boyd
2016-03-16 19:54 ` [PATCH 3/3] ARM: dts: am43xx: add support for clkout1 clock Tero Kristo
2016-03-16 19:54   ` Tero Kristo
2016-03-16 19:54   ` Tero Kristo
2016-04-12 21:05   ` Tony Lindgren
2016-04-12 21:05     ` Tony Lindgren
2016-04-13 12:52     ` Tero Kristo
2016-04-13 12:52       ` Tero Kristo
2016-04-13 12:52       ` Tero Kristo
2016-04-13 19:07       ` Tony Lindgren
2016-04-13 19:07         ` Tony Lindgren
2016-03-16 22:33 ` [PATCH 0/3] ARM: AMx3xx: misc clock fixes Nishanth Menon
2016-03-16 22:33   ` Nishanth Menon
2016-03-16 22:33   ` Nishanth Menon

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