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From: Ian Munsie <imunsie@au1.ibm.com>
To: "andrew.donnellan" <andrew.donnellan@au1.ibm.com>
Cc: linuxppc-dev <linuxppc-dev@lists.ozlabs.org>
Subject: Re: [PATCH] cxl: fix setting of _PAGE_USER bit when handling page
 faults
In-reply-to: <1458273681-18588-1-git-send-email-andrew.donnellan@au1.ibm.com>
References: <1458273681-18588-1-git-send-email-andrew.donnellan@au1.ibm.com>
Date: Fri, 18 Mar 2016 17:30:23 +1100
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Excerpts from andrew.donnellan's message of 2016-03-18 15:01:21 +1100:
> Fixes: f204e0b8cedd ("cxl: Driver code for powernv PCIe based cards for
> userspace access")

It doesn't fix that since there was no cxl kernel API support at the
time, so this wasn't a regression - just something we missed when the
kernel api was added (I believe the broken test in the code was a left
over from some early bringup work and would never have been exercised on
an upstream kernel until then).

> Currently, this should only affect cxlflash.

We haven't run into any problems because of this that I am aware of - do
we have a test case for this?

> -    if ((!ctx->kernel) || ~(dar & (1ULL << 63)))
> +    if ((!ctx->kernel) || !(dar & (1ULL << 63)))

Should it be the top two bits?

-Ian