From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jingjing Wu Subject: [PATCH v6 7/9] i40e: fix VLAN bitmasks for input set Date: Wed, 23 Mar 2016 21:07:10 +0800 Message-ID: <1458738432-3184-8-git-send-email-jingjing.wu@intel.com> References: <1458541132-11953-1-git-send-email-jingjing.wu@intel.com> <1458738432-3184-1-git-send-email-jingjing.wu@intel.com> Cc: dev@dpdk.org, jingjing.wu@intel.com, helin.zhang@intel.com, Andrey Chilikin To: bruce.richardson@intel.com Return-path: Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by dpdk.org (Postfix) with ESMTP id 972942B98 for ; Wed, 23 Mar 2016 14:07:35 +0100 (CET) In-Reply-To: <1458738432-3184-1-git-send-email-jingjing.wu@intel.com> List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Andrey Chilikin This patch adds missing VLAN bitmask for inner frame in case of tunneling and fixes VLAN tags bitmasks for single or outer frame in case of tunneling. Fixes: 98f055707685 ("i40e: configure input fields for RSS or flow director") Signed-off-by: Andrey Chilikin Signed-off-by: Jingjing Wu Acked-by: Helin Zhang --- drivers/net/i40e/i40e_ethdev.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c index ff0ee2e..493db14 100644 --- a/drivers/net/i40e/i40e_ethdev.c +++ b/drivers/net/i40e/i40e_ethdev.c @@ -198,10 +198,12 @@ #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL /* Source MAC address */ #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL -/* VLAN tag in the outer L2 header */ -#define I40E_REG_INSET_L2_OUTER_VLAN 0x0080000000000000ULL -/* VLAN tag in the inner L2 header */ -#define I40E_REG_INSET_L2_INNER_VLAN 0x0100000000000000ULL +/* Outer (S-Tag) VLAN tag in the outer L2 header */ +#define I40E_REG_INSET_L2_OUTER_VLAN 0x0200000000000000ULL +/* Inner (C-Tag) or single VLAN tag in the outer L2 header */ +#define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL +/* Single VLAN tag in the inner L2 header */ +#define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL /* Source IPv4 address */ #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL /* Destination IPv4 address */ @@ -7018,7 +7020,7 @@ i40e_translate_input_set_reg(uint64_t input) I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT}, {I40E_INSET_TUNNEL_DST_PORT, I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT}, - {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID}, + {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN}, {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1}, {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2}, {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3}, -- 2.4.0