From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andre Przywara Subject: [RFC PATCH 15/45] KVM: arm/arm64: vgic-new: Add ENABLE registers handlers Date: Fri, 25 Mar 2016 02:04:38 +0000 Message-ID: <1458871508-17279-16-git-send-email-andre.przywara@arm.com> References: <1458871508-17279-1-git-send-email-andre.przywara@arm.com> Cc: kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org To: Christoffer Dall , Marc Zyngier , Eric Auger Return-path: Received: from foss.arm.com ([217.140.101.70]:54667 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752266AbcCYCFf (ORCPT ); Thu, 24 Mar 2016 22:05:35 -0400 In-Reply-To: <1458871508-17279-1-git-send-email-andre.przywara@arm.com> Sender: kvm-owner@vger.kernel.org List-ID: Signed-off-by: Andre Przywara --- virt/kvm/arm/vgic/vgic_mmio.c | 81 +++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 79 insertions(+), 2 deletions(-) diff --git a/virt/kvm/arm/vgic/vgic_mmio.c b/virt/kvm/arm/vgic/vgic_mmio.c index e62366e..0688a69 100644 --- a/virt/kvm/arm/vgic/vgic_mmio.c +++ b/virt/kvm/arm/vgic/vgic_mmio.c @@ -129,15 +129,92 @@ static int vgic_mmio_write_v2_misc(struct kvm_vcpu *vcpu, return 0; } +/* + * Read accesses to both GICD_ICENABLER and GICD_ISENABLER return the value + * of the enabled bit, so there is only one function for both here. + */ +static int vgic_mmio_read_enable(struct kvm_vcpu *vcpu, + struct kvm_io_device *this, + gpa_t addr, int len, void *val) +{ + struct vgic_io_device *iodev = container_of(this, + struct vgic_io_device, dev); + u32 intid = (addr - iodev->base_addr) * 8; + u32 value = 0; + int i; + + if (iodev->redist_vcpu) + vcpu = iodev->redist_vcpu; + + /* Loop over all IRQs affected by this read */ + for (i = 0; i < len * 8; i++) { + struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i); + + if (irq->enabled) + value |= (1U << i); + } + + write_mask32(value, addr & 3, len, val); + return 0; +} + +static int vgic_mmio_write_senable(struct kvm_vcpu *vcpu, + struct kvm_io_device *this, + gpa_t addr, int len, const void *val) +{ + struct vgic_io_device *iodev = container_of(this, + struct vgic_io_device, dev); + u32 intid = (addr - iodev->base_addr) * 8; + int i; + + if (iodev->redist_vcpu) + vcpu = iodev->redist_vcpu; + + for_each_set_bit(i, val, len * 8) { + struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i); + + spin_lock(&irq->irq_lock); + irq->enabled = true; + vgic_queue_irq(vcpu->kvm, irq); + } + + return 0; +} + +static int vgic_mmio_write_cenable(struct kvm_vcpu *vcpu, + struct kvm_io_device *this, + gpa_t addr, int len, const void *val) +{ + struct vgic_io_device *iodev = container_of(this, + struct vgic_io_device, dev); + u32 intid = (addr - iodev->base_addr) * 8; + int i; + + if (iodev->redist_vcpu) + vcpu = iodev->redist_vcpu; + + for_each_set_bit(i, val, len * 8) { + struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i); + + spin_lock(&irq->irq_lock); + + irq->enabled = false; + /* TODO: Does the exit/entry code take care of "unqueuing"? */ + + spin_unlock(&irq->irq_lock); + } + return 0; +} + struct vgic_register_region vgic_v2_dist_registers[] = { REGISTER_DESC_WITH_LENGTH(GIC_DIST_CTRL, vgic_mmio_read_v2_misc, vgic_mmio_write_v2_misc, 12), REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_IGROUP, vgic_mmio_read_raz, vgic_mmio_write_wi, 1), REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_ENABLE_SET, - vgic_mmio_read_nyi, vgic_mmio_write_nyi, 1), + vgic_mmio_read_enable, vgic_mmio_write_senable, 1), REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_ENABLE_CLEAR, - vgic_mmio_read_nyi, vgic_mmio_write_nyi, 1), + vgic_mmio_read_enable, vgic_mmio_write_cenable, 1), REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_PENDING_SET, vgic_mmio_read_nyi, vgic_mmio_write_nyi, 1), REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_PENDING_CLEAR, -- 2.7.3 From mboxrd@z Thu Jan 1 00:00:00 1970 From: andre.przywara@arm.com (Andre Przywara) Date: Fri, 25 Mar 2016 02:04:38 +0000 Subject: [RFC PATCH 15/45] KVM: arm/arm64: vgic-new: Add ENABLE registers handlers In-Reply-To: <1458871508-17279-1-git-send-email-andre.przywara@arm.com> References: <1458871508-17279-1-git-send-email-andre.przywara@arm.com> Message-ID: <1458871508-17279-16-git-send-email-andre.przywara@arm.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Signed-off-by: Andre Przywara --- virt/kvm/arm/vgic/vgic_mmio.c | 81 +++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 79 insertions(+), 2 deletions(-) diff --git a/virt/kvm/arm/vgic/vgic_mmio.c b/virt/kvm/arm/vgic/vgic_mmio.c index e62366e..0688a69 100644 --- a/virt/kvm/arm/vgic/vgic_mmio.c +++ b/virt/kvm/arm/vgic/vgic_mmio.c @@ -129,15 +129,92 @@ static int vgic_mmio_write_v2_misc(struct kvm_vcpu *vcpu, return 0; } +/* + * Read accesses to both GICD_ICENABLER and GICD_ISENABLER return the value + * of the enabled bit, so there is only one function for both here. + */ +static int vgic_mmio_read_enable(struct kvm_vcpu *vcpu, + struct kvm_io_device *this, + gpa_t addr, int len, void *val) +{ + struct vgic_io_device *iodev = container_of(this, + struct vgic_io_device, dev); + u32 intid = (addr - iodev->base_addr) * 8; + u32 value = 0; + int i; + + if (iodev->redist_vcpu) + vcpu = iodev->redist_vcpu; + + /* Loop over all IRQs affected by this read */ + for (i = 0; i < len * 8; i++) { + struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i); + + if (irq->enabled) + value |= (1U << i); + } + + write_mask32(value, addr & 3, len, val); + return 0; +} + +static int vgic_mmio_write_senable(struct kvm_vcpu *vcpu, + struct kvm_io_device *this, + gpa_t addr, int len, const void *val) +{ + struct vgic_io_device *iodev = container_of(this, + struct vgic_io_device, dev); + u32 intid = (addr - iodev->base_addr) * 8; + int i; + + if (iodev->redist_vcpu) + vcpu = iodev->redist_vcpu; + + for_each_set_bit(i, val, len * 8) { + struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i); + + spin_lock(&irq->irq_lock); + irq->enabled = true; + vgic_queue_irq(vcpu->kvm, irq); + } + + return 0; +} + +static int vgic_mmio_write_cenable(struct kvm_vcpu *vcpu, + struct kvm_io_device *this, + gpa_t addr, int len, const void *val) +{ + struct vgic_io_device *iodev = container_of(this, + struct vgic_io_device, dev); + u32 intid = (addr - iodev->base_addr) * 8; + int i; + + if (iodev->redist_vcpu) + vcpu = iodev->redist_vcpu; + + for_each_set_bit(i, val, len * 8) { + struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i); + + spin_lock(&irq->irq_lock); + + irq->enabled = false; + /* TODO: Does the exit/entry code take care of "unqueuing"? */ + + spin_unlock(&irq->irq_lock); + } + return 0; +} + struct vgic_register_region vgic_v2_dist_registers[] = { REGISTER_DESC_WITH_LENGTH(GIC_DIST_CTRL, vgic_mmio_read_v2_misc, vgic_mmio_write_v2_misc, 12), REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_IGROUP, vgic_mmio_read_raz, vgic_mmio_write_wi, 1), REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_ENABLE_SET, - vgic_mmio_read_nyi, vgic_mmio_write_nyi, 1), + vgic_mmio_read_enable, vgic_mmio_write_senable, 1), REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_ENABLE_CLEAR, - vgic_mmio_read_nyi, vgic_mmio_write_nyi, 1), + vgic_mmio_read_enable, vgic_mmio_write_cenable, 1), REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_PENDING_SET, vgic_mmio_read_nyi, vgic_mmio_write_nyi, 1), REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_PENDING_CLEAR, -- 2.7.3