* [PATCH v2 0/6] Add pinctrl support for Baytrail
@ 2016-03-28 13:29 Cristina Ciocan
2016-03-28 13:29 ` [PATCH v2 1/6] pinctrl: baytrail: Add pin control data structures Cristina Ciocan
` (6 more replies)
0 siblings, 7 replies; 11+ messages in thread
From: Cristina Ciocan @ 2016-03-28 13:29 UTC (permalink / raw)
To: mathias.nyman, mika.westerberg, linux-gpio
Cc: linux-kernel, irina.tirdea, octavian.purdila, Cristina Ciocan
Add support for pin control (pin muxing and pin configuration) for Baytrail
platform.
It follows the design in pinctrl-intel.c, but could not use the
implementation in pinctrl-intel since there were significant differences:
- gpio pin pads are not ordered
- per group functions: for setting a certain mode, there are groups
that need setting pins with different values; for instance, for
setting USB ULPI pins to GPIO function, pin 2 (GPIO_SUS1) needs
to be set to function 1, wihle all other from the group need to be
set to 0
- communities only need pin base and count as specific data
- irq set type only clears all flags, while the actual type setting
is made in the byt_irq_unmask function, which does not comply with
the intel pinctrl implementation
Changes from v1:
- fix reg, reg_val and byt_soc_data not used variables warnings
Cristina Ciocan (6):
pinctrl: baytrail: Add pin control data structures
pinctrl: baytrail: Add pin control operations
pinctrl: baytrail: Update gpio chip operations
pinctrl: baytrail: Update irq chip operations
pinctrl: baytrail: Register pin control handling
pinctrl: baytrail: Add debounce configuration
drivers/pinctrl/intel/Kconfig | 3 +
drivers/pinctrl/intel/pinctrl-baytrail.c | 1690 +++++++++++++++++++++++++-----
2 files changed, 1444 insertions(+), 249 deletions(-)
--
1.9.1
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v2 1/6] pinctrl: baytrail: Add pin control data structures
2016-03-28 13:29 [PATCH v2 0/6] Add pinctrl support for Baytrail Cristina Ciocan
@ 2016-03-28 13:29 ` Cristina Ciocan
2016-03-30 11:15 ` Mika Westerberg
2016-03-28 13:29 ` [PATCH v2 2/6] pinctrl: baytrail: Add pin control operations Cristina Ciocan
` (5 subsequent siblings)
6 siblings, 1 reply; 11+ messages in thread
From: Cristina Ciocan @ 2016-03-28 13:29 UTC (permalink / raw)
To: mathias.nyman, mika.westerberg, linux-gpio
Cc: linux-kernel, irina.tirdea, octavian.purdila, Cristina Ciocan
In order to implement pin control for Baytrail, we need data structures
in which to store and pass along pin, group, function, community and SOC
data information.
Baytrail has 3 GPIO controllers. Add SCORE, NCORE and SUS controller data:
- pins (for all controllers),
- pad map for pins (for all controllers; we need this since pads
are not ordered),
- groups (for SCORE and SUS controllers),
- functions (for SCORE and SUS controllers),
- communities (for all controllers),
- soc specific data gathering all of the above and the ACPI UID
(for all controllers)
This information is useful for pin control functionality. NCORE data is
lighter than the other two controllers' due to lack of pin documentation in
the public datasheet.
Datasheet:
http://www.intel.com/content/www/us/en/embedded/products/bay-trail/atom-e3800-family-datasheet.html
Signed-off-by: Cristina Ciocan <cristina.ciocan@intel.com>
---
drivers/pinctrl/intel/pinctrl-baytrail.c | 628 +++++++++++++++++++++++++++++--
1 file changed, 606 insertions(+), 22 deletions(-)
diff --git a/drivers/pinctrl/intel/pinctrl-baytrail.c b/drivers/pinctrl/intel/pinctrl-baytrail.c
index 21b79a4..cd83de3 100644
--- a/drivers/pinctrl/intel/pinctrl-baytrail.c
+++ b/drivers/pinctrl/intel/pinctrl-baytrail.c
@@ -73,17 +73,207 @@
#define BYT_NCORE_ACPI_UID "2"
#define BYT_SUS_ACPI_UID "3"
-/*
- * Baytrail gpio controller consist of three separate sub-controllers called
- * SCORE, NCORE and SUS. The sub-controllers are identified by their acpi UID.
- *
- * GPIO numbering is _not_ ordered meaning that gpio # 0 in ACPI namespace does
- * _not_ correspond to the first gpio register at controller's gpio base.
- * There is no logic or pattern in mapping gpio numbers to registers (pads) so
- * each sub-controller needs to have its own mapping table
- */
+struct byt_gpio_pin_context {
+ u32 conf0;
+ u32 val;
+};
+
+struct byt_simple_func_mux {
+ const char *name;
+ unsigned short func;
+};
+
+struct byt_mixed_func_mux {
+ const char *name;
+ const unsigned short *func_values;
+};
+
+struct byt_pingroup {
+ const char *name;
+ const unsigned int *pins;
+ size_t npins;
+ unsigned short has_simple_funcs;
+ union {
+ const struct byt_simple_func_mux *simple_funcs;
+ const struct byt_mixed_func_mux *mixed_funcs;
+ };
+ size_t nfuncs;
+};
+
+struct byt_function {
+ const char *name;
+ const char * const *groups;
+ size_t ngroups;
+};
+
+struct byt_community {
+ unsigned int pin_base;
+ size_t npins;
+ const unsigned int *pad_map;
+ void __iomem *reg_base;
+};
+
+#define SIMPLE_FUNC(n, f) \
+ { \
+ .name = (n), \
+ .func = (f), \
+ }
+#define MIXED_FUNC(n, f) \
+ { \
+ .name = (n), \
+ .func_values = (f), \
+ }
+
+#define PIN_GROUP_SIMPLE(n, p, f) \
+ { \
+ .name = (n), \
+ .pins = (p), \
+ .npins = ARRAY_SIZE((p)), \
+ .has_simple_funcs = 1, \
+ .simple_funcs = (f), \
+ .nfuncs = ARRAY_SIZE((f)), \
+ }
+#define PIN_GROUP_MIXED(n, p, f) \
+ { \
+ .name = (n), \
+ .pins = (p), \
+ .npins = ARRAY_SIZE((p)), \
+ .has_simple_funcs = 0, \
+ .mixed_funcs = (f), \
+ .nfuncs = ARRAY_SIZE((f)), \
+ }
+
+#define FUNCTION(n, g) \
+ { \
+ .name = (n), \
+ .groups = (g), \
+ .ngroups = ARRAY_SIZE((g)), \
+ }
+
+#define COMMUNITY(p, n, map) \
+ { \
+ .pin_base = (p), \
+ .npins = (n), \
+ .pad_map = (map),\
+ }
-/* score_pins[gpio_nr] = pad_nr */
+struct byt_pinctrl_soc_data {
+ const char *uid;
+ const struct pinctrl_pin_desc *pins;
+ size_t npins;
+ const struct byt_pingroup *groups;
+ size_t ngroups;
+ const struct byt_function *functions;
+ size_t nfunctions;
+ const struct byt_community *communities;
+ size_t ncommunities;
+};
+
+/* SCORE pins */
+static const struct pinctrl_pin_desc byt_score_pins[] = {
+ PINCTRL_PIN(0, "SATA_GP[0]"), /* GPIOC_0 */
+ PINCTRL_PIN(1, "SATA_GP[1]"), /* GPIOC_1 */
+ PINCTRL_PIN(2, "SATA_LED#"), /* GPIOC_2 */
+ PINCTRL_PIN(3, "PCIE_CLKREQ[0]#"), /* GPIOC_3 */
+ PINCTRL_PIN(4, "PCIE_CLKREQ[1]#"), /* GPIOC_4 */
+ PINCTRL_PIN(5, "PCIE_CLKREQ[2]#"), /* GPIOC_5 */
+ PINCTRL_PIN(6, "PCIE_CLKREQ[3]#"), /* GPIOC_6 */
+ PINCTRL_PIN(7, "SD3_WP"), /* GPIOC_7 */
+ PINCTRL_PIN(8, "HDA_RST#"), /* GPIOC_8 */
+ PINCTRL_PIN(9, "HDA_SYNC"), /* GPIOC_9 */
+ PINCTRL_PIN(10, "HDA_CLK"), /* GPIOC_10 */
+ PINCTRL_PIN(11, "HDA_SDO"), /* GPIOC_11 */
+ PINCTRL_PIN(12, "HDA_SDI[0]"), /* GPIOC_12 */
+ PINCTRL_PIN(13, "HDA_SDI[1]"), /* GPIOC_13 */
+ PINCTRL_PIN(14, "GPIO_S0_SC[014]"), /* GPIOC_14 */
+ PINCTRL_PIN(15, "GPIO_S0_SC[015]"), /* GPIOC_15 */
+ PINCTRL_PIN(16, "MMC1_CLK"), /* GPIOC_16 */
+ PINCTRL_PIN(17, "MMC1_D[0]"), /* GPIOC_17 */
+ PINCTRL_PIN(18, "MMC1_D[1]"), /* GPIOC_18 */
+ PINCTRL_PIN(19, "MMC1_D[2]"), /* GPIOC_19 */
+ PINCTRL_PIN(20, "MMC1_D[3]"), /* GPIOC_20 */
+ PINCTRL_PIN(21, "MMC1_D[4]"), /* GPIOC_21 */
+ PINCTRL_PIN(22, "MMC1_D[5]"), /* GPIOC_22 */
+ PINCTRL_PIN(23, "MMC1_D[6]"), /* GPIOC_23 */
+ PINCTRL_PIN(24, "MMC1_D[7]"), /* GPIOC_24 */
+ PINCTRL_PIN(25, "MMC1_CMD"), /* GPIOC_25 */
+ PINCTRL_PIN(26, "MMC1_RST#"), /* GPIOC_26 */
+ PINCTRL_PIN(27, "SD2_CLK"), /* GPIOC_27 */
+ PINCTRL_PIN(28, "SD2_D[0]"), /* GPIOC_28 */
+ PINCTRL_PIN(29, "SD2_D[1]"), /* GPIOC_29 */
+ PINCTRL_PIN(30, "SD2_D[2]"), /* GPIOC_30 */
+ PINCTRL_PIN(31, "SD2_D[3]_CD#"), /* GPIOC_31 */
+ PINCTRL_PIN(32, "SD2_CMD"), /* GPIOC_32 */
+ PINCTRL_PIN(33, "SD3_CLK"), /* GPIOC_33 */
+ PINCTRL_PIN(34, "SD3_D[0]"), /* GPIOC_34 */
+ PINCTRL_PIN(35, "SD3_D[1]"), /* GPIOC_35 */
+ PINCTRL_PIN(36, "SD3_D[2]"), /* GPIOC_36 */
+ PINCTRL_PIN(37, "SD3_D[3]"), /* GPIOC_37 */
+ PINCTRL_PIN(38, "SD3_CD#"), /* GPIOC_38 */
+ PINCTRL_PIN(39, "SD3_CMD"), /* GPIOC_39 */
+ PINCTRL_PIN(40, "SD3_1P8EN"), /* GPIOC_40 */
+ PINCTRL_PIN(41, "SD3_PWREN#"), /* GPIOC_41 */
+ PINCTRL_PIN(42, "ILB_LPC_AD[0]"), /* GPIOC_42 */
+ PINCTRL_PIN(43, "ILB_LPC_AD[1]"), /* GPIOC_43 */
+ PINCTRL_PIN(44, "ILB_LPC_AD[2]"), /* GPIOC_44 */
+ PINCTRL_PIN(45, "ILB_LPC_AD[3]"), /* GPIOC_45 */
+ PINCTRL_PIN(46, "ILB_LPC_FRAME#"), /* GPIOC_46 */
+ PINCTRL_PIN(47, "ILB_LPC_CLK[0]"), /* GPIOC_47 */
+ PINCTRL_PIN(48, "ILB_LPC_CLK[1]"), /* GPIOC_48 */
+ PINCTRL_PIN(49, "ILB_LPC_CLKRUN#"), /* GPIOC_49 */
+ PINCTRL_PIN(50, "ILB_LPC_SERIRQ"), /* GPIOC_50 */
+ PINCTRL_PIN(51, "PCU_SMB_DATA"), /* GPIOC_51 */
+ PINCTRL_PIN(52, "PCU_SMB_CLK"), /* GPIOC_52 */
+ PINCTRL_PIN(53, "PCU_SMB_ALERT#"), /* GPIOC_53 */
+ PINCTRL_PIN(54, "ILB_8254_SPKR"), /* GPIOC_54 */
+ PINCTRL_PIN(55, "GPIO_S0_SC[055]"), /* GPIOC_55 */
+ PINCTRL_PIN(56, "GPIO_S0_SC[056]"), /* GPIOC_56 */
+ PINCTRL_PIN(57, "GPIO_S0_SC[057]"), /* GPIOC_57 */
+ PINCTRL_PIN(58, "GPIO_S0_SC[058]"), /* GPIOC_58 */
+ PINCTRL_PIN(59, "GPIO_S0_SC[059]"), /* GPIOC_59 */
+ PINCTRL_PIN(60, "GPIO_S0_SC[060]"), /* GPIOC_60 */
+ PINCTRL_PIN(61, "GPIO_S0_SC[061]"), /* GPIOC_61 */
+ PINCTRL_PIN(62, "LPE_I2S2_CLK"), /* GPIOC_62 */
+ PINCTRL_PIN(63, "LPE_I2S2_FRM"), /* GPIOC_63 */
+ PINCTRL_PIN(64, "LPE_I2S2_DATAIN"), /* GPIOC_64 */
+ PINCTRL_PIN(65, "LPE_I2S2_DATAOUT"), /* GPIOC_65 */
+ PINCTRL_PIN(66, "SIO_SPI_CS#"), /* GPIOC_66 */
+ PINCTRL_PIN(67, "SIO_SPI_MISO"), /* GPIOC_67 */
+ PINCTRL_PIN(68, "SIO_SPI_MOSI"), /* GPIOC_68 */
+ PINCTRL_PIN(69, "SIO_SPI_CLK"), /* GPIOC_69 */
+ PINCTRL_PIN(70, "SIO_UART1_RXD"), /* GPIOC_70 */
+ PINCTRL_PIN(71, "SIO_UART1_TXD"), /* GPIOC_71 */
+ PINCTRL_PIN(72, "SIO_UART1_RTS#"), /* GPIOC_72 */
+ PINCTRL_PIN(73, "SIO_UART1_CTS#"), /* GPIOC_73 */
+ PINCTRL_PIN(74, "SIO_UART2_RXD"), /* GPIOC_74 */
+ PINCTRL_PIN(75, "SIO_UART2_TXD"), /* GPIOC_75 */
+ PINCTRL_PIN(76, "SIO_UART2_RTS#"), /* GPIOC_76 */
+ PINCTRL_PIN(77, "SIO_UART2_CTS#"), /* GPIOC_77 */
+ PINCTRL_PIN(78, "SIO_I2C0_DATA"), /* GPIOC_78 */
+ PINCTRL_PIN(79, "SIO_I2C0_CLK"), /* GPIOC_79 */
+ PINCTRL_PIN(80, "SIO_I2C1_DATA"), /* GPIOC_80 */
+ PINCTRL_PIN(81, "SIO_I2C1_CLK"), /* GPIOC_81 */
+ PINCTRL_PIN(82, "SIO_I2C2_DATA"), /* GPIOC_82 */
+ PINCTRL_PIN(83, "SIO_I2C2_CLK"), /* GPIOC_83 */
+ PINCTRL_PIN(84, "SIO_I2C3_DATA"), /* GPIOC_84 */
+ PINCTRL_PIN(85, "SIO_I2C3_CLK"), /* GPIOC_85 */
+ PINCTRL_PIN(86, "SIO_I2C4_DATA"), /* GPIOC_86 */
+ PINCTRL_PIN(87, "SIO_I2C4_CLK"), /* GPIOC_87 */
+ PINCTRL_PIN(88, "SIO_I2C5_DATA"), /* GPIOC_88 */
+ PINCTRL_PIN(89, "SIO_I2C5_CLK"), /* GPIOC_89 */
+ PINCTRL_PIN(90, "SIO_I2C6_DATA"), /* GPIOC_90 */
+ PINCTRL_PIN(91, "SIO_I2C6_CLK"), /* GPIOC_91 */
+ PINCTRL_PIN(92, "GPIO_S0_SC[092]"), /* GPIOC_92 */
+ PINCTRL_PIN(93, "GPIO_S0_SC[093]"), /* GPIOC_93 */
+ PINCTRL_PIN(94, "SIO_PWM[0]"), /* GPIOC_94 */
+ PINCTRL_PIN(95, "SIO_PWM[1]"), /* GPIOC_95 */
+ PINCTRL_PIN(96, "PMC_PLT_CLK[0]"), /* GPIOC_96 */
+ PINCTRL_PIN(97, "PMC_PLT_CLK[1]"), /* GPIOC_97 */
+ PINCTRL_PIN(98, "PMC_PLT_CLK[2]"), /* GPIOC_98 */
+ PINCTRL_PIN(99, "PMC_PLT_CLK[3]"), /* GPIOC_99 */
+ PINCTRL_PIN(100, "PMC_PLT_CLK[4]"), /* GPIOC_100 */
+ PINCTRL_PIN(101, "PMC_PLT_CLK[5]"), /* GPIOC_101 */
+};
static unsigned const score_pins[BYT_NGPIO_SCORE] = {
85, 89, 93, 96, 99, 102, 98, 101, 34, 37,
@@ -99,13 +289,285 @@ static unsigned const score_pins[BYT_NGPIO_SCORE] = {
97, 100,
};
-static unsigned const ncore_pins[BYT_NGPIO_NCORE] = {
- 19, 18, 17, 20, 21, 22, 24, 25, 23, 16,
- 14, 15, 12, 26, 27, 1, 4, 8, 11, 0,
- 3, 6, 10, 13, 2, 5, 9, 7,
+static const unsigned int byt_score_pins_map[BYT_NGPIO_SCORE] = {
+ 85, 89, 93, 96, 99, 102, 98, 101, 34, 37,
+ 36, 38, 39, 35, 40, 84, 62, 61, 64, 59,
+ 54, 56, 60, 55, 63, 57, 51, 50, 53, 47,
+ 52, 49, 48, 43, 46, 41, 45, 42, 58, 44,
+ 95, 105, 70, 68, 67, 66, 69, 71, 65, 72,
+ 86, 90, 88, 92, 103, 77, 79, 83, 78, 81,
+ 80, 82, 13, 12, 15, 14, 17, 18, 19, 16,
+ 2, 1, 0, 4, 6, 7, 9, 8, 33, 32,
+ 31, 30, 29, 27, 25, 28, 26, 23, 21, 20,
+ 24, 22, 5, 3, 10, 11, 106, 87, 91, 104,
+ 97, 100,
+};
+
+/* SCORE groups */
+static const unsigned int byt_score_uart1_pins[] = { 70, 71, 72, 73 };
+static const unsigned int byt_score_uart2_pins[] = { 74, 75, 76, 77 };
+static const struct byt_simple_func_mux byt_score_uart_mux[] = {
+ SIMPLE_FUNC("uart", 1),
+};
+
+static const unsigned int byt_score_pwm0_pins[] = { 94 };
+static const unsigned int byt_score_pwm1_pins[] = { 95 };
+static const struct byt_simple_func_mux byt_score_pwm_mux[] = {
+ SIMPLE_FUNC("pwm", 1),
+};
+
+static const unsigned int byt_score_sio_spi_pins[] = { 66, 67, 68, 69 };
+static const struct byt_simple_func_mux byt_score_spi_mux[] = {
+ SIMPLE_FUNC("spi", 1),
+};
+
+static const unsigned int byt_score_i2c5_pins[] = { 88, 89 };
+static const unsigned int byt_score_i2c6_pins[] = { 90, 91 };
+static const unsigned int byt_score_i2c4_pins[] = { 86, 87 };
+static const unsigned int byt_score_i2c3_pins[] = { 84, 85 };
+static const unsigned int byt_score_i2c2_pins[] = { 82, 83 };
+static const unsigned int byt_score_i2c1_pins[] = { 80, 81 };
+static const unsigned int byt_score_i2c0_pins[] = { 78, 79 };
+static const struct byt_simple_func_mux byt_score_i2c_mux[] = {
+ SIMPLE_FUNC("i2c", 1),
+};
+
+static const unsigned int byt_score_ssp0_pins[] = { 8, 9, 10, 11 };
+static const unsigned int byt_score_ssp1_pins[] = { 12, 13, 14, 15 };
+static const unsigned int byt_score_ssp2_pins[] = { 62, 63, 64, 65 };
+static const struct byt_simple_func_mux byt_score_ssp_mux[] = {
+ SIMPLE_FUNC("ssp", 1),
+};
+
+static const unsigned int byt_score_sdcard_pins[] = {
+ 7, 33, 34, 35, 36, 37, 38, 39, 40, 41,
+};
+static const unsigned short byt_score_sdcard_mux_values[] = {
+ 2, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+};
+static const struct byt_mixed_func_mux byt_score_sdcard_mux[] = {
+ MIXED_FUNC("sdcard", byt_score_sdcard_mux_values),
+};
+
+static const unsigned int byt_score_sdio_pins[] = { 27, 28, 29, 30, 31, 32 };
+static const struct byt_simple_func_mux byt_score_sdio_mux[] = {
+ SIMPLE_FUNC("sdio", 1),
+};
+
+static const unsigned int byt_score_emmc_pins[] = {
+ 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26,
+};
+static const struct byt_simple_func_mux byt_score_emmc_mux[] = {
+ SIMPLE_FUNC("emmc", 1),
+};
+
+static const unsigned int byt_score_ilb_lpc_pins[] = {
+ 42, 43, 44, 45, 46, 47, 48, 49, 50,
+};
+static const struct byt_simple_func_mux byt_score_lpc_mux[] = {
+ SIMPLE_FUNC("lpc", 1),
+};
+
+static const unsigned int byt_score_sata_pins[] = { 0, 1, 2 };
+static const struct byt_simple_func_mux byt_score_sata_mux[] = {
+ SIMPLE_FUNC("sata", 1),
+};
+
+static const unsigned int byt_score_plt_clk0_pins[] = { 96 };
+static const unsigned int byt_score_plt_clk1_pins[] = { 97 };
+static const unsigned int byt_score_plt_clk2_pins[] = { 98 };
+static const unsigned int byt_score_plt_clk4_pins[] = { 99 };
+static const unsigned int byt_score_plt_clk5_pins[] = { 100 };
+static const unsigned int byt_score_plt_clk3_pins[] = { 101 };
+static const struct byt_simple_func_mux byt_score_plt_clk_mux[] = {
+ SIMPLE_FUNC("plt_clk", 1),
};
-static unsigned const sus_pins[BYT_NGPIO_SUS] = {
+static const unsigned int byt_score_smbus_pins[] = { 51, 52, 53 };
+static const struct byt_simple_func_mux byt_score_smbus_mux[] = {
+ SIMPLE_FUNC("smbus", 1),
+};
+
+static const struct byt_pingroup byt_score_groups[] = {
+ PIN_GROUP_SIMPLE("uart1_grp",
+ byt_score_uart1_pins, byt_score_uart_mux),
+ PIN_GROUP_SIMPLE("uart2_grp",
+ byt_score_uart2_pins, byt_score_uart_mux),
+ PIN_GROUP_SIMPLE("pwm0_grp",
+ byt_score_pwm0_pins, byt_score_pwm_mux),
+ PIN_GROUP_SIMPLE("pwm1_grp",
+ byt_score_pwm1_pins, byt_score_pwm_mux),
+ PIN_GROUP_SIMPLE("ssp2_grp",
+ byt_score_ssp2_pins, byt_score_pwm_mux),
+ PIN_GROUP_SIMPLE("sio_spi_grp",
+ byt_score_sio_spi_pins, byt_score_spi_mux),
+ PIN_GROUP_SIMPLE("i2c5_grp",
+ byt_score_i2c5_pins, byt_score_i2c_mux),
+ PIN_GROUP_SIMPLE("i2c6_grp",
+ byt_score_i2c6_pins, byt_score_i2c_mux),
+ PIN_GROUP_SIMPLE("i2c4_grp",
+ byt_score_i2c4_pins, byt_score_i2c_mux),
+ PIN_GROUP_SIMPLE("i2c3_grp",
+ byt_score_i2c3_pins, byt_score_i2c_mux),
+ PIN_GROUP_SIMPLE("i2c2_grp",
+ byt_score_i2c2_pins, byt_score_i2c_mux),
+ PIN_GROUP_SIMPLE("i2c1_grp",
+ byt_score_i2c1_pins, byt_score_i2c_mux),
+ PIN_GROUP_SIMPLE("i2c0_grp",
+ byt_score_i2c0_pins, byt_score_i2c_mux),
+ PIN_GROUP_SIMPLE("ssp0_grp",
+ byt_score_ssp0_pins, byt_score_ssp_mux),
+ PIN_GROUP_SIMPLE("ssp1_grp",
+ byt_score_ssp1_pins, byt_score_ssp_mux),
+ PIN_GROUP_MIXED("sdcard_grp",
+ byt_score_sdcard_pins, byt_score_sdcard_mux),
+ PIN_GROUP_SIMPLE("sdio_grp",
+ byt_score_sdio_pins, byt_score_sdio_mux),
+ PIN_GROUP_SIMPLE("emmc_grp",
+ byt_score_emmc_pins, byt_score_emmc_mux),
+ PIN_GROUP_SIMPLE("lpc_grp",
+ byt_score_ilb_lpc_pins, byt_score_lpc_mux),
+ PIN_GROUP_SIMPLE("sata_grp",
+ byt_score_sata_pins, byt_score_sata_mux),
+ PIN_GROUP_SIMPLE("plt_clk0_grp",
+ byt_score_plt_clk0_pins, byt_score_plt_clk_mux),
+ PIN_GROUP_SIMPLE("plt_clk1_grp",
+ byt_score_plt_clk1_pins, byt_score_plt_clk_mux),
+ PIN_GROUP_SIMPLE("plt_clk2_grp",
+ byt_score_plt_clk2_pins, byt_score_plt_clk_mux),
+ PIN_GROUP_SIMPLE("plt_clk3_grp",
+ byt_score_plt_clk3_pins, byt_score_plt_clk_mux),
+ PIN_GROUP_SIMPLE("plt_clk4_grp",
+ byt_score_plt_clk4_pins, byt_score_plt_clk_mux),
+ PIN_GROUP_SIMPLE("plt_clk5_grp",
+ byt_score_plt_clk5_pins, byt_score_plt_clk_mux),
+ PIN_GROUP_SIMPLE("smbus_grp",
+ byt_score_smbus_pins, byt_score_smbus_mux),
+};
+
+static const char * const byt_score_uart_groups[] = {
+ "uart1_grp", "uart2_grp",
+};
+static const char * const byt_score_pwm_groups[] = {
+ "pwm0_grp", "pwm1_grp",
+};
+static const char * const byt_score_ssp_groups[] = {
+ "ssp0_grp", "ssp1_grp", "ssp2_grp",
+};
+static const char * const byt_score_spi_groups[] = { "sio_spi_grp" };
+static const char * const byt_score_i2c_groups[] = {
+ "i2c0_grp", "i2c1_grp", "i2c2_grp", "i2c3_grp", "i2c4_grp", "i2c5_grp",
+ "i2c6_grp",
+};
+static const char * const byt_score_sdcard_groups[] = { "sdcard_grp" };
+static const char * const byt_score_sdio_groups[] = { "sdio_grp" };
+static const char * const byt_score_emmc_groups[] = { "emmc_grp" };
+static const char * const byt_score_lpc_groups[] = { "lpc_grp" };
+static const char * const byt_score_sata_groups[] = { "sata_grp" };
+static const char * const byt_score_plt_clk_groups[] = {
+ "plt_clk0_grp", "plt_clk1_grp", "plt_clk2_grp", "plt_clk3_grp",
+ "plt_clk4_grp", "plt_clk5_grp",
+};
+static const char * const byt_score_smbus_groups[] = { "smbus_grp" };
+static const char * const byt_score_gpio_groups[] = {
+ "uart1_grp", "uart2_grp", "pwm0_grp", "pwm1_grp", "ssp0_grp",
+ "ssp1_grp", "ssp2_grp", "sio_spi_grp", "i2c0_grp", "i2c1_grp",
+ "i2c2_grp", "i2c3_grp", "i2c4_grp", "i2c5_grp", "i2c6_grp",
+ "sdcard_grp", "sdio_grp", "emmc_grp", "lpc_grp", "sata_grp",
+ "plt_clk0_grp", "plt_clk1_grp", "plt_clk2_grp", "plt_clk3_grp",
+ "plt_clk4_grp", "plt_clk5_grp", "smbus_grp",
+
+};
+
+static const struct byt_function byt_score_functions[] = {
+ FUNCTION("uart", byt_score_uart_groups),
+ FUNCTION("pwm", byt_score_pwm_groups),
+ FUNCTION("ssp", byt_score_ssp_groups),
+ FUNCTION("spi", byt_score_spi_groups),
+ FUNCTION("i2c", byt_score_i2c_groups),
+ FUNCTION("sdcard", byt_score_sdcard_groups),
+ FUNCTION("sdio", byt_score_sdio_groups),
+ FUNCTION("emmc", byt_score_emmc_groups),
+ FUNCTION("lpc", byt_score_lpc_groups),
+ FUNCTION("sata", byt_score_sata_groups),
+ FUNCTION("plt_clk", byt_score_plt_clk_groups),
+ FUNCTION("smbus", byt_score_smbus_groups),
+ FUNCTION("gpio", byt_score_gpio_groups),
+};
+
+static const struct byt_community byt_score_communities[] = {
+ COMMUNITY(0, BYT_NGPIO_SCORE, byt_score_pins_map),
+};
+
+static const struct byt_pinctrl_soc_data byt_score_soc_data = {
+ .uid = BYT_SCORE_ACPI_UID,
+ .pins = byt_score_pins,
+ .npins = ARRAY_SIZE(byt_score_pins),
+ .groups = byt_score_groups,
+ .ngroups = ARRAY_SIZE(byt_score_groups),
+ .functions = byt_score_functions,
+ .nfunctions = ARRAY_SIZE(byt_score_functions),
+ .communities = byt_score_communities,
+ .ncommunities = ARRAY_SIZE(byt_score_communities),
+};
+
+/* SUS pins */
+static const struct pinctrl_pin_desc byt_sus_pins[] = {
+ PINCTRL_PIN(0, "GPIO_S5[00]"), /* GPIO_SUS0 */
+ PINCTRL_PIN(1, "GPIO_S5[01]"), /* GPIO_SUS1 */
+ PINCTRL_PIN(2, "GPIO_S5[02]"), /* GPIO_SUS2 */
+ PINCTRL_PIN(3, "GPIO_S5[03]"), /* GPIO_SUS3 */
+ PINCTRL_PIN(4, "GPIO_S5[04]"), /* GPIO_SUS4 */
+ PINCTRL_PIN(5, "GPIO_S5[05]"), /* GPIO_SUS5 */
+ PINCTRL_PIN(6, "GPIO_S5[06]"), /* GPIO_SUS6 */
+ PINCTRL_PIN(7, "GPIO_S5[07]"), /* GPIO_SUS7 */
+ PINCTRL_PIN(8, "GPIO_S5[08]"), /* SEC_GPIO_SUS8 */
+ PINCTRL_PIN(9, "GPIO_S5[09]"), /* SEC_GPIO_SUS9 */
+ PINCTRL_PIN(10, "GPIO_S5[10]"), /* SEC_GPIO_SUS10 */
+ PINCTRL_PIN(11, "PMC_SUSPWRDNACK"), /* GPIOS_11 */
+ PINCTRL_PIN(12, "PMC_SUSCLK[0]"), /* GPIOS_12 */
+ PINCTRL_PIN(13, "GPIO_S5[13]"), /* GPIOS_13 */
+ PINCTRL_PIN(14, "USB_ULPI_RST#"), /* GPIOS_14 */
+ PINCTRL_PIN(15, "PMC_WAKE_PCIE[0]#"), /* GPIOS_15 */
+ PINCTRL_PIN(16, "PMC_PWRBTN#"), /* GPIOS_16 */
+ PINCTRL_PIN(17, "GPIO_S5[17]"), /* GPIOS_17 */
+ PINCTRL_PIN(18, "PMC_SUS_STAT#"), /* GPIOS_18 */
+ PINCTRL_PIN(19, "USB_OC[0]#"), /* GPIOS_19 */
+ PINCTRL_PIN(20, "USB_OC[1]#"), /* GPIOS_20 */
+ PINCTRL_PIN(21, "PCU_SPI_CS[1]#"), /* GPIOS_21 */
+ PINCTRL_PIN(22, "GPIO_S5[22]"), /* GPIOS_22 */
+ PINCTRL_PIN(23, "GPIO_S5[23]"), /* GPIOS_23 */
+ PINCTRL_PIN(24, "GPIO_S5[24]"), /* GPIOS_24 */
+ PINCTRL_PIN(25, "GPIO_S5[25]"), /* GPIOS_25 */
+ PINCTRL_PIN(26, "GPIO_S5[26]"), /* GPIOS_26 */
+ PINCTRL_PIN(27, "GPIO_S5[27]"), /* GPIOS_27 */
+ PINCTRL_PIN(28, "GPIO_S5[28]"), /* GPIOS_28 */
+ PINCTRL_PIN(29, "GPIO_S5[29]"), /* GPIOS_29 */
+ PINCTRL_PIN(30, "GPIO_S5[30]"), /* GPIOS_30 */
+ PINCTRL_PIN(31, "USB_ULPI_CLK"), /* GPIOS_31 */
+ PINCTRL_PIN(32, "USB_ULPI_DATA[0]"), /* GPIOS_32 */
+ PINCTRL_PIN(33, "USB_ULPI_DATA[1]"), /* GPIOS_33 */
+ PINCTRL_PIN(34, "USB_ULPI_DATA[2]"), /* GPIOS_34 */
+ PINCTRL_PIN(35, "USB_ULPI_DATA[3]"), /* GPIOS_35 */
+ PINCTRL_PIN(36, "USB_ULPI_DATA[4]"), /* GPIOS_36 */
+ PINCTRL_PIN(37, "USB_ULPI_DATA[5]"), /* GPIOS_37 */
+ PINCTRL_PIN(38, "USB_ULPI_DATA[6]"), /* GPIOS_38 */
+ PINCTRL_PIN(39, "USB_ULPI_DATA[7]"), /* GPIOS_39 */
+ PINCTRL_PIN(40, "USB_ULPI_DIR"), /* GPIOS_40 */
+ PINCTRL_PIN(41, "USB_ULPI_NXT"), /* GPIOS_41 */
+ PINCTRL_PIN(42, "USB_ULPI_STP"), /* GPIOS_42 */
+ PINCTRL_PIN(43, "USB_ULPI_REFCLK"), /* GPIOS_43 */
+};
+
+static const unsigned int sus_pins[BYT_NGPIO_SUS] = {
+ 29, 33, 30, 31, 32, 34, 36, 35, 38, 37,
+ 18, 7, 11, 20, 17, 1, 8, 10, 19, 12,
+ 0, 2, 23, 39, 28, 27, 22, 21, 24, 25,
+ 26, 51, 56, 54, 49, 55, 48, 57, 50, 58,
+ 52, 53, 59, 40,
+};
+
+static const unsigned int byt_sus_pins_map[BYT_NGPIO_SUS] = {
29, 33, 30, 31, 32, 34, 36, 35, 38, 37,
18, 7, 11, 20, 17, 1, 8, 10, 19, 12,
0, 2, 23, 39, 28, 27, 22, 21, 24, 25,
@@ -113,6 +575,126 @@ static unsigned const sus_pins[BYT_NGPIO_SUS] = {
52, 53, 59, 40,
};
+static const unsigned int byt_sus_usb_over_current_pins[] = { 19, 20 };
+static const struct byt_simple_func_mux byt_sus_usb_oc_mux[] = {
+ SIMPLE_FUNC("usb", 0),
+ SIMPLE_FUNC("gpio", 1),
+};
+
+static const unsigned int byt_sus_usb_ulpi_pins[] = {
+ 14, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43,
+};
+static const unsigned short byt_sus_usb_ulpi_mode_values[] = {
+ 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+};
+static const unsigned short byt_sus_usb_ulpi_gpio_mode_values[] = {
+ 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+static const struct byt_mixed_func_mux byt_sus_usb_ulpi_mux[] = {
+ MIXED_FUNC("usb", byt_sus_usb_ulpi_mode_values),
+ MIXED_FUNC("gpio", byt_sus_usb_ulpi_gpio_mode_values),
+};
+
+static const unsigned int byt_sus_pcu_spi_pins[] = { 21 };
+static const struct byt_simple_func_mux byt_sus_pcu_spi_mux[] = {
+ SIMPLE_FUNC("spi", 0),
+ SIMPLE_FUNC("gpio", 1),
+};
+
+static const struct byt_pingroup byt_sus_groups[] = {
+ PIN_GROUP_SIMPLE("usb_oc_grp",
+ byt_sus_usb_over_current_pins, byt_sus_usb_oc_mux),
+ PIN_GROUP_MIXED("usb_ulpi_grp",
+ byt_sus_usb_ulpi_pins, byt_sus_usb_ulpi_mux),
+ PIN_GROUP_SIMPLE("pcu_spi_grp",
+ byt_sus_pcu_spi_pins, byt_sus_pcu_spi_mux),
+};
+
+static const char * const byt_sus_usb_groups[] = {
+ "usb_oc_grp", "usb_ulpi_grp",
+};
+static const char * const byt_sus_spi_groups[] = { "pcu_spi_grp" };
+static const char * const byt_sus_gpio_groups[] = {
+ "usb_oc_grp", "usb_ulpi_grp", "pcu_spi_grp",
+};
+
+static const struct byt_function byt_sus_functions[] = {
+ FUNCTION("usb", byt_sus_usb_groups),
+ FUNCTION("spi", byt_sus_spi_groups),
+ FUNCTION("gpio", byt_sus_gpio_groups),
+};
+
+static const struct byt_community byt_sus_communities[] = {
+ COMMUNITY(0, BYT_NGPIO_SUS, byt_sus_pins_map),
+};
+
+static const struct byt_pinctrl_soc_data byt_sus_soc_data = {
+ .uid = BYT_SUS_ACPI_UID,
+ .pins = byt_sus_pins,
+ .npins = ARRAY_SIZE(byt_sus_pins),
+ .groups = byt_sus_groups,
+ .ngroups = ARRAY_SIZE(byt_sus_groups),
+ .functions = byt_sus_functions,
+ .nfunctions = ARRAY_SIZE(byt_sus_functions),
+ .communities = byt_sus_communities,
+ .ncommunities = ARRAY_SIZE(byt_sus_communities),
+};
+
+static const struct pinctrl_pin_desc byt_ncore_pins[] = {
+ PINCTRL_PIN(0, "GPIO_NCORE[0]"),
+ PINCTRL_PIN(1, "GPIO_NCORE[1]"),
+ PINCTRL_PIN(2, "GPIO_NCORE[2]"),
+ PINCTRL_PIN(3, "GPIO_NCORE[3]"),
+ PINCTRL_PIN(4, "GPIO_NCORE[4]"),
+ PINCTRL_PIN(5, "GPIO_NCORE[5]"),
+ PINCTRL_PIN(6, "GPIO_NCORE[6]"),
+ PINCTRL_PIN(7, "GPIO_NCORE[7]"),
+ PINCTRL_PIN(8, "GPIO_NCORE[8]"),
+ PINCTRL_PIN(9, "GPIO_NCORE[9]"),
+ PINCTRL_PIN(10, "GPIO_NCORE[10]"),
+ PINCTRL_PIN(11, "GPIO_NCORE[11]"),
+ PINCTRL_PIN(12, "GPIO_NCORE[12]"),
+ PINCTRL_PIN(13, "GPIO_NCORE[13]"),
+ PINCTRL_PIN(14, "GPIO_NCORE[14]"),
+ PINCTRL_PIN(15, "GPIO_NCORE[15]"),
+ PINCTRL_PIN(16, "GPIO_NCORE[16]"),
+ PINCTRL_PIN(17, "GPIO_NCORE[17]"),
+ PINCTRL_PIN(18, "GPIO_NCORE[18]"),
+ PINCTRL_PIN(19, "GPIO_NCORE[19]"),
+ PINCTRL_PIN(20, "GPIO_NCORE[20]"),
+ PINCTRL_PIN(21, "GPIO_NCORE[21]"),
+ PINCTRL_PIN(22, "GPIO_NCORE[22]"),
+ PINCTRL_PIN(23, "GPIO_NCORE[23]"),
+ PINCTRL_PIN(24, "GPIO_NCORE[24]"),
+ PINCTRL_PIN(25, "GPIO_NCORE[25]"),
+ PINCTRL_PIN(26, "GPIO_NCORE[26]"),
+ PINCTRL_PIN(27, "GPIO_NCORE[27]"),
+};
+
+static unsigned const byt_ncore_pins_map[BYT_NGPIO_NCORE] = {
+ 19, 18, 17, 20, 21, 22, 24, 25, 23, 16,
+ 14, 15, 12, 26, 27, 1, 4, 8, 11, 0,
+ 3, 6, 10, 13, 2, 5, 9, 7,
+};
+
+static const struct byt_community byt_ncore_communities[] = {
+ COMMUNITY(0, BYT_NGPIO_NCORE, byt_ncore_pins_map),
+};
+
+static const struct byt_pinctrl_soc_data byt_ncore_soc_data = {
+ .uid = BYT_NCORE_ACPI_UID,
+ .pins = byt_ncore_pins,
+ .npins = ARRAY_SIZE(byt_ncore_pins),
+ .communities = byt_ncore_communities,
+ .ncommunities = ARRAY_SIZE(byt_ncore_communities),
+};
+
+static unsigned const ncore_pins[BYT_NGPIO_NCORE] = {
+ 19, 18, 17, 20, 21, 22, 24, 25, 23, 16,
+ 14, 15, 12, 26, 27, 1, 4, 8, 11, 0,
+ 3, 6, 10, 13, 2, 5, 9, 7,
+};
+
static struct pinctrl_gpio_range byt_ranges[] = {
{
.name = BYT_SCORE_ACPI_UID, /* match with acpi _UID in probe */
@@ -133,11 +715,6 @@ static struct pinctrl_gpio_range byt_ranges[] = {
},
};
-struct byt_gpio_pin_context {
- u32 conf0;
- u32 val;
-};
-
struct byt_gpio {
struct gpio_chip chip;
struct platform_device *pdev;
@@ -147,6 +724,13 @@ struct byt_gpio {
struct byt_gpio_pin_context *saved_context;
};
+static const struct byt_pinctrl_soc_data *byt_soc_data[] = {
+ &byt_score_soc_data,
+ &byt_sus_soc_data,
+ &byt_ncore_soc_data,
+ NULL,
+};
+
static void __iomem *byt_gpio_reg(struct gpio_chip *chip, unsigned offset,
int reg)
{
@@ -713,8 +1297,8 @@ static const struct dev_pm_ops byt_gpio_pm_ops = {
};
static const struct acpi_device_id byt_gpio_acpi_match[] = {
- { "INT33B2", 0 },
- { "INT33FC", 0 },
+ { "INT33B2", (kernel_ulong_t)byt_soc_data },
+ { "INT33FC", (kernel_ulong_t)byt_soc_data },
{ }
};
MODULE_DEVICE_TABLE(acpi, byt_gpio_acpi_match);
--
1.9.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v2 2/6] pinctrl: baytrail: Add pin control operations
2016-03-28 13:29 [PATCH v2 0/6] Add pinctrl support for Baytrail Cristina Ciocan
2016-03-28 13:29 ` [PATCH v2 1/6] pinctrl: baytrail: Add pin control data structures Cristina Ciocan
@ 2016-03-28 13:29 ` Cristina Ciocan
2016-03-28 13:29 ` [PATCH v2 3/6] pinctrl: baytrail: Update gpio chip operations Cristina Ciocan
` (4 subsequent siblings)
6 siblings, 0 replies; 11+ messages in thread
From: Cristina Ciocan @ 2016-03-28 13:29 UTC (permalink / raw)
To: mathias.nyman, mika.westerberg, linux-gpio
Cc: linux-kernel, irina.tirdea, octavian.purdila, Cristina Ciocan
Add implementation for:
- pin control, group information retrieval: count, name and pins
- pin muxing:
- function information (count, name and groups)
- mux setting
- gpio control (enable, disable, set direction)
- pin configuration:
- pull disable
- pull up/down and pull strength
- debounce
- any other option is treated as not supported.
Signed-off-by: Cristina Ciocan <cristina.ciocan@intel.com>
---
drivers/pinctrl/intel/Kconfig | 3 +
drivers/pinctrl/intel/pinctrl-baytrail.c | 560 +++++++++++++++++++++++++++++--
2 files changed, 528 insertions(+), 35 deletions(-)
diff --git a/drivers/pinctrl/intel/Kconfig b/drivers/pinctrl/intel/Kconfig
index 4d2efad..1c74e03 100644
--- a/drivers/pinctrl/intel/Kconfig
+++ b/drivers/pinctrl/intel/Kconfig
@@ -6,6 +6,9 @@ config PINCTRL_BAYTRAIL
bool "Intel Baytrail GPIO pin control"
depends on GPIOLIB && ACPI
select GPIOLIB_IRQCHIP
+ select PINMUX
+ select PINCONF
+ select GENERIC_PINCONF
help
driver for memory mapped GPIO functionality on Intel Baytrail
platforms. Supports 3 banks with 102, 28 and 44 gpios.
diff --git a/drivers/pinctrl/intel/pinctrl-baytrail.c b/drivers/pinctrl/intel/pinctrl-baytrail.c
index cd83de3..6901964 100644
--- a/drivers/pinctrl/intel/pinctrl-baytrail.c
+++ b/drivers/pinctrl/intel/pinctrl-baytrail.c
@@ -27,6 +27,9 @@
#include <linux/io.h>
#include <linux/pm_runtime.h>
#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinconf-generic.h>
/* memory mapped register offsets */
#define BYT_CONF0_REG 0x000
@@ -73,6 +76,14 @@
#define BYT_NCORE_ACPI_UID "2"
#define BYT_SUS_ACPI_UID "3"
+/*
+ * This is the function value most pins have for GPIO muxing. If the value
+ * differs from the default one, it must be explicitly mentioned. Otherwise, the
+ * pin control implementation will set the muxing value to default GPIO if it
+ * does not find a match for the requested function.
+ */
+#define BYT_DEFAULT_GPIO_MUX 0
+
struct byt_gpio_pin_context {
u32 conf0;
u32 val;
@@ -722,6 +733,8 @@ struct byt_gpio {
void __iomem *reg_base;
struct pinctrl_gpio_range *range;
struct byt_gpio_pin_context *saved_context;
+ const struct byt_pinctrl_soc_data *soc_data;
+ struct byt_community *communities_copy;
};
static const struct byt_pinctrl_soc_data *byt_soc_data[] = {
@@ -731,52 +744,252 @@ static const struct byt_pinctrl_soc_data *byt_soc_data[] = {
NULL,
};
-static void __iomem *byt_gpio_reg(struct gpio_chip *chip, unsigned offset,
- int reg)
+static struct byt_community *byt_get_community(struct byt_gpio *vg,
+ unsigned int pin)
{
- struct byt_gpio *vg = gpiochip_get_data(chip);
- u32 reg_offset;
+ struct byt_community *comm;
+ int i;
+
+ for (i = 0; i < vg->soc_data->ncommunities; i++) {
+ comm = vg->communities_copy + i;
+ if (pin < comm->pin_base + comm->npins && pin >= comm->pin_base)
+ return comm;
+ }
+ return NULL;
+}
+
+static void __iomem *byt_gpio_reg(struct byt_gpio *vg, unsigned int offset,
+ int reg)
+{
+ struct byt_community *comm = byt_get_community(vg, offset);
+ u32 reg_offset = 0;
+
+ if (!comm)
+ return NULL;
+
+ offset -= comm->pin_base;
if (reg == BYT_INT_STAT_REG)
reg_offset = (offset / 32) * 4;
else
- reg_offset = vg->range->pins[offset] * 16;
+ reg_offset = comm->pad_map[offset] * 16;
+
+ return comm->reg_base + reg_offset + reg;
+}
+
+static int byt_get_groups_count(struct pinctrl_dev *pctldev)
+{
+ struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
+
+ return vg->soc_data->ngroups;
+}
+
+static const char *byt_get_group_name(struct pinctrl_dev *pctldev,
+ unsigned int selector)
+{
+ struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
+
+ return vg->soc_data->groups[selector].name;
+}
+
+static int byt_get_group_pins(struct pinctrl_dev *pctldev,
+ unsigned int selector,
+ const unsigned int **pins,
+ unsigned int *num_pins)
+{
+ struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
+
+ *pins = vg->soc_data->groups[selector].pins;
+ *num_pins = vg->soc_data->groups[selector].npins;
+
+ return 0;
+}
+
+static const struct pinctrl_ops byt_pinctrl_ops = {
+ .get_groups_count = byt_get_groups_count,
+ .get_group_name = byt_get_group_name,
+ .get_group_pins = byt_get_group_pins,
+};
+
+static int byt_get_functions_count(struct pinctrl_dev *pctldev)
+{
+ struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
+
+ return vg->soc_data->nfunctions;
+}
+
+static const char *byt_get_function_name(struct pinctrl_dev *pctldev,
+ unsigned int selector)
+{
+ struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
+
+ return vg->soc_data->functions[selector].name;
+}
+
+static int byt_get_function_groups(struct pinctrl_dev *pctldev,
+ unsigned int selector,
+ const char * const **groups,
+ unsigned int *num_groups)
+{
+ struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
+
+ *groups = vg->soc_data->functions[selector].groups;
+ *num_groups = vg->soc_data->functions[selector].ngroups;
+
+ return 0;
+}
+
+static int byt_get_group_simple_mux(const struct byt_pingroup group,
+ const char *func_name,
+ unsigned short *func)
+{
+ int i;
+
+ for (i = 0; i < group.nfuncs; i++) {
+ if (!strcmp(group.simple_funcs[i].name, func_name)) {
+ *func = group.simple_funcs[i].func;
+ return 0;
+ }
+ }
+
+ return 1;
+}
+
+static int byt_get_group_mixed_mux(const struct byt_pingroup group,
+ const char *func_name,
+ const unsigned short **func)
+{
+ int i;
+
+ for (i = 0; i < group.nfuncs; i++) {
+ if (!strcmp(group.mixed_funcs[i].name, func_name)) {
+ *func = group.mixed_funcs[i].func_values;
+ return 0;
+ }
+ }
- return vg->reg_base + reg_offset + reg;
+ return 1;
}
-static void byt_gpio_clear_triggering(struct byt_gpio *vg, unsigned offset)
+static void byt_set_group_simple_mux(struct byt_gpio *vg,
+ const struct byt_pingroup group,
+ unsigned short func)
{
- void __iomem *reg = byt_gpio_reg(&vg->chip, offset, BYT_CONF0_REG);
unsigned long flags;
- u32 value;
+ int i;
raw_spin_lock_irqsave(&vg->lock, flags);
- value = readl(reg);
- value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL);
- writel(value, reg);
+
+ for (i = 0; i < group.npins; i++) {
+ void __iomem *padcfg0;
+ u32 value;
+
+ padcfg0 = byt_gpio_reg(vg, group.pins[i], BYT_CONF0_REG);
+ if (!padcfg0) {
+ dev_warn(&vg->pdev->dev,
+ "Group %s, pin %i not muxed (no padcfg0)\n",
+ group.name, i);
+ continue;
+ }
+
+ value = readl(padcfg0);
+ value &= ~BYT_PIN_MUX;
+ value |= func;
+ writel(value, padcfg0);
+ }
+
raw_spin_unlock_irqrestore(&vg->lock, flags);
}
+static void byt_set_group_mixed_mux(struct byt_gpio *vg,
+ const struct byt_pingroup group,
+ const unsigned short *func)
+{
+ unsigned long flags;
+ int i;
+
+ raw_spin_lock_irqsave(&vg->lock, flags);
+
+ for (i = 0; i < group.npins; i++) {
+ void __iomem *padcfg0;
+ u32 value;
+
+ padcfg0 = byt_gpio_reg(vg, group.pins[i], BYT_CONF0_REG);
+ if (!padcfg0) {
+ dev_warn(&vg->pdev->dev,
+ "Group %s, pin %i not muxed (no padcfg0)\n",
+ group.name, i);
+ continue;
+ }
+
+ value = readl(padcfg0);
+ value &= ~BYT_PIN_MUX;
+ value |= func[i];
+ writel(value, padcfg0);
+ }
+
+ raw_spin_unlock_irqrestore(&vg->lock, flags);
+}
+
+static int byt_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector,
+ unsigned int group_selector)
+{
+ struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
+ const struct byt_function func = vg->soc_data->functions[func_selector];
+ const struct byt_pingroup group = vg->soc_data->groups[group_selector];
+ const unsigned short *mixed_func;
+ unsigned short simple_func;
+ int ret = 1;
+
+ if (group.has_simple_funcs)
+ ret = byt_get_group_simple_mux(group, func.name, &simple_func);
+ else
+ ret = byt_get_group_mixed_mux(group, func.name, &mixed_func);
+
+ if (ret)
+ byt_set_group_simple_mux(vg, group, BYT_DEFAULT_GPIO_MUX);
+ else if (group.has_simple_funcs)
+ byt_set_group_simple_mux(vg, group, simple_func);
+ else
+ byt_set_group_mixed_mux(vg, group, mixed_func);
+
+ return 0;
+}
+
static u32 byt_get_gpio_mux(struct byt_gpio *vg, unsigned offset)
{
/* SCORE pin 92-93 */
- if (!strcmp(vg->range->name, BYT_SCORE_ACPI_UID) &&
- offset >= 92 && offset <= 93)
+ if (!strcmp(vg->soc_data->uid, BYT_SCORE_ACPI_UID) &&
+ offset >= 92 && offset <= 93)
return 1;
/* SUS pin 11-21 */
- if (!strcmp(vg->range->name, BYT_SUS_ACPI_UID) &&
- offset >= 11 && offset <= 21)
+ if (!strcmp(vg->soc_data->uid, BYT_SUS_ACPI_UID) &&
+ offset >= 11 && offset <= 21)
return 1;
return 0;
}
-static int byt_gpio_request(struct gpio_chip *chip, unsigned offset)
+static void byt_gpio_clear_triggering(struct byt_gpio *vg, unsigned int offset)
{
- struct byt_gpio *vg = gpiochip_get_data(chip);
- void __iomem *reg = byt_gpio_reg(chip, offset, BYT_CONF0_REG);
+ void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
+ unsigned long flags;
+ u32 value;
+
+ raw_spin_lock_irqsave(&vg->lock, flags);
+ value = readl(reg);
+ value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL);
+ writel(value, reg);
+ raw_spin_unlock_irqrestore(&vg->lock, flags);
+}
+
+static int byt_gpio_request_enable(struct pinctrl_dev *pctl_dev,
+ struct pinctrl_gpio_range *range,
+ unsigned int offset)
+{
+ struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev);
+ void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
u32 value, gpio_mux;
unsigned long flags;
@@ -817,13 +1030,102 @@ static void byt_gpio_free(struct gpio_chip *chip, unsigned offset)
pm_runtime_put(&vg->pdev->dev);
}
+static void byt_gpio_disable_free(struct pinctrl_dev *pctl_dev,
+ struct pinctrl_gpio_range *range,
+ unsigned int offset)
+{
+ struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev);
+
+ byt_gpio_clear_triggering(vg, offset);
+ pm_runtime_put(&vg->pdev->dev);
+}
+
+static int byt_gpio_set_direction(struct pinctrl_dev *pctl_dev,
+ struct pinctrl_gpio_range *range,
+ unsigned int offset,
+ bool input)
+{
+ struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev);
+ void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
+ void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
+ unsigned long flags;
+ u32 value;
+
+ raw_spin_lock_irqsave(&vg->lock, flags);
+
+ value = readl(val_reg);
+ value &= ~BYT_DIR_MASK;
+ if (input)
+ value |= BYT_OUTPUT_EN;
+ else
+ /*
+ * Before making any direction modifications, do a check if gpio
+ * is set for direct IRQ. On baytrail, setting GPIO to output
+ * does not make sense, so let's at least warn the caller before
+ * they shoot themselves in the foot.
+ */
+ WARN(readl(conf_reg) & BYT_DIRECT_IRQ_EN,
+ "Potential Error: Setting GPIO with direct_irq_en to output");
+ writel(value, val_reg);
+
+ raw_spin_unlock_irqrestore(&vg->lock, flags);
+
+ return 0;
+}
+
+static const struct pinmux_ops byt_pinmux_ops = {
+ .get_functions_count = byt_get_functions_count,
+ .get_function_name = byt_get_function_name,
+ .get_function_groups = byt_get_function_groups,
+ .set_mux = byt_set_mux,
+ .gpio_request_enable = byt_gpio_request_enable,
+ .gpio_disable_free = byt_gpio_disable_free,
+ .gpio_set_direction = byt_gpio_set_direction,
+};
+
+static int byt_gpio_request(struct gpio_chip *chip, unsigned int offset)
+{
+ struct byt_gpio *vg = gpiochip_get_data(chip);
+ void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
+ u32 value, gpio_mux;
+ unsigned long flags;
+
+ raw_spin_lock_irqsave(&vg->lock, flags);
+
+ /*
+ * In most cases, func pin mux 000 means GPIO function.
+ * But, some pins may have func pin mux 001 represents
+ * GPIO function.
+ *
+ * Because there are devices out there where some pins were not
+ * configured correctly we allow changing the mux value from
+ * request (but print out warning about that).
+ */
+ value = readl(reg) & BYT_PIN_MUX;
+ gpio_mux = byt_get_gpio_mux(vg, offset);
+ if (WARN_ON(gpio_mux != value)) {
+ value = readl(reg) & ~BYT_PIN_MUX;
+ value |= gpio_mux;
+ writel(value, reg);
+
+ dev_warn(&vg->pdev->dev,
+ "pin %u forcibly re-configured as GPIO\n", offset);
+ }
+
+ raw_spin_unlock_irqrestore(&vg->lock, flags);
+
+ pm_runtime_get(&vg->pdev->dev);
+
+ return 0;
+}
+
static int byt_irq_type(struct irq_data *d, unsigned type)
{
struct byt_gpio *vg = gpiochip_get_data(irq_data_get_irq_chip_data(d));
u32 offset = irqd_to_hwirq(d);
u32 value;
unsigned long flags;
- void __iomem *reg = byt_gpio_reg(&vg->chip, offset, BYT_CONF0_REG);
+ void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
if (offset >= vg->chip.ngpio)
return -EINVAL;
@@ -832,7 +1134,7 @@ static int byt_irq_type(struct irq_data *d, unsigned type)
value = readl(reg);
WARN(value & BYT_DIRECT_IRQ_EN,
- "Bad pad config for io mode, force direct_irq_en bit clearing");
+ "Bad pad config for io mode, force direct_irq_en bit clearing");
/* For level trigges the BYT_TRIG_POS and BYT_TRIG_NEG bits
* are used to indicate high and low level triggering
@@ -852,10 +1154,198 @@ static int byt_irq_type(struct irq_data *d, unsigned type)
return 0;
}
+static void byt_get_pull_strength(u32 reg, u16 *strength)
+{
+ switch (reg & BYT_PULL_STR_MASK) {
+ case BYT_PULL_STR_2K:
+ *strength = 2000;
+ break;
+ case BYT_PULL_STR_10K:
+ *strength = 10000;
+ break;
+ case BYT_PULL_STR_20K:
+ *strength = 20000;
+ break;
+ case BYT_PULL_STR_40K:
+ *strength = 40000;
+ break;
+ }
+}
+
+static int byt_set_pull_strength(u32 *reg, u16 strength)
+{
+ *reg &= ~BYT_PULL_STR_MASK;
+
+ switch (strength) {
+ case 2000:
+ *reg |= BYT_PULL_STR_2K;
+ break;
+ case 10000:
+ *reg |= BYT_PULL_STR_10K;
+ break;
+ case 20000:
+ *reg |= BYT_PULL_STR_20K;
+ break;
+ case 40000:
+ *reg |= BYT_PULL_STR_40K;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int byt_pin_config_get(struct pinctrl_dev *pctl_dev, unsigned int offset,
+ unsigned long *config)
+{
+ struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev);
+ enum pin_config_param param = pinconf_to_config_param(*config);
+ void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
+ void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
+ unsigned long flags;
+ u32 conf, pull, val;
+ u16 arg = 0;
+
+ raw_spin_lock_irqsave(&vg->lock, flags);
+ conf = readl(conf_reg);
+ pull = conf & BYT_PULL_ASSIGN_MASK;
+ val = readl(val_reg);
+ raw_spin_unlock_irqrestore(&vg->lock, flags);
+
+ switch (param) {
+ case PIN_CONFIG_BIAS_DISABLE:
+ if (pull)
+ return -EINVAL;
+ break;
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ /* Pull assignment is only applicable in input mode */
+ if ((val & BYT_INPUT_EN) || pull != BYT_PULL_ASSIGN_DOWN)
+ return -EINVAL;
+
+ byt_get_pull_strength(conf, &arg);
+
+ break;
+ case PIN_CONFIG_BIAS_PULL_UP:
+ /* Pull assignment is only applicable in input mode */
+ if ((val & BYT_INPUT_EN) || pull != BYT_PULL_ASSIGN_UP)
+ return -EINVAL;
+
+ byt_get_pull_strength(conf, &arg);
+
+ break;
+ default:
+ return -ENOTSUPP;
+ }
+
+ *config = pinconf_to_config_packed(param, arg);
+
+ return 0;
+}
+
+static int byt_pin_config_set(struct pinctrl_dev *pctl_dev,
+ unsigned int offset,
+ unsigned long *configs,
+ unsigned int num_configs)
+{
+ struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev);
+ unsigned int param, arg;
+ void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
+ void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
+ unsigned long flags;
+ u32 conf, val;
+ int i, ret = 0;
+
+ raw_spin_lock_irqsave(&vg->lock, flags);
+
+ conf = readl(conf_reg);
+ val = readl(val_reg);
+
+ for (i = 0; i < num_configs; i++) {
+ param = pinconf_to_config_param(configs[i]);
+ arg = pinconf_to_config_argument(configs[i]);
+
+ switch (param) {
+ case PIN_CONFIG_BIAS_DISABLE:
+ conf &= ~BYT_PULL_ASSIGN_MASK;
+ break;
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ /* Set default strength value in case none is given */
+ if (arg == 1)
+ arg = 2000;
+
+ /*
+ * Pull assignment is only applicable in input mode. If
+ * chip is not in input mode, set it and warn about it.
+ */
+ if (val & BYT_INPUT_EN) {
+ val &= ~BYT_INPUT_EN;
+ writel(val, val_reg);
+ dev_warn(&vg->pdev->dev,
+ "pin %u forcibly set to input mode\n",
+ offset);
+ }
+
+ conf &= ~BYT_PULL_ASSIGN_MASK;
+ conf |= BYT_PULL_ASSIGN_DOWN;
+ ret = byt_set_pull_strength(&conf, arg);
+
+ break;
+ case PIN_CONFIG_BIAS_PULL_UP:
+ /* Set default strength value in case none is given */
+ if (arg == 1)
+ arg = 2000;
+
+ /*
+ * Pull assignment is only applicable in input mode. If
+ * chip is not in input mode, set it and warn about it.
+ */
+ if (val & BYT_INPUT_EN) {
+ val &= ~BYT_INPUT_EN;
+ writel(val, val_reg);
+ dev_warn(&vg->pdev->dev,
+ "pin %u forcibly set to input mode\n",
+ offset);
+ }
+
+ conf &= ~BYT_PULL_ASSIGN_MASK;
+ conf |= BYT_PULL_ASSIGN_UP;
+ ret = byt_set_pull_strength(&conf, arg);
+
+ break;
+ default:
+ ret = -ENOTSUPP;
+ }
+
+ if (ret)
+ break;
+ }
+
+ if (!ret)
+ writel(conf, conf_reg);
+
+ raw_spin_unlock_irqrestore(&vg->lock, flags);
+
+ return ret;
+}
+
+static const struct pinconf_ops byt_pinconf_ops = {
+ .is_generic = true,
+ .pin_config_get = byt_pin_config_get,
+ .pin_config_set = byt_pin_config_set,
+};
+
+static const struct pinctrl_desc byt_pinctrl_desc = {
+ .pctlops = &byt_pinctrl_ops,
+ .pmxops = &byt_pinmux_ops,
+ .confops = &byt_pinconf_ops,
+ .owner = THIS_MODULE,
+};
+
static int byt_gpio_get(struct gpio_chip *chip, unsigned offset)
{
- void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG);
struct byt_gpio *vg = gpiochip_get_data(chip);
+ void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
unsigned long flags;
u32 val;
@@ -869,7 +1359,7 @@ static int byt_gpio_get(struct gpio_chip *chip, unsigned offset)
static void byt_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
struct byt_gpio *vg = gpiochip_get_data(chip);
- void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG);
+ void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
unsigned long flags;
u32 old_val;
@@ -888,7 +1378,7 @@ static void byt_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
static int byt_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
struct byt_gpio *vg = gpiochip_get_data(chip);
- void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG);
+ void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
unsigned long flags;
u32 value;
@@ -907,8 +1397,8 @@ static int byt_gpio_direction_output(struct gpio_chip *chip,
unsigned gpio, int value)
{
struct byt_gpio *vg = gpiochip_get_data(chip);
- void __iomem *conf_reg = byt_gpio_reg(chip, gpio, BYT_CONF0_REG);
- void __iomem *reg = byt_gpio_reg(chip, gpio, BYT_VAL_REG);
+ void __iomem *conf_reg = byt_gpio_reg(vg, gpio, BYT_CONF0_REG);
+ void __iomem *reg = byt_gpio_reg(vg, gpio, BYT_VAL_REG);
unsigned long flags;
u32 reg_val;
@@ -1019,7 +1509,7 @@ static void byt_gpio_irq_handler(struct irq_desc *desc)
/* check from GPIO controller which pin triggered the interrupt */
for (base = 0; base < vg->chip.ngpio; base += 32) {
- reg = byt_gpio_reg(&vg->chip, base, BYT_INT_STAT_REG);
+ reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG);
pending = readl(reg);
for_each_set_bit(pin, &pending, 32) {
virq = irq_find_mapping(vg->chip.irqdomain, base + pin);
@@ -1037,7 +1527,7 @@ static void byt_irq_ack(struct irq_data *d)
void __iomem *reg;
raw_spin_lock(&vg->lock);
- reg = byt_gpio_reg(&vg->chip, offset, BYT_INT_STAT_REG);
+ reg = byt_gpio_reg(vg, offset, BYT_INT_STAT_REG);
writel(BIT(offset % 32), reg);
raw_spin_unlock(&vg->lock);
}
@@ -1051,7 +1541,7 @@ static void byt_irq_unmask(struct irq_data *d)
void __iomem *reg;
u32 value;
- reg = byt_gpio_reg(&vg->chip, offset, BYT_CONF0_REG);
+ reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
raw_spin_lock_irqsave(&vg->lock, flags);
value = readl(reg);
@@ -1106,7 +1596,7 @@ static void byt_gpio_irq_init_hw(struct byt_gpio *vg)
* interrupts from misconfigured pins.
*/
for (i = 0; i < vg->chip.ngpio; i++) {
- value = readl(byt_gpio_reg(&vg->chip, i, BYT_CONF0_REG));
+ value = readl(byt_gpio_reg(vg, i, BYT_CONF0_REG));
if ((value & BYT_PIN_MUX) == byt_get_gpio_mux(vg, i) &&
!(value & BYT_DIRECT_IRQ_EN)) {
byt_gpio_clear_triggering(vg, i);
@@ -1116,7 +1606,7 @@ static void byt_gpio_irq_init_hw(struct byt_gpio *vg)
/* clear interrupt status trigger registers */
for (base = 0; base < vg->chip.ngpio; base += 32) {
- reg = byt_gpio_reg(&vg->chip, base, BYT_INT_STAT_REG);
+ reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG);
writel(0xffffffff, reg);
/* make sure trigger bits are cleared, if not then a pin
might be misconfigured in bios */
@@ -1226,11 +1716,11 @@ static int byt_gpio_suspend(struct device *dev)
void __iomem *reg;
u32 value;
- reg = byt_gpio_reg(&vg->chip, i, BYT_CONF0_REG);
+ reg = byt_gpio_reg(vg, i, BYT_CONF0_REG);
value = readl(reg) & BYT_CONF0_RESTORE_MASK;
vg->saved_context[i].conf0 = value;
- reg = byt_gpio_reg(&vg->chip, i, BYT_VAL_REG);
+ reg = byt_gpio_reg(vg, i, BYT_VAL_REG);
value = readl(reg) & BYT_VAL_RESTORE_MASK;
vg->saved_context[i].val = value;
}
@@ -1248,7 +1738,7 @@ static int byt_gpio_resume(struct device *dev)
void __iomem *reg;
u32 value;
- reg = byt_gpio_reg(&vg->chip, i, BYT_CONF0_REG);
+ reg = byt_gpio_reg(vg, i, BYT_CONF0_REG);
value = readl(reg);
if ((value & BYT_CONF0_RESTORE_MASK) !=
vg->saved_context[i].conf0) {
@@ -1258,7 +1748,7 @@ static int byt_gpio_resume(struct device *dev)
dev_info(dev, "restored pin %d conf0 %#08x", i, value);
}
- reg = byt_gpio_reg(&vg->chip, i, BYT_VAL_REG);
+ reg = byt_gpio_reg(vg, i, BYT_VAL_REG);
value = readl(reg);
if ((value & BYT_VAL_RESTORE_MASK) !=
vg->saved_context[i].val) {
--
1.9.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v2 3/6] pinctrl: baytrail: Update gpio chip operations
2016-03-28 13:29 [PATCH v2 0/6] Add pinctrl support for Baytrail Cristina Ciocan
2016-03-28 13:29 ` [PATCH v2 1/6] pinctrl: baytrail: Add pin control data structures Cristina Ciocan
2016-03-28 13:29 ` [PATCH v2 2/6] pinctrl: baytrail: Add pin control operations Cristina Ciocan
@ 2016-03-28 13:29 ` Cristina Ciocan
2016-03-28 13:29 ` [PATCH v2 4/6] pinctrl: baytrail: Update irq " Cristina Ciocan
` (3 subsequent siblings)
6 siblings, 0 replies; 11+ messages in thread
From: Cristina Ciocan @ 2016-03-28 13:29 UTC (permalink / raw)
To: mathias.nyman, mika.westerberg, linux-gpio
Cc: linux-kernel, irina.tirdea, octavian.purdila, Cristina Ciocan
This patch updates the gpio chip implementation in order to interact with
the pin control model: the chip contains reference to SOC data and
pin/group/community information is retrieved through the SOC reference.
Signed-off-by: Cristina Ciocan <cristina.ciocan@intel.com>
---
drivers/pinctrl/intel/pinctrl-baytrail.c | 97 ++++++++++++++++++++++----------
1 file changed, 68 insertions(+), 29 deletions(-)
diff --git a/drivers/pinctrl/intel/pinctrl-baytrail.c b/drivers/pinctrl/intel/pinctrl-baytrail.c
index 6901964..eb06bf7 100644
--- a/drivers/pinctrl/intel/pinctrl-baytrail.c
+++ b/drivers/pinctrl/intel/pinctrl-baytrail.c
@@ -20,6 +20,7 @@
#include <linux/types.h>
#include <linux/bitops.h>
#include <linux/interrupt.h>
+#include <linux/gpio.h>
#include <linux/gpio/driver.h>
#include <linux/acpi.h>
#include <linux/platform_device.h>
@@ -1363,44 +1364,45 @@ static void byt_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
unsigned long flags;
u32 old_val;
- raw_spin_lock_irqsave(&vg->lock, flags);
+ if (!reg)
+ return;
+ raw_spin_lock_irqsave(&vg->lock, flags);
old_val = readl(reg);
-
if (value)
writel(old_val | BYT_LEVEL, reg);
else
writel(old_val & ~BYT_LEVEL, reg);
-
raw_spin_unlock_irqrestore(&vg->lock, flags);
}
-static int byt_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
+static int byt_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
{
struct byt_gpio *vg = gpiochip_get_data(chip);
void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
unsigned long flags;
u32 value;
- raw_spin_lock_irqsave(&vg->lock, flags);
-
- value = readl(reg) | BYT_DIR_MASK;
- value &= ~BYT_INPUT_EN; /* active low */
- writel(value, reg);
+ if (!reg)
+ return -EINVAL;
+ raw_spin_lock_irqsave(&vg->lock, flags);
+ value = readl(reg);
raw_spin_unlock_irqrestore(&vg->lock, flags);
- return 0;
+ if (!(value & BYT_OUTPUT_EN))
+ return GPIOF_DIR_OUT;
+ if (!(value & BYT_INPUT_EN))
+ return GPIOF_DIR_IN;
+
+ return -EINVAL;
}
-static int byt_gpio_direction_output(struct gpio_chip *chip,
- unsigned gpio, int value)
+static int byt_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
{
struct byt_gpio *vg = gpiochip_get_data(chip);
- void __iomem *conf_reg = byt_gpio_reg(vg, gpio, BYT_CONF0_REG);
- void __iomem *reg = byt_gpio_reg(vg, gpio, BYT_VAL_REG);
+ void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
unsigned long flags;
- u32 reg_val;
raw_spin_lock_irqsave(&vg->lock, flags);
@@ -1413,15 +1415,18 @@ static int byt_gpio_direction_output(struct gpio_chip *chip,
WARN(readl(conf_reg) & BYT_DIRECT_IRQ_EN,
"Potential Error: Setting GPIO with direct_irq_en to output");
- reg_val = readl(reg) | BYT_DIR_MASK;
- reg_val &= ~(BYT_OUTPUT_EN | BYT_INPUT_EN);
+ return pinctrl_gpio_direction_input(chip->base + offset);
+}
- if (value)
- writel(reg_val | BYT_LEVEL, reg);
- else
- writel(reg_val & ~BYT_LEVEL, reg);
+static int byt_gpio_direction_output(struct gpio_chip *chip,
+ unsigned int offset, int value)
+{
+ int ret = pinctrl_gpio_direction_output(chip->base + offset);
- raw_spin_unlock_irqrestore(&vg->lock, flags);
+ if (ret)
+ return ret;
+
+ byt_gpio_set(chip, offset, value);
return 0;
}
@@ -1430,20 +1435,42 @@ static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
{
struct byt_gpio *vg = gpiochip_get_data(chip);
int i;
- u32 conf0, val, offs;
+ u32 conf0, val;
- for (i = 0; i < vg->chip.ngpio; i++) {
+ for (i = 0; i < vg->soc_data->npins; i++) {
+ const struct byt_community *comm;
const char *pull_str = NULL;
const char *pull = NULL;
+ void __iomem *reg;
unsigned long flags;
const char *label;
- offs = vg->range->pins[i] * 16;
+ unsigned int pin;
raw_spin_lock_irqsave(&vg->lock, flags);
- conf0 = readl(vg->reg_base + offs + BYT_CONF0_REG);
- val = readl(vg->reg_base + offs + BYT_VAL_REG);
+ pin = vg->soc_data->pins[i].number;
+ reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
+ if (!reg) {
+ seq_printf(s,
+ "Could not retrieve pin %i conf0 reg\n",
+ pin);
+ continue;
+ }
+ conf0 = readl(reg);
+
+ reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
+ if (!reg) {
+ seq_printf(s,
+ "Could not retrieve pin %i val reg\n", pin);
+ }
+ val = readl(reg);
raw_spin_unlock_irqrestore(&vg->lock, flags);
+ comm = byt_get_community(vg, pin);
+ if (!comm) {
+ seq_printf(s,
+ "Could not get community for pin %i\n", pin);
+ continue;
+ }
label = gpiochip_is_requested(chip, i);
if (!label)
label = "Unrequested";
@@ -1474,12 +1501,12 @@ static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
seq_printf(s,
" gpio-%-3d (%-20.20s) %s %s %s pad-%-3d offset:0x%03x mux:%d %s%s%s",
- i,
+ pin,
label,
val & BYT_INPUT_EN ? " " : "in",
val & BYT_OUTPUT_EN ? " " : "out",
val & BYT_LEVEL ? "hi" : "lo",
- vg->range->pins[i], offs,
+ comm->pad_map[i], comm->pad_map[i] * 32,
conf0 & 0x7,
conf0 & BYT_TRIG_NEG ? " fall" : " ",
conf0 & BYT_TRIG_POS ? " rise" : " ",
@@ -1519,6 +1546,18 @@ static void byt_gpio_irq_handler(struct irq_desc *desc)
chip->irq_eoi(data);
}
+static const struct gpio_chip byt_gpio_chip = {
+ .owner = THIS_MODULE,
+ .request = gpiochip_generic_request,
+ .free = gpiochip_generic_free,
+ .get_direction = byt_gpio_get_direction,
+ .direction_input = byt_gpio_direction_input,
+ .direction_output = byt_gpio_direction_output,
+ .get = byt_gpio_get,
+ .set = byt_gpio_set,
+ .dbg_show = byt_gpio_dbg_show,
+};
+
static void byt_irq_ack(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
--
1.9.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v2 4/6] pinctrl: baytrail: Update irq chip operations
2016-03-28 13:29 [PATCH v2 0/6] Add pinctrl support for Baytrail Cristina Ciocan
` (2 preceding siblings ...)
2016-03-28 13:29 ` [PATCH v2 3/6] pinctrl: baytrail: Update gpio chip operations Cristina Ciocan
@ 2016-03-28 13:29 ` Cristina Ciocan
2016-03-28 13:29 ` [PATCH v2 5/6] pinctrl: baytrail: Register pin control handling Cristina Ciocan
` (2 subsequent siblings)
6 siblings, 0 replies; 11+ messages in thread
From: Cristina Ciocan @ 2016-03-28 13:29 UTC (permalink / raw)
To: mathias.nyman, mika.westerberg, linux-gpio
Cc: linux-kernel, irina.tirdea, octavian.purdila, Cristina Ciocan
This patch updates the irq chip implementation in order to interact with
the pin control chip model: the chip contains reference to SOC data and
pin/group/community information is retrieved through the SOC reference.
Signed-off-by: Cristina Ciocan <cristina.ciocan@intel.com>
---
drivers/pinctrl/intel/pinctrl-baytrail.c | 97 +++++++++++++++++---------------
1 file changed, 51 insertions(+), 46 deletions(-)
diff --git a/drivers/pinctrl/intel/pinctrl-baytrail.c b/drivers/pinctrl/intel/pinctrl-baytrail.c
index eb06bf7..d8a6809 100644
--- a/drivers/pinctrl/intel/pinctrl-baytrail.c
+++ b/drivers/pinctrl/intel/pinctrl-baytrail.c
@@ -1120,41 +1120,6 @@ static int byt_gpio_request(struct gpio_chip *chip, unsigned int offset)
return 0;
}
-static int byt_irq_type(struct irq_data *d, unsigned type)
-{
- struct byt_gpio *vg = gpiochip_get_data(irq_data_get_irq_chip_data(d));
- u32 offset = irqd_to_hwirq(d);
- u32 value;
- unsigned long flags;
- void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
-
- if (offset >= vg->chip.ngpio)
- return -EINVAL;
-
- raw_spin_lock_irqsave(&vg->lock, flags);
- value = readl(reg);
-
- WARN(value & BYT_DIRECT_IRQ_EN,
- "Bad pad config for io mode, force direct_irq_en bit clearing");
-
- /* For level trigges the BYT_TRIG_POS and BYT_TRIG_NEG bits
- * are used to indicate high and low level triggering
- */
- value &= ~(BYT_DIRECT_IRQ_EN | BYT_TRIG_POS | BYT_TRIG_NEG |
- BYT_TRIG_LVL);
-
- writel(value, reg);
-
- if (type & IRQ_TYPE_EDGE_BOTH)
- irq_set_handler_locked(d, handle_edge_irq);
- else if (type & IRQ_TYPE_LEVEL_MASK)
- irq_set_handler_locked(d, handle_level_irq);
-
- raw_spin_unlock_irqrestore(&vg->lock, flags);
-
- return 0;
-}
-
static void byt_get_pull_strength(u32 reg, u16 *strength)
{
switch (reg & BYT_PULL_STR_MASK) {
@@ -1565,12 +1530,23 @@ static void byt_irq_ack(struct irq_data *d)
unsigned offset = irqd_to_hwirq(d);
void __iomem *reg;
- raw_spin_lock(&vg->lock);
reg = byt_gpio_reg(vg, offset, BYT_INT_STAT_REG);
+ if (!reg)
+ return;
+
+ raw_spin_lock(&vg->lock);
writel(BIT(offset % 32), reg);
raw_spin_unlock(&vg->lock);
}
+static void byt_irq_mask(struct irq_data *d)
+{
+ struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
+ struct byt_gpio *vg = gpiochip_get_data(gc);
+
+ byt_gpio_clear_triggering(vg, irqd_to_hwirq(d));
+}
+
static void byt_irq_unmask(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
@@ -1581,6 +1557,8 @@ static void byt_irq_unmask(struct irq_data *d)
u32 value;
reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
+ if (!reg)
+ return;
raw_spin_lock_irqsave(&vg->lock, flags);
value = readl(reg);
@@ -1606,21 +1584,48 @@ static void byt_irq_unmask(struct irq_data *d)
raw_spin_unlock_irqrestore(&vg->lock, flags);
}
-static void byt_irq_mask(struct irq_data *d)
+static int byt_irq_type(struct irq_data *d, unsigned int type)
{
- struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
- struct byt_gpio *vg = gpiochip_get_data(gc);
+ struct byt_gpio *vg = gpiochip_get_data(irq_data_get_irq_chip_data(d));
+ u32 offset = irqd_to_hwirq(d);
+ u32 value;
+ unsigned long flags;
+ void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
- byt_gpio_clear_triggering(vg, irqd_to_hwirq(d));
+ if (!reg || offset >= vg->chip.ngpio)
+ return -EINVAL;
+
+ raw_spin_lock_irqsave(&vg->lock, flags);
+ value = readl(reg);
+
+ WARN(value & BYT_DIRECT_IRQ_EN,
+ "Bad pad config for io mode, force direct_irq_en bit clearing");
+
+ /* For level trigges the BYT_TRIG_POS and BYT_TRIG_NEG bits
+ * are used to indicate high and low level triggering
+ */
+ value &= ~(BYT_DIRECT_IRQ_EN | BYT_TRIG_POS | BYT_TRIG_NEG |
+ BYT_TRIG_LVL);
+
+ writel(value, reg);
+
+ if (type & IRQ_TYPE_EDGE_BOTH)
+ irq_set_handler_locked(d, handle_edge_irq);
+ else if (type & IRQ_TYPE_LEVEL_MASK)
+ irq_set_handler_locked(d, handle_level_irq);
+
+ raw_spin_unlock_irqrestore(&vg->lock, flags);
+
+ return 0;
}
static struct irq_chip byt_irqchip = {
- .name = "BYT-GPIO",
- .irq_ack = byt_irq_ack,
- .irq_mask = byt_irq_mask,
- .irq_unmask = byt_irq_unmask,
- .irq_set_type = byt_irq_type,
- .flags = IRQCHIP_SKIP_SET_WAKE,
+ .name = "BYT-GPIO",
+ .irq_ack = byt_irq_ack,
+ .irq_mask = byt_irq_mask,
+ .irq_unmask = byt_irq_unmask,
+ .irq_set_type = byt_irq_type,
+ .flags = IRQCHIP_SKIP_SET_WAKE,
};
static void byt_gpio_irq_init_hw(struct byt_gpio *vg)
--
1.9.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v2 5/6] pinctrl: baytrail: Register pin control handling
2016-03-28 13:29 [PATCH v2 0/6] Add pinctrl support for Baytrail Cristina Ciocan
` (3 preceding siblings ...)
2016-03-28 13:29 ` [PATCH v2 4/6] pinctrl: baytrail: Update irq " Cristina Ciocan
@ 2016-03-28 13:29 ` Cristina Ciocan
2016-03-28 13:29 ` [PATCH v2 6/6] pinctrl: baytrail: Add debounce configuration Cristina Ciocan
2016-03-30 14:45 ` [PATCH v2 0/6] Add pinctrl support for Baytrail Mika Westerberg
6 siblings, 0 replies; 11+ messages in thread
From: Cristina Ciocan @ 2016-03-28 13:29 UTC (permalink / raw)
To: mathias.nyman, mika.westerberg, linux-gpio
Cc: linux-kernel, irina.tirdea, octavian.purdila, Cristina Ciocan
This patch updates device's probing, removal and irq handling in order to
register it as pinctrl device. Pin control data is matched by ACPI UID,
since it is passed along as driver data in acpi_device_id structure.
Signed-off-by: Cristina Ciocan <cristina.ciocan@intel.com>
---
drivers/pinctrl/intel/pinctrl-baytrail.c | 447 +++++++++++++++----------------
1 file changed, 221 insertions(+), 226 deletions(-)
diff --git a/drivers/pinctrl/intel/pinctrl-baytrail.c b/drivers/pinctrl/intel/pinctrl-baytrail.c
index d8a6809..0ba28fd 100644
--- a/drivers/pinctrl/intel/pinctrl-baytrail.c
+++ b/drivers/pinctrl/intel/pinctrl-baytrail.c
@@ -181,6 +181,17 @@ struct byt_pinctrl_soc_data {
size_t ncommunities;
};
+struct byt_gpio {
+ struct gpio_chip chip;
+ struct platform_device *pdev;
+ struct pinctrl_dev *pctl_dev;
+ struct pinctrl_desc pctl_desc;
+ raw_spinlock_t lock;
+ const struct byt_pinctrl_soc_data *soc_data;
+ struct byt_community *communities_copy;
+ struct byt_gpio_pin_context *saved_context;
+};
+
/* SCORE pins */
static const struct pinctrl_pin_desc byt_score_pins[] = {
PINCTRL_PIN(0, "SATA_GP[0]"), /* GPIOC_0 */
@@ -287,20 +298,6 @@ static const struct pinctrl_pin_desc byt_score_pins[] = {
PINCTRL_PIN(101, "PMC_PLT_CLK[5]"), /* GPIOC_101 */
};
-static unsigned const score_pins[BYT_NGPIO_SCORE] = {
- 85, 89, 93, 96, 99, 102, 98, 101, 34, 37,
- 36, 38, 39, 35, 40, 84, 62, 61, 64, 59,
- 54, 56, 60, 55, 63, 57, 51, 50, 53, 47,
- 52, 49, 48, 43, 46, 41, 45, 42, 58, 44,
- 95, 105, 70, 68, 67, 66, 69, 71, 65, 72,
- 86, 90, 88, 92, 103, 77, 79, 83, 78, 81,
- 80, 82, 13, 12, 15, 14, 17, 18, 19, 16,
- 2, 1, 0, 4, 6, 7, 9, 8, 33, 32,
- 31, 30, 29, 27, 25, 28, 26, 23, 21, 20,
- 24, 22, 5, 3, 10, 11, 106, 87, 91, 104,
- 97, 100,
-};
-
static const unsigned int byt_score_pins_map[BYT_NGPIO_SCORE] = {
85, 89, 93, 96, 99, 102, 98, 101, 34, 37,
36, 38, 39, 35, 40, 84, 62, 61, 64, 59,
@@ -571,14 +568,6 @@ static const struct pinctrl_pin_desc byt_sus_pins[] = {
PINCTRL_PIN(43, "USB_ULPI_REFCLK"), /* GPIOS_43 */
};
-static const unsigned int sus_pins[BYT_NGPIO_SUS] = {
- 29, 33, 30, 31, 32, 34, 36, 35, 38, 37,
- 18, 7, 11, 20, 17, 1, 8, 10, 19, 12,
- 0, 2, 23, 39, 28, 27, 22, 21, 24, 25,
- 26, 51, 56, 54, 49, 55, 48, 57, 50, 58,
- 52, 53, 59, 40,
-};
-
static const unsigned int byt_sus_pins_map[BYT_NGPIO_SUS] = {
29, 33, 30, 31, 32, 34, 36, 35, 38, 37,
18, 7, 11, 20, 17, 1, 8, 10, 19, 12,
@@ -701,43 +690,6 @@ static const struct byt_pinctrl_soc_data byt_ncore_soc_data = {
.ncommunities = ARRAY_SIZE(byt_ncore_communities),
};
-static unsigned const ncore_pins[BYT_NGPIO_NCORE] = {
- 19, 18, 17, 20, 21, 22, 24, 25, 23, 16,
- 14, 15, 12, 26, 27, 1, 4, 8, 11, 0,
- 3, 6, 10, 13, 2, 5, 9, 7,
-};
-
-static struct pinctrl_gpio_range byt_ranges[] = {
- {
- .name = BYT_SCORE_ACPI_UID, /* match with acpi _UID in probe */
- .npins = BYT_NGPIO_SCORE,
- .pins = score_pins,
- },
- {
- .name = BYT_NCORE_ACPI_UID,
- .npins = BYT_NGPIO_NCORE,
- .pins = ncore_pins,
- },
- {
- .name = BYT_SUS_ACPI_UID,
- .npins = BYT_NGPIO_SUS,
- .pins = sus_pins,
- },
- {
- },
-};
-
-struct byt_gpio {
- struct gpio_chip chip;
- struct platform_device *pdev;
- raw_spinlock_t lock;
- void __iomem *reg_base;
- struct pinctrl_gpio_range *range;
- struct byt_gpio_pin_context *saved_context;
- const struct byt_pinctrl_soc_data *soc_data;
- struct byt_community *communities_copy;
-};
-
static const struct byt_pinctrl_soc_data *byt_soc_data[] = {
&byt_score_soc_data,
&byt_sus_soc_data,
@@ -1023,14 +975,6 @@ static int byt_gpio_request_enable(struct pinctrl_dev *pctl_dev,
return 0;
}
-static void byt_gpio_free(struct gpio_chip *chip, unsigned offset)
-{
- struct byt_gpio *vg = gpiochip_get_data(chip);
-
- byt_gpio_clear_triggering(vg, offset);
- pm_runtime_put(&vg->pdev->dev);
-}
-
static void byt_gpio_disable_free(struct pinctrl_dev *pctl_dev,
struct pinctrl_gpio_range *range,
unsigned int offset)
@@ -1084,42 +1028,6 @@ static const struct pinmux_ops byt_pinmux_ops = {
.gpio_set_direction = byt_gpio_set_direction,
};
-static int byt_gpio_request(struct gpio_chip *chip, unsigned int offset)
-{
- struct byt_gpio *vg = gpiochip_get_data(chip);
- void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
- u32 value, gpio_mux;
- unsigned long flags;
-
- raw_spin_lock_irqsave(&vg->lock, flags);
-
- /*
- * In most cases, func pin mux 000 means GPIO function.
- * But, some pins may have func pin mux 001 represents
- * GPIO function.
- *
- * Because there are devices out there where some pins were not
- * configured correctly we allow changing the mux value from
- * request (but print out warning about that).
- */
- value = readl(reg) & BYT_PIN_MUX;
- gpio_mux = byt_get_gpio_mux(vg, offset);
- if (WARN_ON(gpio_mux != value)) {
- value = readl(reg) & ~BYT_PIN_MUX;
- value |= gpio_mux;
- writel(value, reg);
-
- dev_warn(&vg->pdev->dev,
- "pin %u forcibly re-configured as GPIO\n", offset);
- }
-
- raw_spin_unlock_irqrestore(&vg->lock, flags);
-
- pm_runtime_get(&vg->pdev->dev);
-
- return 0;
-}
-
static void byt_get_pull_strength(u32 reg, u16 *strength)
{
switch (reg & BYT_PULL_STR_MASK) {
@@ -1365,21 +1273,6 @@ static int byt_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
static int byt_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
{
- struct byt_gpio *vg = gpiochip_get_data(chip);
- void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
- unsigned long flags;
-
- raw_spin_lock_irqsave(&vg->lock, flags);
-
- /*
- * Before making any direction modifications, do a check if gpio
- * is set for direct IRQ. On baytrail, setting GPIO to output does
- * not make sense, so let's at least warn the caller before they shoot
- * themselves in the foot.
- */
- WARN(readl(conf_reg) & BYT_DIRECT_IRQ_EN,
- "Potential Error: Setting GPIO with direct_irq_en to output");
-
return pinctrl_gpio_direction_input(chip->base + offset);
}
@@ -1489,28 +1382,6 @@ static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
}
}
-static void byt_gpio_irq_handler(struct irq_desc *desc)
-{
- struct irq_data *data = irq_desc_get_irq_data(desc);
- struct byt_gpio *vg = gpiochip_get_data(irq_desc_get_handler_data(desc));
- struct irq_chip *chip = irq_data_get_irq_chip(data);
- u32 base, pin;
- void __iomem *reg;
- unsigned long pending;
- unsigned virq;
-
- /* check from GPIO controller which pin triggered the interrupt */
- for (base = 0; base < vg->chip.ngpio; base += 32) {
- reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG);
- pending = readl(reg);
- for_each_set_bit(pin, &pending, 32) {
- virq = irq_find_mapping(vg->chip.irqdomain, base + pin);
- generic_handle_irq(virq);
- }
- }
- chip->irq_eoi(data);
-}
-
static const struct gpio_chip byt_gpio_chip = {
.owner = THIS_MODULE,
.request = gpiochip_generic_request,
@@ -1628,6 +1499,37 @@ static struct irq_chip byt_irqchip = {
.flags = IRQCHIP_SKIP_SET_WAKE,
};
+static void byt_gpio_irq_handler(struct irq_desc *desc)
+{
+ struct irq_data *data = irq_desc_get_irq_data(desc);
+ struct byt_gpio *vg = gpiochip_get_data(
+ irq_desc_get_handler_data(desc));
+ struct irq_chip *chip = irq_data_get_irq_chip(data);
+ u32 base, pin;
+ void __iomem *reg;
+ unsigned long pending;
+ unsigned int virq;
+
+ /* check from GPIO controller which pin triggered the interrupt */
+ for (base = 0; base < vg->chip.ngpio; base += 32) {
+ reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG);
+
+ if (!reg) {
+ dev_warn(&vg->pdev->dev,
+ "Pin %i: could not retrieve interrupt status register\n",
+ base);
+ continue;
+ }
+
+ pending = readl(reg);
+ for_each_set_bit(pin, &pending, 32) {
+ virq = irq_find_mapping(vg->chip.irqdomain, base + pin);
+ generic_handle_irq(virq);
+ }
+ }
+ chip->irq_eoi(data);
+}
+
static void byt_gpio_irq_init_hw(struct byt_gpio *vg)
{
void __iomem *reg;
@@ -1639,8 +1541,18 @@ static void byt_gpio_irq_init_hw(struct byt_gpio *vg)
* do not use direct IRQ mode. This will prevent spurious
* interrupts from misconfigured pins.
*/
- for (i = 0; i < vg->chip.ngpio; i++) {
- value = readl(byt_gpio_reg(vg, i, BYT_CONF0_REG));
+ for (i = 0; i < vg->soc_data->npins; i++) {
+ unsigned int pin = vg->soc_data->pins[i].number;
+
+ reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
+ if (!reg) {
+ dev_warn(&vg->pdev->dev,
+ "Pin %i: could not retrieve conf0 register\n",
+ i);
+ continue;
+ }
+
+ value = readl(reg);
if ((value & BYT_PIN_MUX) == byt_get_gpio_mux(vg, i) &&
!(value & BYT_DIRECT_IRQ_EN)) {
byt_gpio_clear_triggering(vg, i);
@@ -1649,8 +1561,16 @@ static void byt_gpio_irq_init_hw(struct byt_gpio *vg)
}
/* clear interrupt status trigger registers */
- for (base = 0; base < vg->chip.ngpio; base += 32) {
+ for (base = 0; base < vg->soc_data->npins; base += 32) {
reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG);
+
+ if (!reg) {
+ dev_warn(&vg->pdev->dev,
+ "Pin %i: could not retrieve irq status reg\n",
+ base);
+ continue;
+ }
+
writel(0xffffffff, reg);
/* make sure trigger bits are cleared, if not then a pin
might be misconfigured in bios */
@@ -1661,82 +1581,47 @@ static void byt_gpio_irq_init_hw(struct byt_gpio *vg)
}
}
-static int byt_gpio_probe(struct platform_device *pdev)
+static int byt_gpio_probe(struct byt_gpio *vg)
{
- struct byt_gpio *vg;
struct gpio_chip *gc;
- struct resource *mem_rc, *irq_rc;
- struct device *dev = &pdev->dev;
- struct acpi_device *acpi_dev;
- struct pinctrl_gpio_range *range;
- acpi_handle handle = ACPI_HANDLE(dev);
+ struct resource *irq_rc;
int ret;
- if (acpi_bus_get_device(handle, &acpi_dev))
- return -ENODEV;
-
- vg = devm_kzalloc(dev, sizeof(struct byt_gpio), GFP_KERNEL);
- if (!vg) {
- dev_err(&pdev->dev, "can't allocate byt_gpio chip data\n");
- return -ENOMEM;
- }
-
- for (range = byt_ranges; range->name; range++) {
- if (!strcmp(acpi_dev->pnp.unique_id, range->name)) {
- vg->chip.ngpio = range->npins;
- vg->range = range;
- break;
- }
- }
-
- if (!vg->chip.ngpio || !vg->range)
- return -ENODEV;
-
- vg->pdev = pdev;
- platform_set_drvdata(pdev, vg);
-
- mem_rc = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- vg->reg_base = devm_ioremap_resource(dev, mem_rc);
- if (IS_ERR(vg->reg_base))
- return PTR_ERR(vg->reg_base);
-
- raw_spin_lock_init(&vg->lock);
-
- gc = &vg->chip;
- gc->label = dev_name(&pdev->dev);
- gc->owner = THIS_MODULE;
- gc->request = byt_gpio_request;
- gc->free = byt_gpio_free;
- gc->direction_input = byt_gpio_direction_input;
- gc->direction_output = byt_gpio_direction_output;
- gc->get = byt_gpio_get;
- gc->set = byt_gpio_set;
- gc->dbg_show = byt_gpio_dbg_show;
- gc->base = -1;
- gc->can_sleep = false;
- gc->parent = dev;
+ /* Set up gpio chip */
+ vg->chip = byt_gpio_chip;
+ gc = &vg->chip;
+ gc->label = dev_name(&vg->pdev->dev);
+ gc->base = -1;
+ gc->can_sleep = false;
+ gc->parent = &vg->pdev->dev;
+ gc->ngpio = vg->soc_data->npins;
#ifdef CONFIG_PM_SLEEP
- vg->saved_context = devm_kcalloc(&pdev->dev, gc->ngpio,
+ vg->saved_context = devm_kcalloc(&vg->pdev->dev, gc->ngpio,
sizeof(*vg->saved_context), GFP_KERNEL);
#endif
-
ret = gpiochip_add_data(gc, vg);
if (ret) {
- dev_err(&pdev->dev, "failed adding byt-gpio chip\n");
+ dev_err(&vg->pdev->dev, "failed adding byt-gpio chip\n");
return ret;
}
+ ret = gpiochip_add_pin_range(&vg->chip, dev_name(&vg->pdev->dev),
+ 0, 0, vg->soc_data->npins);
+ if (ret) {
+ dev_err(&vg->pdev->dev, "failed to add GPIO pin range\n");
+ goto fail;
+ }
+
/* set up interrupts */
- irq_rc = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+ irq_rc = platform_get_resource(vg->pdev, IORESOURCE_IRQ, 0);
if (irq_rc && irq_rc->start) {
byt_gpio_irq_init_hw(vg);
ret = gpiochip_irqchip_add(gc, &byt_irqchip, 0,
handle_simple_irq, IRQ_TYPE_NONE);
if (ret) {
- dev_err(dev, "failed to add irqchip\n");
- gpiochip_remove(gc);
- return ret;
+ dev_err(&vg->pdev->dev, "failed to add irqchip\n");
+ goto fail;
}
gpiochip_set_chained_irqchip(gc, &byt_irqchip,
@@ -1744,7 +1629,120 @@ static int byt_gpio_probe(struct platform_device *pdev)
byt_gpio_irq_handler);
}
- pm_runtime_enable(dev);
+ return ret;
+
+fail:
+ gpiochip_remove(&vg->chip);
+
+ return ret;
+}
+
+static int byt_set_soc_data(struct byt_gpio *vg,
+ const struct byt_pinctrl_soc_data *soc_data)
+{
+ int i;
+
+ vg->soc_data = soc_data;
+ vg->communities_copy = devm_kcalloc(&vg->pdev->dev,
+ soc_data->ncommunities,
+ sizeof(*vg->communities_copy),
+ GFP_KERNEL);
+ if (!vg->communities_copy)
+ return -ENOMEM;
+
+ for (i = 0; i < soc_data->ncommunities; i++) {
+ struct byt_community *comm = vg->communities_copy + i;
+ struct resource *mem_rc;
+
+ *comm = vg->soc_data->communities[i];
+
+ mem_rc = platform_get_resource(vg->pdev, IORESOURCE_MEM, 0);
+ comm->reg_base = devm_ioremap_resource(&vg->pdev->dev, mem_rc);
+ if (IS_ERR(comm->reg_base))
+ return PTR_ERR(comm->reg_base);
+ }
+
+ return 0;
+}
+
+static const struct acpi_device_id byt_gpio_acpi_match[] = {
+ { "INT33B2", (kernel_ulong_t)byt_soc_data },
+ { "INT33FC", (kernel_ulong_t)byt_soc_data },
+ { }
+};
+MODULE_DEVICE_TABLE(acpi, byt_gpio_acpi_match);
+
+static int byt_pinctrl_probe(struct platform_device *pdev)
+{
+ const struct byt_pinctrl_soc_data *soc_data = NULL;
+ const struct byt_pinctrl_soc_data **soc_table;
+ const struct acpi_device_id *acpi_id;
+ struct acpi_device *acpi_dev;
+ struct byt_gpio *vg;
+ int i, ret;
+
+ acpi_dev = ACPI_COMPANION(&pdev->dev);
+ if (!acpi_dev)
+ return -ENODEV;
+
+ acpi_id = acpi_match_device(byt_gpio_acpi_match, &pdev->dev);
+ if (!acpi_id)
+ return -ENODEV;
+
+ soc_table = (const struct byt_pinctrl_soc_data **)acpi_id->driver_data;
+
+ for (i = 0; soc_table[i]; i++) {
+ if (!strcmp(acpi_dev->pnp.unique_id, soc_table[i]->uid)) {
+ soc_data = soc_table[i];
+ break;
+ }
+ }
+
+ if (!soc_data)
+ return -ENODEV;
+
+ vg = devm_kzalloc(&pdev->dev, sizeof(*vg), GFP_KERNEL);
+ if (!vg)
+ return -ENOMEM;
+
+ vg->pdev = pdev;
+ ret = byt_set_soc_data(vg, soc_data);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to set soc data\n");
+ return ret;
+ }
+
+ vg->pctl_desc = byt_pinctrl_desc;
+ vg->pctl_desc.name = dev_name(&pdev->dev);
+ vg->pctl_desc.pins = vg->soc_data->pins;
+ vg->pctl_desc.npins = vg->soc_data->npins;
+
+ vg->pctl_dev = pinctrl_register(&vg->pctl_desc, &pdev->dev, vg);
+ if (IS_ERR(vg->pctl_dev)) {
+ dev_err(&pdev->dev, "failed to register pinctrl driver\n");
+ return PTR_ERR(vg->pctl_dev);
+ }
+
+ ret = byt_gpio_probe(vg);
+ if (ret) {
+ pinctrl_unregister(vg->pctl_dev);
+ return ret;
+ }
+
+ platform_set_drvdata(pdev, vg);
+ raw_spin_lock_init(&vg->lock);
+ pm_runtime_enable(&pdev->dev);
+
+ return 0;
+}
+
+static int byt_pinctrl_remove(struct platform_device *pdev)
+{
+ struct byt_gpio *vg = platform_get_drvdata(pdev);
+
+ pm_runtime_disable(&pdev->dev);
+ gpiochip_remove(&vg->chip);
+ pinctrl_unregister(vg->pctl_dev);
return 0;
}
@@ -1756,15 +1754,22 @@ static int byt_gpio_suspend(struct device *dev)
struct byt_gpio *vg = platform_get_drvdata(pdev);
int i;
- for (i = 0; i < vg->chip.ngpio; i++) {
+ for (i = 0; i < vg->soc_data->npins; i++) {
void __iomem *reg;
u32 value;
+ unsigned int pin = vg->soc_data->pins[i].number;
- reg = byt_gpio_reg(vg, i, BYT_CONF0_REG);
+ reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
+ if (!reg) {
+ dev_warn(&vg->pdev->dev,
+ "Pin %i: could not retrieve conf0 register\n",
+ i);
+ continue;
+ }
value = readl(reg) & BYT_CONF0_RESTORE_MASK;
vg->saved_context[i].conf0 = value;
- reg = byt_gpio_reg(vg, i, BYT_VAL_REG);
+ reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
value = readl(reg) & BYT_VAL_RESTORE_MASK;
vg->saved_context[i].val = value;
}
@@ -1778,11 +1783,18 @@ static int byt_gpio_resume(struct device *dev)
struct byt_gpio *vg = platform_get_drvdata(pdev);
int i;
- for (i = 0; i < vg->chip.ngpio; i++) {
+ for (i = 0; i < vg->soc_data->npins; i++) {
void __iomem *reg;
u32 value;
+ unsigned int pin = vg->soc_data->pins[i].number;
- reg = byt_gpio_reg(vg, i, BYT_CONF0_REG);
+ reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
+ if (!reg) {
+ dev_warn(&vg->pdev->dev,
+ "Pin %i: could not retrieve conf0 register\n",
+ i);
+ continue;
+ }
value = readl(reg);
if ((value & BYT_CONF0_RESTORE_MASK) !=
vg->saved_context[i].conf0) {
@@ -1792,7 +1804,7 @@ static int byt_gpio_resume(struct device *dev)
dev_info(dev, "restored pin %d conf0 %#08x", i, value);
}
- reg = byt_gpio_reg(vg, i, BYT_VAL_REG);
+ reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
value = readl(reg);
if ((value & BYT_VAL_RESTORE_MASK) !=
vg->saved_context[i].val) {
@@ -1830,26 +1842,9 @@ static const struct dev_pm_ops byt_gpio_pm_ops = {
NULL)
};
-static const struct acpi_device_id byt_gpio_acpi_match[] = {
- { "INT33B2", (kernel_ulong_t)byt_soc_data },
- { "INT33FC", (kernel_ulong_t)byt_soc_data },
- { }
-};
-MODULE_DEVICE_TABLE(acpi, byt_gpio_acpi_match);
-
-static int byt_gpio_remove(struct platform_device *pdev)
-{
- struct byt_gpio *vg = platform_get_drvdata(pdev);
-
- pm_runtime_disable(&pdev->dev);
- gpiochip_remove(&vg->chip);
-
- return 0;
-}
-
static struct platform_driver byt_gpio_driver = {
- .probe = byt_gpio_probe,
- .remove = byt_gpio_remove,
+ .probe = byt_pinctrl_probe,
+ .remove = byt_pinctrl_remove,
.driver = {
.name = "byt_gpio",
.pm = &byt_gpio_pm_ops,
--
1.9.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v2 6/6] pinctrl: baytrail: Add debounce configuration
2016-03-28 13:29 [PATCH v2 0/6] Add pinctrl support for Baytrail Cristina Ciocan
` (4 preceding siblings ...)
2016-03-28 13:29 ` [PATCH v2 5/6] pinctrl: baytrail: Register pin control handling Cristina Ciocan
@ 2016-03-28 13:29 ` Cristina Ciocan
2016-03-30 14:45 ` [PATCH v2 0/6] Add pinctrl support for Baytrail Mika Westerberg
6 siblings, 0 replies; 11+ messages in thread
From: Cristina Ciocan @ 2016-03-28 13:29 UTC (permalink / raw)
To: mathias.nyman, mika.westerberg, linux-gpio
Cc: linux-kernel, irina.tirdea, octavian.purdila, Cristina Ciocan
Make debounce setting and getting functionality available when
configurating a certain pin.
Signed-off-by: Cristina Ciocan <cristina.ciocan@intel.com>
---
drivers/pinctrl/intel/pinctrl-baytrail.c | 83 +++++++++++++++++++++++++++++++-
1 file changed, 81 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/intel/pinctrl-baytrail.c b/drivers/pinctrl/intel/pinctrl-baytrail.c
index 0ba28fd..f7ae57e 100644
--- a/drivers/pinctrl/intel/pinctrl-baytrail.c
+++ b/drivers/pinctrl/intel/pinctrl-baytrail.c
@@ -38,6 +38,7 @@
#define BYT_VAL_REG 0x008
#define BYT_DFT_REG 0x00c
#define BYT_INT_STAT_REG 0x800
+#define BYT_DEBOUNCE_REG 0x9d0
/* BYT_CONF0_REG register bits */
#define BYT_IODEN BIT(31)
@@ -45,6 +46,7 @@
#define BYT_TRIG_NEG BIT(26)
#define BYT_TRIG_POS BIT(25)
#define BYT_TRIG_LVL BIT(24)
+#define BYT_DEBOUNCE_EN BIT(20)
#define BYT_PULL_STR_SHIFT 9
#define BYT_PULL_STR_MASK (3 << BYT_PULL_STR_SHIFT)
#define BYT_PULL_STR_2K (0 << BYT_PULL_STR_SHIFT)
@@ -69,6 +71,16 @@
BYT_PIN_MUX)
#define BYT_VAL_RESTORE_MASK (BYT_DIR_MASK | BYT_LEVEL)
+/* BYT_DEBOUNCE_REG bits */
+#define BYT_DEBOUNCE_PULSE_MASK 0x7
+#define BYT_DEBOUNCE_PULSE_375US 1
+#define BYT_DEBOUNCE_PULSE_750US 2
+#define BYT_DEBOUNCE_PULSE_1500US 3
+#define BYT_DEBOUNCE_PULSE_3MS 4
+#define BYT_DEBOUNCE_PULSE_6MS 5
+#define BYT_DEBOUNCE_PULSE_12MS 6
+#define BYT_DEBOUNCE_PULSE_24MS 7
+
#define BYT_NGPIO_SCORE 102
#define BYT_NGPIO_NCORE 28
#define BYT_NGPIO_SUS 44
@@ -1078,7 +1090,7 @@ static int byt_pin_config_get(struct pinctrl_dev *pctl_dev, unsigned int offset,
void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
unsigned long flags;
- u32 conf, pull, val;
+ u32 conf, pull, val, debounce;
u16 arg = 0;
raw_spin_lock_irqsave(&vg->lock, flags);
@@ -1108,6 +1120,41 @@ static int byt_pin_config_get(struct pinctrl_dev *pctl_dev, unsigned int offset,
byt_get_pull_strength(conf, &arg);
break;
+ case PIN_CONFIG_INPUT_DEBOUNCE:
+ if (!(conf & BYT_DEBOUNCE_EN))
+ return -EINVAL;
+
+ raw_spin_lock_irqsave(&vg->lock, flags);
+ debounce = readl(byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG));
+ raw_spin_unlock_irqrestore(&vg->lock, flags);
+
+ switch (debounce & BYT_DEBOUNCE_PULSE_MASK) {
+ case BYT_DEBOUNCE_PULSE_375US:
+ arg = 375;
+ break;
+ case BYT_DEBOUNCE_PULSE_750US:
+ arg = 750;
+ break;
+ case BYT_DEBOUNCE_PULSE_1500US:
+ arg = 1500;
+ break;
+ case BYT_DEBOUNCE_PULSE_3MS:
+ arg = 3000;
+ break;
+ case BYT_DEBOUNCE_PULSE_6MS:
+ arg = 6000;
+ break;
+ case BYT_DEBOUNCE_PULSE_12MS:
+ arg = 12000;
+ break;
+ case BYT_DEBOUNCE_PULSE_24MS:
+ arg = 24000;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ break;
default:
return -ENOTSUPP;
}
@@ -1127,7 +1174,7 @@ static int byt_pin_config_set(struct pinctrl_dev *pctl_dev,
void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
unsigned long flags;
- u32 conf, val;
+ u32 conf, val, debounce;
int i, ret = 0;
raw_spin_lock_irqsave(&vg->lock, flags);
@@ -1187,6 +1234,38 @@ static int byt_pin_config_set(struct pinctrl_dev *pctl_dev,
ret = byt_set_pull_strength(&conf, arg);
break;
+ case PIN_CONFIG_INPUT_DEBOUNCE:
+ debounce = readl(byt_gpio_reg(vg, offset,
+ BYT_DEBOUNCE_REG));
+ conf &= ~BYT_DEBOUNCE_PULSE_MASK;
+
+ switch (arg) {
+ case 375:
+ conf |= BYT_DEBOUNCE_PULSE_375US;
+ break;
+ case 750:
+ conf |= BYT_DEBOUNCE_PULSE_750US;
+ break;
+ case 1500:
+ conf |= BYT_DEBOUNCE_PULSE_1500US;
+ break;
+ case 3000:
+ conf |= BYT_DEBOUNCE_PULSE_3MS;
+ break;
+ case 6000:
+ conf |= BYT_DEBOUNCE_PULSE_6MS;
+ break;
+ case 12000:
+ conf |= BYT_DEBOUNCE_PULSE_12MS;
+ break;
+ case 24000:
+ conf |= BYT_DEBOUNCE_PULSE_24MS;
+ break;
+ default:
+ ret = -EINVAL;
+ }
+
+ break;
default:
ret = -ENOTSUPP;
}
--
1.9.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH v2 1/6] pinctrl: baytrail: Add pin control data structures
2016-03-28 13:29 ` [PATCH v2 1/6] pinctrl: baytrail: Add pin control data structures Cristina Ciocan
@ 2016-03-30 11:15 ` Mika Westerberg
2016-03-30 11:33 ` Cristina Ciocan
0 siblings, 1 reply; 11+ messages in thread
From: Mika Westerberg @ 2016-03-30 11:15 UTC (permalink / raw)
To: Cristina Ciocan
Cc: mathias.nyman, linux-gpio, linux-kernel, irina.tirdea, octavian.purdila
On Mon, Mar 28, 2016 at 04:29:35PM +0300, Cristina Ciocan wrote:
> +/* SCORE pins */
> +static const struct pinctrl_pin_desc byt_score_pins[] = {
> + PINCTRL_PIN(0, "SATA_GP[0]"), /* GPIOC_0 */
> + PINCTRL_PIN(1, "SATA_GP[1]"), /* GPIOC_1 */
Maybe we should call these "SATA_GP0" and "SATA_GP1" like we do in other
Intel pinctrl drivers?
Also I don't think /* GPIOC_1 */ is really useful comment as that can be
derived already from the pin number.
Otherwise this looks good.
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v2 1/6] pinctrl: baytrail: Add pin control data structures
2016-03-30 11:15 ` Mika Westerberg
@ 2016-03-30 11:33 ` Cristina Ciocan
2016-03-30 11:42 ` Mika Westerberg
0 siblings, 1 reply; 11+ messages in thread
From: Cristina Ciocan @ 2016-03-30 11:33 UTC (permalink / raw)
To: Mika Westerberg
Cc: mathias.nyman, linux-gpio, linux-kernel, irina.tirdea, octavian.purdila
On 30.03.2016 14:15, Mika Westerberg wrote:
> On Mon, Mar 28, 2016 at 04:29:35PM +0300, Cristina Ciocan wrote:
>> +/* SCORE pins */
>> +static const struct pinctrl_pin_desc byt_score_pins[] = {
>> + PINCTRL_PIN(0, "SATA_GP[0]"), /* GPIOC_0 */
>> + PINCTRL_PIN(1, "SATA_GP[1]"), /* GPIOC_1 */
>
> Maybe we should call these "SATA_GP0" and "SATA_GP1" like we do in other
> Intel pinctrl drivers?
The names are directly taken form the public datasheet found at:
http://www.intel.com/content/www/us/en/embedded/products/bay-trail/atom-e3800-family-datasheet.html,
section 10.3, Ball Name and Function by Location.
I kept those names, even though they are not always pretty, so that teh
pins can be easily identified if someone searches them in the datasheet
for extra information.
>
> Also I don't think /* GPIOC_1 */ is really useful comment as that can be
> derived already from the pin number.
The issue here is that pins are not referenced by the same name in the
datasheet. In the above mentioned section (10.3), south core pins are
GPIO_S0_SC[<pin_number>], whereas in the GPIO section (39) they are
referenced as GPIOC_<pin_number>. I added the comments for the same
reasoning as above, easy search for datasheet-driver pin matching.
If this is not an issue, I can change both names and comments.
Thank you for the review.
>
> Otherwise this looks good.
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v2 1/6] pinctrl: baytrail: Add pin control data structures
2016-03-30 11:33 ` Cristina Ciocan
@ 2016-03-30 11:42 ` Mika Westerberg
0 siblings, 0 replies; 11+ messages in thread
From: Mika Westerberg @ 2016-03-30 11:42 UTC (permalink / raw)
To: Cristina Ciocan
Cc: mathias.nyman, linux-gpio, linux-kernel, irina.tirdea, octavian.purdila
On Wed, Mar 30, 2016 at 02:33:39PM +0300, Cristina Ciocan wrote:
> On 30.03.2016 14:15, Mika Westerberg wrote:
> > On Mon, Mar 28, 2016 at 04:29:35PM +0300, Cristina Ciocan wrote:
> >> +/* SCORE pins */
> >> +static const struct pinctrl_pin_desc byt_score_pins[] = {
> >> + PINCTRL_PIN(0, "SATA_GP[0]"), /* GPIOC_0 */
> >> + PINCTRL_PIN(1, "SATA_GP[1]"), /* GPIOC_1 */
> >
> > Maybe we should call these "SATA_GP0" and "SATA_GP1" like we do in other
> > Intel pinctrl drivers?
>
> The names are directly taken form the public datasheet found at:
> http://www.intel.com/content/www/us/en/embedded/products/bay-trail/atom-e3800-family-datasheet.html,
> section 10.3, Ball Name and Function by Location.
>
> I kept those names, even though they are not always pretty, so that teh
> pins can be easily identified if someone searches them in the datasheet
> for extra information.
Well, I think it is not too hard to find out that SATA_GP0 matches
SATA_GP[0] in the datasheet ;-)
> > Also I don't think /* GPIOC_1 */ is really useful comment as that can be
> > derived already from the pin number.
>
> The issue here is that pins are not referenced by the same name in the
> datasheet. In the above mentioned section (10.3), south core pins are
> GPIO_S0_SC[<pin_number>], whereas in the GPIO section (39) they are
> referenced as GPIOC_<pin_number>. I added the comments for the same
> reasoning as above, easy search for datasheet-driver pin matching.
And the <pin_number> in both cases is the same.
> If this is not an issue, I can change both names and comments.
I'm fine either way. Just wanted to mention because other Intel pinctrl
drivers use slightly different naming.
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v2 0/6] Add pinctrl support for Baytrail
2016-03-28 13:29 [PATCH v2 0/6] Add pinctrl support for Baytrail Cristina Ciocan
` (5 preceding siblings ...)
2016-03-28 13:29 ` [PATCH v2 6/6] pinctrl: baytrail: Add debounce configuration Cristina Ciocan
@ 2016-03-30 14:45 ` Mika Westerberg
6 siblings, 0 replies; 11+ messages in thread
From: Mika Westerberg @ 2016-03-30 14:45 UTC (permalink / raw)
To: Cristina Ciocan
Cc: mathias.nyman, linux-gpio, linux-kernel, irina.tirdea, octavian.purdila
On Mon, Mar 28, 2016 at 04:29:34PM +0300, Cristina Ciocan wrote:
> Add support for pin control (pin muxing and pin configuration) for Baytrail
> platform.
>
> It follows the design in pinctrl-intel.c, but could not use the
> implementation in pinctrl-intel since there were significant differences:
> - gpio pin pads are not ordered
> - per group functions: for setting a certain mode, there are groups
> that need setting pins with different values; for instance, for
> setting USB ULPI pins to GPIO function, pin 2 (GPIO_SUS1) needs
> to be set to function 1, wihle all other from the group need to be
> set to 0
> - communities only need pin base and count as specific data
> - irq set type only clears all flags, while the actual type setting
> is made in the byt_irq_unmask function, which does not comply with
> the intel pinctrl implementation
>
> Changes from v1:
> - fix reg, reg_val and byt_soc_data not used variables warnings
>
> Cristina Ciocan (6):
> pinctrl: baytrail: Add pin control data structures
> pinctrl: baytrail: Add pin control operations
> pinctrl: baytrail: Update gpio chip operations
> pinctrl: baytrail: Update irq chip operations
> pinctrl: baytrail: Register pin control handling
> pinctrl: baytrail: Add debounce configuration
Apart of the pin naming I commented, this patch series finally
brings real pinctrl support to the misnamed baytrail GPIO driver which
is definitely the right thing to do :)
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2016-03-30 14:45 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-03-28 13:29 [PATCH v2 0/6] Add pinctrl support for Baytrail Cristina Ciocan
2016-03-28 13:29 ` [PATCH v2 1/6] pinctrl: baytrail: Add pin control data structures Cristina Ciocan
2016-03-30 11:15 ` Mika Westerberg
2016-03-30 11:33 ` Cristina Ciocan
2016-03-30 11:42 ` Mika Westerberg
2016-03-28 13:29 ` [PATCH v2 2/6] pinctrl: baytrail: Add pin control operations Cristina Ciocan
2016-03-28 13:29 ` [PATCH v2 3/6] pinctrl: baytrail: Update gpio chip operations Cristina Ciocan
2016-03-28 13:29 ` [PATCH v2 4/6] pinctrl: baytrail: Update irq " Cristina Ciocan
2016-03-28 13:29 ` [PATCH v2 5/6] pinctrl: baytrail: Register pin control handling Cristina Ciocan
2016-03-28 13:29 ` [PATCH v2 6/6] pinctrl: baytrail: Add debounce configuration Cristina Ciocan
2016-03-30 14:45 ` [PATCH v2 0/6] Add pinctrl support for Baytrail Mika Westerberg
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