[PATCH v2 0/8] add TCON and Vybrid support

[PATCH v2 0/8] add TCON and Vybrid support

[Stefan Agner]

This patchset adds the missing pieces to make the Freescale
DCU DRM driver work on Freescale Vybrid.

Foremost, it adds support for the timing controller (TCON)
module. The module is between the Display Controller and the
actual output pins. It allows to alter the timings for RAW
TFT displays, but can also operate in a bypass mode. This
change has only support for the bypass mode.

Earlier variants of the DCU DRM driver configured the TCON
module in bypass mode, however this has been removed and
postponed. The last variant with the TCON code was v9:
https://lkml.org/lkml/2015/7/13/242

The patchset also fixes the DCU related clocks in the Vybrid
clock tree and makes use of the common clock framework for
the pixelclock divider.

Testing on LS1021a welcomeing!

Changes since v1:
- Properly disable clocks on errors
- Create clear seperation of pixel clock and bus clock
- Simplified TCON driver by removing suspend/resume
  capabilities (encoder disable/enable makes sure that
  TCON bypass gets disabled/reenabled on suspend)
- Use common clock framework to create a divider clock
  which represents the DCU internal pixel clock divider

Stefan Agner (8):
  ARM: imx: clk-vf610: fix DCU clock tree
  ARM: imx: clk-vf610: add TCON ipg clock
  drm/fsl-dcu: disable clock on initialization failure and remove
  drm/fsl-dcu: add extra clock for pixel clock
  drm/fsl-dcu: use common clock framework for pixel clock divider
  drm/fsl-dcu: add TCON driver
  ARM: dts: vf610: add display nodes
  ARM: dts: vf610-colibri: enable display controller

 .../devicetree/bindings/display/fsl,dcu.txt        |   6 ++
 .../devicetree/bindings/display/fsl,tcon.txt       |  18 ++++
 arch/arm/boot/dts/vf-colibri-eval-v3.dtsi          |  16 +++
 arch/arm/boot/dts/vf-colibri.dtsi                  |  33 +++++++
 arch/arm/boot/dts/vfxxx.dtsi                       |  19 ++++
 drivers/clk/imx/clk-vf610.c                        |   7 +-
 drivers/gpu/drm/fsl-dcu/Makefile                   |   3 +-
 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c         |   7 +-
 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c          |  73 ++++++++++----
 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h          |   2 +
 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c          |  11 +++
 drivers/gpu/drm/fsl-dcu/fsl_tcon.c                 | 108 +++++++++++++++++++++
 drivers/gpu/drm/fsl-dcu/fsl_tcon.h                 |  33 +++++++
 include/dt-bindings/clock/vf610-clock.h            |   4 +-
 14 files changed, 311 insertions(+), 29 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/display/fsl,tcon.txt
 create mode 100644 drivers/gpu/drm/fsl-dcu/fsl_tcon.c
 create mode 100644 drivers/gpu/drm/fsl-dcu/fsl_tcon.h

-- 
2.7.4

[PATCH v2 0/8] add TCON and Vybrid support

[Stefan Agner]

This patchset adds the missing pieces to make the Freescale
DCU DRM driver work on Freescale Vybrid.

Foremost, it adds support for the timing controller (TCON)
module. The module is between the Display Controller and the
actual output pins. It allows to alter the timings for RAW
TFT displays, but can also operate in a bypass mode. This
change has only support for the bypass mode.

Earlier variants of the DCU DRM driver configured the TCON
module in bypass mode, however this has been removed and
postponed. The last variant with the TCON code was v9:
https://lkml.org/lkml/2015/7/13/242

The patchset also fixes the DCU related clocks in the Vybrid
clock tree and makes use of the common clock framework for
the pixelclock divider.

Testing on LS1021a welcomeing!

Changes since v1:
- Properly disable clocks on errors
- Create clear seperation of pixel clock and bus clock
- Simplified TCON driver by removing suspend/resume
  capabilities (encoder disable/enable makes sure that
  TCON bypass gets disabled/reenabled on suspend)
- Use common clock framework to create a divider clock
  which represents the DCU internal pixel clock divider

Stefan Agner (8):
  ARM: imx: clk-vf610: fix DCU clock tree
  ARM: imx: clk-vf610: add TCON ipg clock
  drm/fsl-dcu: disable clock on initialization failure and remove
  drm/fsl-dcu: add extra clock for pixel clock
  drm/fsl-dcu: use common clock framework for pixel clock divider
  drm/fsl-dcu: add TCON driver
  ARM: dts: vf610: add display nodes
  ARM: dts: vf610-colibri: enable display controller

 .../devicetree/bindings/display/fsl,dcu.txt        |   6 ++
 .../devicetree/bindings/display/fsl,tcon.txt       |  18 ++++
 arch/arm/boot/dts/vf-colibri-eval-v3.dtsi          |  16 +++
 arch/arm/boot/dts/vf-colibri.dtsi                  |  33 +++++++
 arch/arm/boot/dts/vfxxx.dtsi                       |  19 ++++
 drivers/clk/imx/clk-vf610.c                        |   7 +-
 drivers/gpu/drm/fsl-dcu/Makefile                   |   3 +-
 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c         |   7 +-
 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c          |  73 ++++++++++----
 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h          |   2 +
 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c          |  11 +++
 drivers/gpu/drm/fsl-dcu/fsl_tcon.c                 | 108 +++++++++++++++++++++
 drivers/gpu/drm/fsl-dcu/fsl_tcon.h                 |  33 +++++++
 include/dt-bindings/clock/vf610-clock.h            |   4 +-
 14 files changed, 311 insertions(+), 29 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/display/fsl,tcon.txt
 create mode 100644 drivers/gpu/drm/fsl-dcu/fsl_tcon.c
 create mode 100644 drivers/gpu/drm/fsl-dcu/fsl_tcon.h

-- 
2.7.4

_______________________________________________
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

[PATCH v2 0/8] add TCON and Vybrid support

[Stefan Agner]

This patchset adds the missing pieces to make the Freescale
DCU DRM driver work on Freescale Vybrid.

Foremost, it adds support for the timing controller (TCON)
module. The module is between the Display Controller and the
actual output pins. It allows to alter the timings for RAW
TFT displays, but can also operate in a bypass mode. This
change has only support for the bypass mode.

Earlier variants of the DCU DRM driver configured the TCON
module in bypass mode, however this has been removed and
postponed. The last variant with the TCON code was v9:
https://lkml.org/lkml/2015/7/13/242

The patchset also fixes the DCU related clocks in the Vybrid
clock tree and makes use of the common clock framework for
the pixelclock divider.

Testing on LS1021a welcomeing!

Changes since v1:
- Properly disable clocks on errors
- Create clear seperation of pixel clock and bus clock
- Simplified TCON driver by removing suspend/resume
  capabilities (encoder disable/enable makes sure that
  TCON bypass gets disabled/reenabled on suspend)
- Use common clock framework to create a divider clock
  which represents the DCU internal pixel clock divider

Stefan Agner (8):
  ARM: imx: clk-vf610: fix DCU clock tree
  ARM: imx: clk-vf610: add TCON ipg clock
  drm/fsl-dcu: disable clock on initialization failure and remove
  drm/fsl-dcu: add extra clock for pixel clock
  drm/fsl-dcu: use common clock framework for pixel clock divider
  drm/fsl-dcu: add TCON driver
  ARM: dts: vf610: add display nodes
  ARM: dts: vf610-colibri: enable display controller

 .../devicetree/bindings/display/fsl,dcu.txt        |   6 ++
 .../devicetree/bindings/display/fsl,tcon.txt       |  18 ++++
 arch/arm/boot/dts/vf-colibri-eval-v3.dtsi          |  16 +++
 arch/arm/boot/dts/vf-colibri.dtsi                  |  33 +++++++
 arch/arm/boot/dts/vfxxx.dtsi                       |  19 ++++
 drivers/clk/imx/clk-vf610.c                        |   7 +-
 drivers/gpu/drm/fsl-dcu/Makefile                   |   3 +-
 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c         |   7 +-
 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c          |  73 ++++++++++----
 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h          |   2 +
 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c          |  11 +++
 drivers/gpu/drm/fsl-dcu/fsl_tcon.c                 | 108 +++++++++++++++++++++
 drivers/gpu/drm/fsl-dcu/fsl_tcon.h                 |  33 +++++++
 include/dt-bindings/clock/vf610-clock.h            |   4 +-
 14 files changed, 311 insertions(+), 29 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/display/fsl,tcon.txt
 create mode 100644 drivers/gpu/drm/fsl-dcu/fsl_tcon.c
 create mode 100644 drivers/gpu/drm/fsl-dcu/fsl_tcon.h

-- 
2.7.4

[PATCH v2 1/8] ARM: imx: clk-vf610: fix DCU clock tree

[Stefan Agner]

Similar to an earlier fix for the SAI clocks, the DCU clock hierarchy
mixes the bus clock with the display controllers pixel clock. Tests
have shown that the gates in CCM_CCGR3/9 registers do not control
the DCU pixel clock, but only the register access clock (bus clock).

Fix this by defining the parent clock of VF610_CLK_DCUx to be the bus
clock (ipg_bus).

Since the clock has not been used far, there are no further changes
needed.

Signed-off-by: Stefan Agner <stefan@agner.ch>
---
 drivers/clk/imx/clk-vf610.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/imx/clk-vf610.c b/drivers/clk/imx/clk-vf610.c
index 0a94d96..426fde2 100644
--- a/drivers/clk/imx/clk-vf610.c
+++ b/drivers/clk/imx/clk-vf610.c
@@ -321,11 +321,11 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
 	clk[VF610_CLK_DCU0_SEL] = imx_clk_mux("dcu0_sel", CCM_CSCMR1, 28, 1, dcu_sels, 2);
 	clk[VF610_CLK_DCU0_EN] = imx_clk_gate("dcu0_en", "dcu0_sel", CCM_CSCDR3, 19);
 	clk[VF610_CLK_DCU0_DIV] = imx_clk_divider("dcu0_div", "dcu0_en", CCM_CSCDR3, 16, 3);
-	clk[VF610_CLK_DCU0] = imx_clk_gate2("dcu0", "dcu0_div", CCM_CCGR3, CCM_CCGRx_CGn(8));
+	clk[VF610_CLK_DCU0] = imx_clk_gate2("dcu0", "ipg_bus", CCM_CCGR3, CCM_CCGRx_CGn(8));
 	clk[VF610_CLK_DCU1_SEL] = imx_clk_mux("dcu1_sel", CCM_CSCMR1, 29, 1, dcu_sels, 2);
 	clk[VF610_CLK_DCU1_EN] = imx_clk_gate("dcu1_en", "dcu1_sel", CCM_CSCDR3, 23);
 	clk[VF610_CLK_DCU1_DIV] = imx_clk_divider("dcu1_div", "dcu1_en", CCM_CSCDR3, 20, 3);
-	clk[VF610_CLK_DCU1] = imx_clk_gate2("dcu1", "dcu1_div", CCM_CCGR9, CCM_CCGRx_CGn(8));
+	clk[VF610_CLK_DCU1] = imx_clk_gate2("dcu1", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(8));
 
 	clk[VF610_CLK_ESAI_SEL] = imx_clk_mux("esai_sel", CCM_CSCMR1, 20, 2, esai_sels, 4);
 	clk[VF610_CLK_ESAI_EN] = imx_clk_gate("esai_en", "esai_sel", CCM_CSCDR2, 30);
-- 
2.7.4

[PATCH v2 1/8] ARM: imx: clk-vf610: fix DCU clock tree

[Stefan Agner]

Similar to an earlier fix for the SAI clocks, the DCU clock hierarchy
mixes the bus clock with the display controllers pixel clock. Tests
have shown that the gates in CCM_CCGR3/9 registers do not control
the DCU pixel clock, but only the register access clock (bus clock).

Fix this by defining the parent clock of VF610_CLK_DCUx to be the bus
clock (ipg_bus).

Since the clock has not been used far, there are no further changes
needed.

Signed-off-by: Stefan Agner <stefan@agner.ch>
---
 drivers/clk/imx/clk-vf610.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/imx/clk-vf610.c b/drivers/clk/imx/clk-vf610.c
index 0a94d96..426fde2 100644
--- a/drivers/clk/imx/clk-vf610.c
+++ b/drivers/clk/imx/clk-vf610.c
@@ -321,11 +321,11 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
 	clk[VF610_CLK_DCU0_SEL] = imx_clk_mux("dcu0_sel", CCM_CSCMR1, 28, 1, dcu_sels, 2);
 	clk[VF610_CLK_DCU0_EN] = imx_clk_gate("dcu0_en", "dcu0_sel", CCM_CSCDR3, 19);
 	clk[VF610_CLK_DCU0_DIV] = imx_clk_divider("dcu0_div", "dcu0_en", CCM_CSCDR3, 16, 3);
-	clk[VF610_CLK_DCU0] = imx_clk_gate2("dcu0", "dcu0_div", CCM_CCGR3, CCM_CCGRx_CGn(8));
+	clk[VF610_CLK_DCU0] = imx_clk_gate2("dcu0", "ipg_bus", CCM_CCGR3, CCM_CCGRx_CGn(8));
 	clk[VF610_CLK_DCU1_SEL] = imx_clk_mux("dcu1_sel", CCM_CSCMR1, 29, 1, dcu_sels, 2);
 	clk[VF610_CLK_DCU1_EN] = imx_clk_gate("dcu1_en", "dcu1_sel", CCM_CSCDR3, 23);
 	clk[VF610_CLK_DCU1_DIV] = imx_clk_divider("dcu1_div", "dcu1_en", CCM_CSCDR3, 20, 3);
-	clk[VF610_CLK_DCU1] = imx_clk_gate2("dcu1", "dcu1_div", CCM_CCGR9, CCM_CCGRx_CGn(8));
+	clk[VF610_CLK_DCU1] = imx_clk_gate2("dcu1", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(8));
 
 	clk[VF610_CLK_ESAI_SEL] = imx_clk_mux("esai_sel", CCM_CSCMR1, 20, 2, esai_sels, 4);
 	clk[VF610_CLK_ESAI_EN] = imx_clk_gate("esai_en", "esai_sel", CCM_CSCDR2, 30);
-- 
2.7.4

[PATCH v2 2/8] ARM: imx: clk-vf610: add TCON ipg clock

[Stefan Agner]

Add the ipg (bus) clock for the TCON modules (Timing Controller). This
module is required by the new DCU DRM driver, since the display signals
pass through TCON.

Signed-off-by: Stefan Agner <stefan@agner.ch>
---
 drivers/clk/imx/clk-vf610.c             | 3 +++
 include/dt-bindings/clock/vf610-clock.h | 4 +++-
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/imx/clk-vf610.c b/drivers/clk/imx/clk-vf610.c
index 426fde2..43be1cf 100644
--- a/drivers/clk/imx/clk-vf610.c
+++ b/drivers/clk/imx/clk-vf610.c
@@ -327,6 +327,9 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
 	clk[VF610_CLK_DCU1_DIV] = imx_clk_divider("dcu1_div", "dcu1_en", CCM_CSCDR3, 20, 3);
 	clk[VF610_CLK_DCU1] = imx_clk_gate2("dcu1", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(8));
 
+	clk[VF610_CLK_TCON0] = imx_clk_gate2("tcon0", "platform_bus", CCM_CCGR1, CCM_CCGRx_CGn(13));
+	clk[VF610_CLK_TCON1] = imx_clk_gate2("tcon1", "platform_bus", CCM_CCGR7, CCM_CCGRx_CGn(13));
+
 	clk[VF610_CLK_ESAI_SEL] = imx_clk_mux("esai_sel", CCM_CSCMR1, 20, 2, esai_sels, 4);
 	clk[VF610_CLK_ESAI_EN] = imx_clk_gate("esai_en", "esai_sel", CCM_CSCDR2, 30);
 	clk[VF610_CLK_ESAI_DIV] = imx_clk_divider("esai_div", "esai_en", CCM_CSCDR2, 24, 4);
diff --git a/include/dt-bindings/clock/vf610-clock.h b/include/dt-bindings/clock/vf610-clock.h
index 56c16aa..fbe17cc 100644
--- a/include/dt-bindings/clock/vf610-clock.h
+++ b/include/dt-bindings/clock/vf610-clock.h
@@ -195,6 +195,8 @@
 #define VF610_CLK_SNVS			182
 #define VF610_CLK_DAP			183
 #define VF610_CLK_OCOTP         184
-#define VF610_CLK_END			185
+#define VF610_CLK_TCON0			185
+#define VF610_CLK_TCON1			186
+#define VF610_CLK_END			187
 
 #endif /* __DT_BINDINGS_CLOCK_VF610_H */
-- 
2.7.4

[PATCH v2 2/8] ARM: imx: clk-vf610: add TCON ipg clock

[Stefan Agner]

Add the ipg (bus) clock for the TCON modules (Timing Controller). This
module is required by the new DCU DRM driver, since the display signals
pass through TCON.

Signed-off-by: Stefan Agner <stefan@agner.ch>
---
 drivers/clk/imx/clk-vf610.c             | 3 +++
 include/dt-bindings/clock/vf610-clock.h | 4 +++-
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/imx/clk-vf610.c b/drivers/clk/imx/clk-vf610.c
index 426fde2..43be1cf 100644
--- a/drivers/clk/imx/clk-vf610.c
+++ b/drivers/clk/imx/clk-vf610.c
@@ -327,6 +327,9 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
 	clk[VF610_CLK_DCU1_DIV] = imx_clk_divider("dcu1_div", "dcu1_en", CCM_CSCDR3, 20, 3);
 	clk[VF610_CLK_DCU1] = imx_clk_gate2("dcu1", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(8));
 
+	clk[VF610_CLK_TCON0] = imx_clk_gate2("tcon0", "platform_bus", CCM_CCGR1, CCM_CCGRx_CGn(13));
+	clk[VF610_CLK_TCON1] = imx_clk_gate2("tcon1", "platform_bus", CCM_CCGR7, CCM_CCGRx_CGn(13));
+
 	clk[VF610_CLK_ESAI_SEL] = imx_clk_mux("esai_sel", CCM_CSCMR1, 20, 2, esai_sels, 4);
 	clk[VF610_CLK_ESAI_EN] = imx_clk_gate("esai_en", "esai_sel", CCM_CSCDR2, 30);
 	clk[VF610_CLK_ESAI_DIV] = imx_clk_divider("esai_div", "esai_en", CCM_CSCDR2, 24, 4);
diff --git a/include/dt-bindings/clock/vf610-clock.h b/include/dt-bindings/clock/vf610-clock.h
index 56c16aa..fbe17cc 100644
--- a/include/dt-bindings/clock/vf610-clock.h
+++ b/include/dt-bindings/clock/vf610-clock.h
@@ -195,6 +195,8 @@
 #define VF610_CLK_SNVS			182
 #define VF610_CLK_DAP			183
 #define VF610_CLK_OCOTP         184
-#define VF610_CLK_END			185
+#define VF610_CLK_TCON0			185
+#define VF610_CLK_TCON1			186
+#define VF610_CLK_END			187
 
 #endif /* __DT_BINDINGS_CLOCK_VF610_H */
-- 
2.7.4

[PATCH v2 3/8] drm/fsl-dcu: disable clock on initialization failure and remove

[Stefan Agner]

Fix error handling during probe by reordering initialization and
adding a error path which disables clock again. Also disable the
clock on remove.

Signed-off-by: Stefan Agner <stefan@agner.ch>
---
 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c | 44 +++++++++++++++----------------
 1 file changed, 21 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
index e8d9337..f2a9c1b 100644
--- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
+++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
@@ -290,6 +290,11 @@ static int fsl_dcu_drm_probe(struct platform_device *pdev)
 	if (!fsl_dev)
 		return -ENOMEM;
 
+	id = of_match_node(fsl_dcu_of_match, pdev->dev.of_node);
+	if (!id)
+		return -ENODEV;
+	fsl_dev->soc = id->data;
+
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	if (!res) {
 		dev_err(dev, "could not get memory IO resource\n");
@@ -308,39 +313,29 @@ static int fsl_dcu_drm_probe(struct platform_device *pdev)
 		return -ENXIO;
 	}
 
+	fsl_dev->regmap = devm_regmap_init_mmio(dev, base,
+			&fsl_dcu_regmap_config);
+	if (IS_ERR(fsl_dev->regmap)) {
+		dev_err(dev, "regmap init failed\n");
+		return PTR_ERR(fsl_dev->regmap);
+	}
+
 	fsl_dev->clk = devm_clk_get(dev, "dcu");
 	if (IS_ERR(fsl_dev->clk)) {
-		ret = PTR_ERR(fsl_dev->clk);
 		dev_err(dev, "failed to get dcu clock\n");
-		return ret;
-	}
-	ret = clk_prepare(fsl_dev->clk);
-	if (ret < 0) {
-		dev_err(dev, "failed to prepare dcu clk\n");
-		return ret;
+		return PTR_ERR(fsl_dev->clk);
 	}
-	ret = clk_enable(fsl_dev->clk);
+	ret = clk_prepare_enable(fsl_dev->clk);
 	if (ret < 0) {
 		dev_err(dev, "failed to enable dcu clk\n");
-		clk_unprepare(fsl_dev->clk);
 		return ret;
 	}
 
-	fsl_dev->regmap = devm_regmap_init_mmio(dev, base,
-			&fsl_dcu_regmap_config);
-	if (IS_ERR(fsl_dev->regmap)) {
-		dev_err(dev, "regmap init failed\n");
-		return PTR_ERR(fsl_dev->regmap);
-	}
-
-	id = of_match_node(fsl_dcu_of_match, pdev->dev.of_node);
-	if (!id)
-		return -ENODEV;
-	fsl_dev->soc = id->data;
-
 	drm = drm_dev_alloc(driver, dev);
-	if (!drm)
-		return -ENOMEM;
+	if (!drm) {
+		ret = -ENOMEM;
+		goto disable_clk;
+	}
 
 	fsl_dev->dev = dev;
 	fsl_dev->drm = drm;
@@ -360,6 +355,8 @@ static int fsl_dcu_drm_probe(struct platform_device *pdev)
 
 unref:
 	drm_dev_unref(drm);
+disable_clk:
+	clk_disable_unprepare(fsl_dev->clk);
 	return ret;
 }
 
@@ -367,6 +364,7 @@ static int fsl_dcu_drm_remove(struct platform_device *pdev)
 {
 	struct fsl_dcu_drm_device *fsl_dev = platform_get_drvdata(pdev);
 
+	clk_disable_unprepare(fsl_dev->clk);
 	drm_put_dev(fsl_dev->drm);
 
 	return 0;
-- 
2.7.4

[PATCH v2 3/8] drm/fsl-dcu: disable clock on initialization failure and remove

[Stefan Agner]

Fix error handling during probe by reordering initialization and
adding a error path which disables clock again. Also disable the
clock on remove.

Signed-off-by: Stefan Agner <stefan-XLVq0VzYD2Y@public.gmane.org>
---
 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c | 44 +++++++++++++++----------------
 1 file changed, 21 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
index e8d9337..f2a9c1b 100644
--- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
+++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
@@ -290,6 +290,11 @@ static int fsl_dcu_drm_probe(struct platform_device *pdev)
 	if (!fsl_dev)
 		return -ENOMEM;
 
+	id = of_match_node(fsl_dcu_of_match, pdev->dev.of_node);
+	if (!id)
+		return -ENODEV;
+	fsl_dev->soc = id->data;
+
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	if (!res) {
 		dev_err(dev, "could not get memory IO resource\n");
@@ -308,39 +313,29 @@ static int fsl_dcu_drm_probe(struct platform_device *pdev)
 		return -ENXIO;
 	}
 
+	fsl_dev->regmap = devm_regmap_init_mmio(dev, base,
+			&fsl_dcu_regmap_config);
+	if (IS_ERR(fsl_dev->regmap)) {
+		dev_err(dev, "regmap init failed\n");
+		return PTR_ERR(fsl_dev->regmap);
+	}
+
 	fsl_dev->clk = devm_clk_get(dev, "dcu");
 	if (IS_ERR(fsl_dev->clk)) {
-		ret = PTR_ERR(fsl_dev->clk);
 		dev_err(dev, "failed to get dcu clock\n");
-		return ret;
-	}
-	ret = clk_prepare(fsl_dev->clk);
-	if (ret < 0) {
-		dev_err(dev, "failed to prepare dcu clk\n");
-		return ret;
+		return PTR_ERR(fsl_dev->clk);
 	}
-	ret = clk_enable(fsl_dev->clk);
+	ret = clk_prepare_enable(fsl_dev->clk);
 	if (ret < 0) {
 		dev_err(dev, "failed to enable dcu clk\n");
-		clk_unprepare(fsl_dev->clk);
 		return ret;
 	}
 
-	fsl_dev->regmap = devm_regmap_init_mmio(dev, base,
-			&fsl_dcu_regmap_config);
-	if (IS_ERR(fsl_dev->regmap)) {
-		dev_err(dev, "regmap init failed\n");
-		return PTR_ERR(fsl_dev->regmap);
-	}
-
-	id = of_match_node(fsl_dcu_of_match, pdev->dev.of_node);
-	if (!id)
-		return -ENODEV;
-	fsl_dev->soc = id->data;
-
 	drm = drm_dev_alloc(driver, dev);
-	if (!drm)
-		return -ENOMEM;
+	if (!drm) {
+		ret = -ENOMEM;
+		goto disable_clk;
+	}
 
 	fsl_dev->dev = dev;
 	fsl_dev->drm = drm;
@@ -360,6 +355,8 @@ static int fsl_dcu_drm_probe(struct platform_device *pdev)
 
 unref:
 	drm_dev_unref(drm);
+disable_clk:
+	clk_disable_unprepare(fsl_dev->clk);
 	return ret;
 }
 
@@ -367,6 +364,7 @@ static int fsl_dcu_drm_remove(struct platform_device *pdev)
 {
 	struct fsl_dcu_drm_device *fsl_dev = platform_get_drvdata(pdev);
 
+	clk_disable_unprepare(fsl_dev->clk);
 	drm_put_dev(fsl_dev->drm);
 
 	return 0;
-- 
2.7.4

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[PATCH v2 3/8] drm/fsl-dcu: disable clock on initialization failure and remove

[Stefan Agner]

Fix error handling during probe by reordering initialization and
adding a error path which disables clock again. Also disable the
clock on remove.

Signed-off-by: Stefan Agner <stefan@agner.ch>
---
 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c | 44 +++++++++++++++----------------
 1 file changed, 21 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
index e8d9337..f2a9c1b 100644
--- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
+++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
@@ -290,6 +290,11 @@ static int fsl_dcu_drm_probe(struct platform_device *pdev)
 	if (!fsl_dev)
 		return -ENOMEM;
 
+	id = of_match_node(fsl_dcu_of_match, pdev->dev.of_node);
+	if (!id)
+		return -ENODEV;
+	fsl_dev->soc = id->data;
+
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	if (!res) {
 		dev_err(dev, "could not get memory IO resource\n");
@@ -308,39 +313,29 @@ static int fsl_dcu_drm_probe(struct platform_device *pdev)
 		return -ENXIO;
 	}
 
+	fsl_dev->regmap = devm_regmap_init_mmio(dev, base,
+			&fsl_dcu_regmap_config);
+	if (IS_ERR(fsl_dev->regmap)) {
+		dev_err(dev, "regmap init failed\n");
+		return PTR_ERR(fsl_dev->regmap);
+	}
+
 	fsl_dev->clk = devm_clk_get(dev, "dcu");
 	if (IS_ERR(fsl_dev->clk)) {
-		ret = PTR_ERR(fsl_dev->clk);
 		dev_err(dev, "failed to get dcu clock\n");
-		return ret;
-	}
-	ret = clk_prepare(fsl_dev->clk);
-	if (ret < 0) {
-		dev_err(dev, "failed to prepare dcu clk\n");
-		return ret;
+		return PTR_ERR(fsl_dev->clk);
 	}
-	ret = clk_enable(fsl_dev->clk);
+	ret = clk_prepare_enable(fsl_dev->clk);
 	if (ret < 0) {
 		dev_err(dev, "failed to enable dcu clk\n");
-		clk_unprepare(fsl_dev->clk);
 		return ret;
 	}
 
-	fsl_dev->regmap = devm_regmap_init_mmio(dev, base,
-			&fsl_dcu_regmap_config);
-	if (IS_ERR(fsl_dev->regmap)) {
-		dev_err(dev, "regmap init failed\n");
-		return PTR_ERR(fsl_dev->regmap);
-	}
-
-	id = of_match_node(fsl_dcu_of_match, pdev->dev.of_node);
-	if (!id)
-		return -ENODEV;
-	fsl_dev->soc = id->data;
-
 	drm = drm_dev_alloc(driver, dev);
-	if (!drm)
-		return -ENOMEM;
+	if (!drm) {
+		ret = -ENOMEM;
+		goto disable_clk;
+	}
 
 	fsl_dev->dev = dev;
 	fsl_dev->drm = drm;
@@ -360,6 +355,8 @@ static int fsl_dcu_drm_probe(struct platform_device *pdev)
 
 unref:
 	drm_dev_unref(drm);
+disable_clk:
+	clk_disable_unprepare(fsl_dev->clk);
 	return ret;
 }
 
@@ -367,6 +364,7 @@ static int fsl_dcu_drm_remove(struct platform_device *pdev)
 {
 	struct fsl_dcu_drm_device *fsl_dev = platform_get_drvdata(pdev);
 
+	clk_disable_unprepare(fsl_dev->clk);
 	drm_put_dev(fsl_dev->drm);
 
 	return 0;
-- 
2.7.4

[PATCH v2 4/8] drm/fsl-dcu: add extra clock for pixel clock

[Stefan Agner]

The Vybrid DCU variant has two independent clock inputs, one
for the registers (IPG bus clock) and one for the pixel clock.
Support this distinction in the DCU DRM driver while staying
backward compatible with devices providing only a single clock
(e.g. LS1021a SoC's).

Signed-off-by: Stefan Agner <stefan@agner.ch>
---
 Documentation/devicetree/bindings/display/fsl,dcu.txt |  4 ++++
 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c            |  2 +-
 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c             | 16 +++++++++++++++-
 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h             |  1 +
 4 files changed, 21 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/display/fsl,dcu.txt b/Documentation/devicetree/bindings/display/fsl,dcu.txt
index ebf1be9..f299e1e 100644
--- a/Documentation/devicetree/bindings/display/fsl,dcu.txt
+++ b/Documentation/devicetree/bindings/display/fsl,dcu.txt
@@ -11,6 +11,10 @@ Required properties:
 - big-endian		Boolean property, LS1021A DCU registers are big-endian.
 - fsl,panel:		The phandle to panel node.
 
+Optional properties:
+- clocks:		Second handle for pixel clock.
+- clock-names:		Second name "pix" for pixel clock.
+
 Examples:
 dcu: dcu@2ce0000 {
 	compatible = "fsl,ls1021a-dcu";
diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
index 35876e3..68f72fb 100644
--- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
+++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
@@ -79,7 +79,7 @@ static void fsl_dcu_drm_crtc_mode_set_nofb(struct drm_crtc *crtc)
 	unsigned long dcuclk;
 
 	index = drm_crtc_index(crtc);
-	dcuclk = clk_get_rate(fsl_dev->clk);
+	dcuclk = clk_get_rate(fsl_dev->pix_clk);
 	div = dcuclk / mode->clock / 1000;
 
 	/* Configure timings: */
diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
index f2a9c1b..f80c116 100644
--- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
+++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
@@ -331,10 +331,21 @@ static int fsl_dcu_drm_probe(struct platform_device *pdev)
 		return ret;
 	}
 
+	fsl_dev->pix_clk = devm_clk_get(dev, "pix");
+	if (IS_ERR(fsl_dev->pix_clk)) {
+		/* legancy binding, use dcu clock as pixel clock */
+		fsl_dev->pix_clk = fsl_dev->clk;
+	}
+	ret = clk_prepare_enable(fsl_dev->pix_clk);
+	if (ret < 0) {
+		dev_err(dev, "failed to enable pix clk\n");
+		goto disable_clk;
+	}
+
 	drm = drm_dev_alloc(driver, dev);
 	if (!drm) {
 		ret = -ENOMEM;
-		goto disable_clk;
+		goto disable_pix_clk;
 	}
 
 	fsl_dev->dev = dev;
@@ -355,6 +366,8 @@ static int fsl_dcu_drm_probe(struct platform_device *pdev)
 
 unref:
 	drm_dev_unref(drm);
+disable_pix_clk:
+	clk_disable_unprepare(fsl_dev->pix_clk);
 disable_clk:
 	clk_disable_unprepare(fsl_dev->clk);
 	return ret;
@@ -365,6 +378,7 @@ static int fsl_dcu_drm_remove(struct platform_device *pdev)
 	struct fsl_dcu_drm_device *fsl_dev = platform_get_drvdata(pdev);
 
 	clk_disable_unprepare(fsl_dev->clk);
+	clk_disable_unprepare(fsl_dev->pix_clk);
 	drm_put_dev(fsl_dev->drm);
 
 	return 0;
diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h
index af3a707..f60ec0a 100644
--- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h
+++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h
@@ -183,6 +183,7 @@ struct fsl_dcu_drm_device {
 	struct regmap *regmap;
 	int irq;
 	struct clk *clk;
+	struct clk *pix_clk;
 	/*protects hardware register*/
 	spinlock_t irq_lock;
 	struct drm_device *drm;
-- 
2.7.4

[PATCH v2 4/8] drm/fsl-dcu: add extra clock for pixel clock

[Stefan Agner]

The Vybrid DCU variant has two independent clock inputs, one
for the registers (IPG bus clock) and one for the pixel clock.
Support this distinction in the DCU DRM driver while staying
backward compatible with devices providing only a single clock
(e.g. LS1021a SoC's).

Signed-off-by: Stefan Agner <stefan@agner.ch>
---
 Documentation/devicetree/bindings/display/fsl,dcu.txt |  4 ++++
 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c            |  2 +-
 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c             | 16 +++++++++++++++-
 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h             |  1 +
 4 files changed, 21 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/display/fsl,dcu.txt b/Documentation/devicetree/bindings/display/fsl,dcu.txt
index ebf1be9..f299e1e 100644
--- a/Documentation/devicetree/bindings/display/fsl,dcu.txt
+++ b/Documentation/devicetree/bindings/display/fsl,dcu.txt
@@ -11,6 +11,10 @@ Required properties:
 - big-endian		Boolean property, LS1021A DCU registers are big-endian.
 - fsl,panel:		The phandle to panel node.
 
+Optional properties:
+- clocks:		Second handle for pixel clock.
+- clock-names:		Second name "pix" for pixel clock.
+
 Examples:
 dcu: dcu@2ce0000 {
 	compatible = "fsl,ls1021a-dcu";
diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
index 35876e3..68f72fb 100644
--- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
+++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
@@ -79,7 +79,7 @@ static void fsl_dcu_drm_crtc_mode_set_nofb(struct drm_crtc *crtc)
 	unsigned long dcuclk;
 
 	index = drm_crtc_index(crtc);
-	dcuclk = clk_get_rate(fsl_dev->clk);
+	dcuclk = clk_get_rate(fsl_dev->pix_clk);
 	div = dcuclk / mode->clock / 1000;
 
 	/* Configure timings: */
diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
index f2a9c1b..f80c116 100644
--- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
+++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
@@ -331,10 +331,21 @@ static int fsl_dcu_drm_probe(struct platform_device *pdev)
 		return ret;
 	}
 
+	fsl_dev->pix_clk = devm_clk_get(dev, "pix");
+	if (IS_ERR(fsl_dev->pix_clk)) {
+		/* legancy binding, use dcu clock as pixel clock */
+		fsl_dev->pix_clk = fsl_dev->clk;
+	}
+	ret = clk_prepare_enable(fsl_dev->pix_clk);
+	if (ret < 0) {
+		dev_err(dev, "failed to enable pix clk\n");
+		goto disable_clk;
+	}
+
 	drm = drm_dev_alloc(driver, dev);
 	if (!drm) {
 		ret = -ENOMEM;
-		goto disable_clk;
+		goto disable_pix_clk;
 	}
 
 	fsl_dev->dev = dev;
@@ -355,6 +366,8 @@ static int fsl_dcu_drm_probe(struct platform_device *pdev)
 
 unref:
 	drm_dev_unref(drm);
+disable_pix_clk:
+	clk_disable_unprepare(fsl_dev->pix_clk);
 disable_clk:
 	clk_disable_unprepare(fsl_dev->clk);
 	return ret;
@@ -365,6 +378,7 @@ static int fsl_dcu_drm_remove(struct platform_device *pdev)
 	struct fsl_dcu_drm_device *fsl_dev = platform_get_drvdata(pdev);
 
 	clk_disable_unprepare(fsl_dev->clk);
+	clk_disable_unprepare(fsl_dev->pix_clk);
 	drm_put_dev(fsl_dev->drm);
 
 	return 0;
diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h
index af3a707..f60ec0a 100644
--- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h
+++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h
@@ -183,6 +183,7 @@ struct fsl_dcu_drm_device {
 	struct regmap *regmap;
 	int irq;
 	struct clk *clk;
+	struct clk *pix_clk;
 	/*protects hardware register*/
 	spinlock_t irq_lock;
 	struct drm_device *drm;
-- 
2.7.4

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

[PATCH v2 4/8] drm/fsl-dcu: add extra clock for pixel clock

[Stefan Agner]

The Vybrid DCU variant has two independent clock inputs, one
for the registers (IPG bus clock) and one for the pixel clock.
Support this distinction in the DCU DRM driver while staying
backward compatible with devices providing only a single clock
(e.g. LS1021a SoC's).

Signed-off-by: Stefan Agner <stefan@agner.ch>
---
 Documentation/devicetree/bindings/display/fsl,dcu.txt |  4 ++++
 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c            |  2 +-
 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c             | 16 +++++++++++++++-
 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h             |  1 +
 4 files changed, 21 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/display/fsl,dcu.txt b/Documentation/devicetree/bindings/display/fsl,dcu.txt
index ebf1be9..f299e1e 100644
--- a/Documentation/devicetree/bindings/display/fsl,dcu.txt
+++ b/Documentation/devicetree/bindings/display/fsl,dcu.txt
@@ -11,6 +11,10 @@ Required properties:
 - big-endian		Boolean property, LS1021A DCU registers are big-endian.
 - fsl,panel:		The phandle to panel node.
 
+Optional properties:
+- clocks:		Second handle for pixel clock.
+- clock-names:		Second name "pix" for pixel clock.
+
 Examples:
 dcu: dcu at 2ce0000 {
 	compatible = "fsl,ls1021a-dcu";
diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
index 35876e3..68f72fb 100644
--- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
+++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
@@ -79,7 +79,7 @@ static void fsl_dcu_drm_crtc_mode_set_nofb(struct drm_crtc *crtc)
 	unsigned long dcuclk;
 
 	index = drm_crtc_index(crtc);
-	dcuclk = clk_get_rate(fsl_dev->clk);
+	dcuclk = clk_get_rate(fsl_dev->pix_clk);
 	div = dcuclk / mode->clock / 1000;
 
 	/* Configure timings: */
diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
index f2a9c1b..f80c116 100644
--- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
+++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
@@ -331,10 +331,21 @@ static int fsl_dcu_drm_probe(struct platform_device *pdev)
 		return ret;
 	}
 
+	fsl_dev->pix_clk = devm_clk_get(dev, "pix");
+	if (IS_ERR(fsl_dev->pix_clk)) {
+		/* legancy binding, use dcu clock as pixel clock */
+		fsl_dev->pix_clk = fsl_dev->clk;
+	}
+	ret = clk_prepare_enable(fsl_dev->pix_clk);
+	if (ret < 0) {
+		dev_err(dev, "failed to enable pix clk\n");
+		goto disable_clk;
+	}
+
 	drm = drm_dev_alloc(driver, dev);
 	if (!drm) {
 		ret = -ENOMEM;
-		goto disable_clk;
+		goto disable_pix_clk;
 	}
 
 	fsl_dev->dev = dev;
@@ -355,6 +366,8 @@ static int fsl_dcu_drm_probe(struct platform_device *pdev)
 
 unref:
 	drm_dev_unref(drm);
+disable_pix_clk:
+	clk_disable_unprepare(fsl_dev->pix_clk);
 disable_clk:
 	clk_disable_unprepare(fsl_dev->clk);
 	return ret;
@@ -365,6 +378,7 @@ static int fsl_dcu_drm_remove(struct platform_device *pdev)
 	struct fsl_dcu_drm_device *fsl_dev = platform_get_drvdata(pdev);
 
 	clk_disable_unprepare(fsl_dev->clk);
+	clk_disable_unprepare(fsl_dev->pix_clk);
 	drm_put_dev(fsl_dev->drm);
 
 	return 0;
diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h
index af3a707..f60ec0a 100644
--- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h
+++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h
@@ -183,6 +183,7 @@ struct fsl_dcu_drm_device {
 	struct regmap *regmap;
 	int irq;
 	struct clk *clk;
+	struct clk *pix_clk;
 	/*protects hardware register*/
 	spinlock_t irq_lock;
 	struct drm_device *drm;
-- 
2.7.4

[PATCH v2 5/8] drm/fsl-dcu: use common clock framework for pixel clock divider

[Stefan Agner]

Use the common clock framework to calculate the pixel clock
dividier. The previous implementation rounded down the calculated
factor. Thanks to the CLK_DIVIDER_ROUND_CLOSEST flag using the
common clock framework divider implementation improves the pixel
clock accuracy in some cases. Ontop of that it also allows to see
the actual pixel clock in the sysfs clock summary.

Signed-off-by: Stefan Agner <stefan@agner.ch>
---
 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c |  7 ++-----
 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c  | 26 ++++++++++++++++++++++----
 2 files changed, 24 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
index 68f72fb..f7b4d87 100644
--- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
+++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
@@ -75,12 +75,10 @@ static void fsl_dcu_drm_crtc_mode_set_nofb(struct drm_crtc *crtc)
 	struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
 	struct drm_connector *con = &fsl_dev->connector.base;
 	struct drm_display_mode *mode = &crtc->state->mode;
-	unsigned int hbp, hfp, hsw, vbp, vfp, vsw, div, index, pol = 0;
-	unsigned long dcuclk;
+	unsigned int hbp, hfp, hsw, vbp, vfp, vsw, index, pol = 0;
 
 	index = drm_crtc_index(crtc);
-	dcuclk = clk_get_rate(fsl_dev->pix_clk);
-	div = dcuclk / mode->clock / 1000;
+	clk_set_rate(fsl_dev->pix_clk, mode->clock * 1000);
 
 	/* Configure timings: */
 	hbp = mode->htotal - mode->hsync_end;
@@ -111,7 +109,6 @@ static void fsl_dcu_drm_crtc_mode_set_nofb(struct drm_crtc *crtc)
 	regmap_write(fsl_dev->regmap, DCU_DISP_SIZE,
 		     DCU_DISP_SIZE_DELTA_Y(mode->vdisplay) |
 		     DCU_DISP_SIZE_DELTA_X(mode->hdisplay));
-	regmap_write(fsl_dev->regmap, DCU_DIV_RATIO, div);
 	regmap_write(fsl_dev->regmap, DCU_SYN_POL, pol);
 	regmap_write(fsl_dev->regmap, DCU_BGND, DCU_BGND_R(0) |
 		     DCU_BGND_G(0) | DCU_BGND_B(0));
diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
index f80c116..093a60b 100644
--- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
+++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
@@ -283,6 +283,9 @@ static int fsl_dcu_drm_probe(struct platform_device *pdev)
 	struct resource *res;
 	void __iomem *base;
 	struct drm_driver *driver = &fsl_dcu_drm_driver;
+	struct clk *pix_clk_in;
+	char pix_clk_name[32];
+	const char *pix_clk_in_name;
 	const struct of_device_id *id;
 	int ret;
 
@@ -331,15 +334,27 @@ static int fsl_dcu_drm_probe(struct platform_device *pdev)
 		return ret;
 	}
 
-	fsl_dev->pix_clk = devm_clk_get(dev, "pix");
+	pix_clk_in = devm_clk_get(dev, "pix");
+	if (IS_ERR(pix_clk_in)) {
+		/* legancy binding, use dcu clock as pixel clock input */
+		pix_clk_in = fsl_dev->clk;
+	}
+
+	pix_clk_in_name = __clk_get_name(pix_clk_in);
+	snprintf(pix_clk_name, sizeof(pix_clk_name), "%s_pix", pix_clk_in_name);
+	fsl_dev->pix_clk = clk_register_divider(dev, pix_clk_name,
+			pix_clk_in_name, 0, base + DCU_DIV_RATIO,
+			0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL);
 	if (IS_ERR(fsl_dev->pix_clk)) {
-		/* legancy binding, use dcu clock as pixel clock */
-		fsl_dev->pix_clk = fsl_dev->clk;
+		dev_err(dev, "failed to register pix clk\n");
+		ret = PTR_ERR(fsl_dev->pix_clk);
+		goto disable_clk;
 	}
+
 	ret = clk_prepare_enable(fsl_dev->pix_clk);
 	if (ret < 0) {
 		dev_err(dev, "failed to enable pix clk\n");
-		goto disable_clk;
+		goto unregister_pix_clk;
 	}
 
 	drm = drm_dev_alloc(driver, dev);
@@ -368,6 +383,8 @@ unref:
 	drm_dev_unref(drm);
 disable_pix_clk:
 	clk_disable_unprepare(fsl_dev->pix_clk);
+unregister_pix_clk:
+	clk_unregister(fsl_dev->pix_clk);
 disable_clk:
 	clk_disable_unprepare(fsl_dev->clk);
 	return ret;
@@ -379,6 +396,7 @@ static int fsl_dcu_drm_remove(struct platform_device *pdev)
 
 	clk_disable_unprepare(fsl_dev->clk);
 	clk_disable_unprepare(fsl_dev->pix_clk);
+	clk_unregister(fsl_dev->pix_clk);
 	drm_put_dev(fsl_dev->drm);
 
 	return 0;
-- 
2.7.4

[PATCH v2 5/8] drm/fsl-dcu: use common clock framework for pixel clock divider

[Stefan Agner]

Use the common clock framework to calculate the pixel clock
dividier. The previous implementation rounded down the calculated
factor. Thanks to the CLK_DIVIDER_ROUND_CLOSEST flag using the
common clock framework divider implementation improves the pixel
clock accuracy in some cases. Ontop of that it also allows to see
the actual pixel clock in the sysfs clock summary.

Signed-off-by: Stefan Agner <stefan@agner.ch>
---
 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c |  7 ++-----
 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c  | 26 ++++++++++++++++++++++----
 2 files changed, 24 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
index 68f72fb..f7b4d87 100644
--- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
+++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
@@ -75,12 +75,10 @@ static void fsl_dcu_drm_crtc_mode_set_nofb(struct drm_crtc *crtc)
 	struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
 	struct drm_connector *con = &fsl_dev->connector.base;
 	struct drm_display_mode *mode = &crtc->state->mode;
-	unsigned int hbp, hfp, hsw, vbp, vfp, vsw, div, index, pol = 0;
-	unsigned long dcuclk;
+	unsigned int hbp, hfp, hsw, vbp, vfp, vsw, index, pol = 0;
 
 	index = drm_crtc_index(crtc);
-	dcuclk = clk_get_rate(fsl_dev->pix_clk);
-	div = dcuclk / mode->clock / 1000;
+	clk_set_rate(fsl_dev->pix_clk, mode->clock * 1000);
 
 	/* Configure timings: */
 	hbp = mode->htotal - mode->hsync_end;
@@ -111,7 +109,6 @@ static void fsl_dcu_drm_crtc_mode_set_nofb(struct drm_crtc *crtc)
 	regmap_write(fsl_dev->regmap, DCU_DISP_SIZE,
 		     DCU_DISP_SIZE_DELTA_Y(mode->vdisplay) |
 		     DCU_DISP_SIZE_DELTA_X(mode->hdisplay));
-	regmap_write(fsl_dev->regmap, DCU_DIV_RATIO, div);
 	regmap_write(fsl_dev->regmap, DCU_SYN_POL, pol);
 	regmap_write(fsl_dev->regmap, DCU_BGND, DCU_BGND_R(0) |
 		     DCU_BGND_G(0) | DCU_BGND_B(0));
diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
index f80c116..093a60b 100644
--- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
+++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
@@ -283,6 +283,9 @@ static int fsl_dcu_drm_probe(struct platform_device *pdev)
 	struct resource *res;
 	void __iomem *base;
 	struct drm_driver *driver = &fsl_dcu_drm_driver;
+	struct clk *pix_clk_in;
+	char pix_clk_name[32];
+	const char *pix_clk_in_name;
 	const struct of_device_id *id;
 	int ret;
 
@@ -331,15 +334,27 @@ static int fsl_dcu_drm_probe(struct platform_device *pdev)
 		return ret;
 	}
 
-	fsl_dev->pix_clk = devm_clk_get(dev, "pix");
+	pix_clk_in = devm_clk_get(dev, "pix");
+	if (IS_ERR(pix_clk_in)) {
+		/* legancy binding, use dcu clock as pixel clock input */
+		pix_clk_in = fsl_dev->clk;
+	}
+
+	pix_clk_in_name = __clk_get_name(pix_clk_in);
+	snprintf(pix_clk_name, sizeof(pix_clk_name), "%s_pix", pix_clk_in_name);
+	fsl_dev->pix_clk = clk_register_divider(dev, pix_clk_name,
+			pix_clk_in_name, 0, base + DCU_DIV_RATIO,
+			0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL);
 	if (IS_ERR(fsl_dev->pix_clk)) {
-		/* legancy binding, use dcu clock as pixel clock */
-		fsl_dev->pix_clk = fsl_dev->clk;
+		dev_err(dev, "failed to register pix clk\n");
+		ret = PTR_ERR(fsl_dev->pix_clk);
+		goto disable_clk;
 	}
+
 	ret = clk_prepare_enable(fsl_dev->pix_clk);
 	if (ret < 0) {
 		dev_err(dev, "failed to enable pix clk\n");
-		goto disable_clk;
+		goto unregister_pix_clk;
 	}
 
 	drm = drm_dev_alloc(driver, dev);
@@ -368,6 +383,8 @@ unref:
 	drm_dev_unref(drm);
 disable_pix_clk:
 	clk_disable_unprepare(fsl_dev->pix_clk);
+unregister_pix_clk:
+	clk_unregister(fsl_dev->pix_clk);
 disable_clk:
 	clk_disable_unprepare(fsl_dev->clk);
 	return ret;
@@ -379,6 +396,7 @@ static int fsl_dcu_drm_remove(struct platform_device *pdev)
 
 	clk_disable_unprepare(fsl_dev->clk);
 	clk_disable_unprepare(fsl_dev->pix_clk);
+	clk_unregister(fsl_dev->pix_clk);
 	drm_put_dev(fsl_dev->drm);
 
 	return 0;
-- 
2.7.4

[PATCH v2 6/8] drm/fsl-dcu: add TCON driver

[Stefan Agner]

Add driver for the TCON (timing controller) module. The TCON module
is a separate module attached after the DCU (display controller
unit). Each DCU instance has its own, directly connected TCON
instance. The DCU's RGB and timing signals are passing through
the TCON module. TCON can provide timing signals for raw TFT panels
or operate in a bypass mode which leaves all signals unaltered.

The driver currently only supports the bypass mode.

Signed-off-by: Stefan Agner <stefan@agner.ch>
---
 .../devicetree/bindings/display/fsl,dcu.txt        |   2 +
 .../devicetree/bindings/display/fsl,tcon.txt       |  18 ++++
 drivers/gpu/drm/fsl-dcu/Makefile                   |   3 +-
 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c          |   3 +
 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h          |   1 +
 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c          |  11 +++
 drivers/gpu/drm/fsl-dcu/fsl_tcon.c                 | 108 +++++++++++++++++++++
 drivers/gpu/drm/fsl-dcu/fsl_tcon.h                 |  33 +++++++
 8 files changed, 178 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/display/fsl,tcon.txt
 create mode 100644 drivers/gpu/drm/fsl-dcu/fsl_tcon.c
 create mode 100644 drivers/gpu/drm/fsl-dcu/fsl_tcon.h

diff --git a/Documentation/devicetree/bindings/display/fsl,dcu.txt b/Documentation/devicetree/bindings/display/fsl,dcu.txt
index f299e1e..b19bf12 100644
--- a/Documentation/devicetree/bindings/display/fsl,dcu.txt
+++ b/Documentation/devicetree/bindings/display/fsl,dcu.txt
@@ -14,6 +14,7 @@ Required properties:
 Optional properties:
 - clocks:		Second handle for pixel clock.
 - clock-names:		Second name "pix" for pixel clock.
+- fsl,tcon:		The phandle to the timing controller node.
 
 Examples:
 dcu: dcu@2ce0000 {
@@ -23,4 +24,5 @@ dcu: dcu@2ce0000 {
 	clock-names = "dcu";
 	big-endian;
 	fsl,panel = <&panel>;
+	fsl,tcon = <&tcon>;
 };
diff --git a/Documentation/devicetree/bindings/display/fsl,tcon.txt b/Documentation/devicetree/bindings/display/fsl,tcon.txt
new file mode 100644
index 0000000..2e1015e
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/fsl,tcon.txt
@@ -0,0 +1,18 @@
+Device Tree bindings for Freescale TCON Driver
+
+Required properties:
+- compatible:		Should be one of
+	* "fsl,vf610-tcon".
+
+- reg:			Address and length of the register set for dcu.
+- clocks:		From common clock binding: handle to tcon ipg clock.
+- clock-names:		From common clock binding: Shall be "ipg".
+
+Examples:
+timing-controller@4003d000 {
+	compatible = "fsl,vf610-tcon";
+	reg = <0x4003d000 0x1000>;
+	clocks = <&clks VF610_CLK_TCON0>;
+	clock-names = "ipg";
+	status = "okay";
+};
diff --git a/drivers/gpu/drm/fsl-dcu/Makefile b/drivers/gpu/drm/fsl-dcu/Makefile
index 6ea1523..b35a292 100644
--- a/drivers/gpu/drm/fsl-dcu/Makefile
+++ b/drivers/gpu/drm/fsl-dcu/Makefile
@@ -3,5 +3,6 @@ fsl-dcu-drm-y := fsl_dcu_drm_drv.o \
 		 fsl_dcu_drm_rgb.o \
 		 fsl_dcu_drm_plane.o \
 		 fsl_dcu_drm_crtc.o \
-		 fsl_dcu_drm_fbdev.o
+		 fsl_dcu_drm_fbdev.o \
+		 fsl_tcon.o
 obj-$(CONFIG_DRM_FSL_DCU)	+= fsl-dcu-drm.o
diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
index 093a60b..f62bff2 100644
--- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
+++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
@@ -27,6 +27,7 @@
 
 #include "fsl_dcu_drm_crtc.h"
 #include "fsl_dcu_drm_drv.h"
+#include "fsl_tcon.h"
 
 static bool fsl_dcu_drm_is_volatile_reg(struct device *dev, unsigned int reg)
 {
@@ -357,6 +358,8 @@ static int fsl_dcu_drm_probe(struct platform_device *pdev)
 		goto unregister_pix_clk;
 	}
 
+	fsl_dev->tcon = fsl_tcon_init(dev);
+
 	drm = drm_dev_alloc(driver, dev);
 	if (!drm) {
 		ret = -ENOMEM;
diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h
index f60ec0a..c275f90 100644
--- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h
+++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h
@@ -184,6 +184,7 @@ struct fsl_dcu_drm_device {
 	int irq;
 	struct clk *clk;
 	struct clk *pix_clk;
+	struct fsl_tcon *tcon;
 	/*protects hardware register*/
 	spinlock_t irq_lock;
 	struct drm_device *drm;
diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c
index 8780deb..f586f1e 100644
--- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c
+++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c
@@ -17,6 +17,7 @@
 #include <drm/drm_panel.h>
 
 #include "fsl_dcu_drm_drv.h"
+#include "fsl_tcon.h"
 
 static int
 fsl_dcu_drm_encoder_atomic_check(struct drm_encoder *encoder,
@@ -28,10 +29,20 @@ fsl_dcu_drm_encoder_atomic_check(struct drm_encoder *encoder,
 
 static void fsl_dcu_drm_encoder_disable(struct drm_encoder *encoder)
 {
+	struct drm_device *dev = encoder->dev;
+	struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
+
+	if (fsl_dev->tcon)
+		fsl_tcon_bypass_disable(fsl_dev->tcon);
 }
 
 static void fsl_dcu_drm_encoder_enable(struct drm_encoder *encoder)
 {
+	struct drm_device *dev = encoder->dev;
+	struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
+
+	if (fsl_dev->tcon)
+		fsl_tcon_bypass_enable(fsl_dev->tcon);
 }
 
 static const struct drm_encoder_helper_funcs encoder_helper_funcs = {
diff --git a/drivers/gpu/drm/fsl-dcu/fsl_tcon.c b/drivers/gpu/drm/fsl-dcu/fsl_tcon.c
new file mode 100644
index 0000000..e5001a1
--- /dev/null
+++ b/drivers/gpu/drm/fsl-dcu/fsl_tcon.c
@@ -0,0 +1,108 @@
+/*
+ * Copyright 2015 Toradex AG
+ *
+ * Stefan Agner <stefan@agner.ch>
+ *
+ * Freescale TCON device driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/mm.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+#include "fsl_tcon.h"
+
+void fsl_tcon_bypass_disable(struct fsl_tcon *tcon)
+{
+	regmap_update_bits(tcon->regs, FSL_TCON_CTRL1,
+			   FSL_TCON_CTRL1_TCON_BYPASS, 0);
+}
+
+void fsl_tcon_bypass_enable(struct fsl_tcon *tcon)
+{
+	regmap_update_bits(tcon->regs, FSL_TCON_CTRL1,
+			   FSL_TCON_CTRL1_TCON_BYPASS,
+			   FSL_TCON_CTRL1_TCON_BYPASS);
+}
+
+static struct regmap_config fsl_tcon_regmap_config = {
+	.reg_bits = 32,
+	.reg_stride = 4,
+	.val_bits = 32,
+
+	.name = "tcon",
+};
+
+static int fsl_tcon_init_regmap(struct device *dev,
+				struct fsl_tcon *tcon,
+				struct device_node *np)
+{
+	struct resource res;
+	void __iomem *regs;
+
+	if (of_address_to_resource(np, 0, &res))
+		return -EINVAL;
+
+	regs = devm_ioremap_resource(dev, &res);
+	if (IS_ERR(regs))
+		return PTR_ERR(regs);
+
+	tcon->regs = devm_regmap_init_mmio(dev, regs,
+					   &fsl_tcon_regmap_config);
+	if (IS_ERR(tcon->regs))
+		return PTR_ERR(tcon->regs);
+
+	return 0;
+}
+
+struct fsl_tcon *fsl_tcon_init(struct device *dev)
+{
+	struct fsl_tcon *tcon;
+	struct device_node *np;
+	int ret;
+
+	tcon = devm_kzalloc(dev, sizeof(*tcon), GFP_KERNEL);
+	if (!tcon)
+		return NULL;
+
+	np = of_parse_phandle(dev->of_node, "fsl,tcon", 0);
+	if (!np) {
+		dev_warn(dev, "Couldn't find the tcon node\n");
+		return NULL;
+	}
+
+	ret = fsl_tcon_init_regmap(dev, tcon, np);
+	if (ret) {
+		dev_err(dev, "Couldn't create the TCON regmap\n");
+		goto err_node_put;
+	}
+
+	tcon->ipg_clk = of_clk_get_by_name(np, "ipg");
+	if (IS_ERR(tcon->ipg_clk)) {
+		dev_err(dev, "Couldn't get the TCON bus clock\n");
+		goto err_node_put;
+	}
+
+	clk_prepare_enable(tcon->ipg_clk);
+
+	return tcon;
+
+err_node_put:
+	of_node_put(np);
+	return NULL;
+}
+
+void fsl_tcon_free(struct fsl_tcon *tcon)
+{
+	clk_disable_unprepare(tcon->ipg_clk);
+	clk_put(tcon->ipg_clk);
+}
+
diff --git a/drivers/gpu/drm/fsl-dcu/fsl_tcon.h b/drivers/gpu/drm/fsl-dcu/fsl_tcon.h
new file mode 100644
index 0000000..80a7617
--- /dev/null
+++ b/drivers/gpu/drm/fsl-dcu/fsl_tcon.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright 2015 Toradex AG
+ *
+ * Stefan Agner <stefan@agner.ch>
+ *
+ * Freescale TCON device driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __FSL_TCON_H__
+#define __FSL_TCON_H__
+
+#include <linux/bitops.h>
+
+#define FSL_TCON_CTRL1			0x0
+#define FSL_TCON_CTRL1_TCON_BYPASS	BIT(29)
+
+struct fsl_tcon {
+	struct regmap		*regs;
+	struct clk		*ipg_clk;
+};
+
+struct fsl_tcon *fsl_tcon_init(struct device *dev);
+void fsl_tcon_free(struct fsl_tcon *tcon);
+
+void fsl_tcon_bypass_disable(struct fsl_tcon *tcon);
+void fsl_tcon_bypass_enable(struct fsl_tcon *tcon);
+
+#endif /* __FSL_TCON_H__ */
-- 
2.7.4

[PATCH v2 6/8] drm/fsl-dcu: add TCON driver

[Stefan Agner]

Add driver for the TCON (timing controller) module. The TCON module
is a separate module attached after the DCU (display controller
unit). Each DCU instance has its own, directly connected TCON
instance. The DCU's RGB and timing signals are passing through
the TCON module. TCON can provide timing signals for raw TFT panels
or operate in a bypass mode which leaves all signals unaltered.

The driver currently only supports the bypass mode.

Signed-off-by: Stefan Agner <stefan@agner.ch>
---
 .../devicetree/bindings/display/fsl,dcu.txt        |   2 +
 .../devicetree/bindings/display/fsl,tcon.txt       |  18 ++++
 drivers/gpu/drm/fsl-dcu/Makefile                   |   3 +-
 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c          |   3 +
 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h          |   1 +
 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c          |  11 +++
 drivers/gpu/drm/fsl-dcu/fsl_tcon.c                 | 108 +++++++++++++++++++++
 drivers/gpu/drm/fsl-dcu/fsl_tcon.h                 |  33 +++++++
 8 files changed, 178 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/display/fsl,tcon.txt
 create mode 100644 drivers/gpu/drm/fsl-dcu/fsl_tcon.c
 create mode 100644 drivers/gpu/drm/fsl-dcu/fsl_tcon.h

diff --git a/Documentation/devicetree/bindings/display/fsl,dcu.txt b/Documentation/devicetree/bindings/display/fsl,dcu.txt
index f299e1e..b19bf12 100644
--- a/Documentation/devicetree/bindings/display/fsl,dcu.txt
+++ b/Documentation/devicetree/bindings/display/fsl,dcu.txt
@@ -14,6 +14,7 @@ Required properties:
 Optional properties:
 - clocks:		Second handle for pixel clock.
 - clock-names:		Second name "pix" for pixel clock.
+- fsl,tcon:		The phandle to the timing controller node.
 
 Examples:
 dcu: dcu at 2ce0000 {
@@ -23,4 +24,5 @@ dcu: dcu at 2ce0000 {
 	clock-names = "dcu";
 	big-endian;
 	fsl,panel = <&panel>;
+	fsl,tcon = <&tcon>;
 };
diff --git a/Documentation/devicetree/bindings/display/fsl,tcon.txt b/Documentation/devicetree/bindings/display/fsl,tcon.txt
new file mode 100644
index 0000000..2e1015e
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/fsl,tcon.txt
@@ -0,0 +1,18 @@
+Device Tree bindings for Freescale TCON Driver
+
+Required properties:
+- compatible:		Should be one of
+	* "fsl,vf610-tcon".
+
+- reg:			Address and length of the register set for dcu.
+- clocks:		From common clock binding: handle to tcon ipg clock.
+- clock-names:		From common clock binding: Shall be "ipg".
+
+Examples:
+timing-controller at 4003d000 {
+	compatible = "fsl,vf610-tcon";
+	reg = <0x4003d000 0x1000>;
+	clocks = <&clks VF610_CLK_TCON0>;
+	clock-names = "ipg";
+	status = "okay";
+};
diff --git a/drivers/gpu/drm/fsl-dcu/Makefile b/drivers/gpu/drm/fsl-dcu/Makefile
index 6ea1523..b35a292 100644
--- a/drivers/gpu/drm/fsl-dcu/Makefile
+++ b/drivers/gpu/drm/fsl-dcu/Makefile
@@ -3,5 +3,6 @@ fsl-dcu-drm-y := fsl_dcu_drm_drv.o \
 		 fsl_dcu_drm_rgb.o \
 		 fsl_dcu_drm_plane.o \
 		 fsl_dcu_drm_crtc.o \
-		 fsl_dcu_drm_fbdev.o
+		 fsl_dcu_drm_fbdev.o \
+		 fsl_tcon.o
 obj-$(CONFIG_DRM_FSL_DCU)	+= fsl-dcu-drm.o
diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
index 093a60b..f62bff2 100644
--- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
+++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
@@ -27,6 +27,7 @@
 
 #include "fsl_dcu_drm_crtc.h"
 #include "fsl_dcu_drm_drv.h"
+#include "fsl_tcon.h"
 
 static bool fsl_dcu_drm_is_volatile_reg(struct device *dev, unsigned int reg)
 {
@@ -357,6 +358,8 @@ static int fsl_dcu_drm_probe(struct platform_device *pdev)
 		goto unregister_pix_clk;
 	}
 
+	fsl_dev->tcon = fsl_tcon_init(dev);
+
 	drm = drm_dev_alloc(driver, dev);
 	if (!drm) {
 		ret = -ENOMEM;
diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h
index f60ec0a..c275f90 100644
--- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h
+++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h
@@ -184,6 +184,7 @@ struct fsl_dcu_drm_device {
 	int irq;
 	struct clk *clk;
 	struct clk *pix_clk;
+	struct fsl_tcon *tcon;
 	/*protects hardware register*/
 	spinlock_t irq_lock;
 	struct drm_device *drm;
diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c
index 8780deb..f586f1e 100644
--- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c
+++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c
@@ -17,6 +17,7 @@
 #include <drm/drm_panel.h>
 
 #include "fsl_dcu_drm_drv.h"
+#include "fsl_tcon.h"
 
 static int
 fsl_dcu_drm_encoder_atomic_check(struct drm_encoder *encoder,
@@ -28,10 +29,20 @@ fsl_dcu_drm_encoder_atomic_check(struct drm_encoder *encoder,
 
 static void fsl_dcu_drm_encoder_disable(struct drm_encoder *encoder)
 {
+	struct drm_device *dev = encoder->dev;
+	struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
+
+	if (fsl_dev->tcon)
+		fsl_tcon_bypass_disable(fsl_dev->tcon);
 }
 
 static void fsl_dcu_drm_encoder_enable(struct drm_encoder *encoder)
 {
+	struct drm_device *dev = encoder->dev;
+	struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
+
+	if (fsl_dev->tcon)
+		fsl_tcon_bypass_enable(fsl_dev->tcon);
 }
 
 static const struct drm_encoder_helper_funcs encoder_helper_funcs = {
diff --git a/drivers/gpu/drm/fsl-dcu/fsl_tcon.c b/drivers/gpu/drm/fsl-dcu/fsl_tcon.c
new file mode 100644
index 0000000..e5001a1
--- /dev/null
+++ b/drivers/gpu/drm/fsl-dcu/fsl_tcon.c
@@ -0,0 +1,108 @@
+/*
+ * Copyright 2015 Toradex AG
+ *
+ * Stefan Agner <stefan@agner.ch>
+ *
+ * Freescale TCON device driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/mm.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+#include "fsl_tcon.h"
+
+void fsl_tcon_bypass_disable(struct fsl_tcon *tcon)
+{
+	regmap_update_bits(tcon->regs, FSL_TCON_CTRL1,
+			   FSL_TCON_CTRL1_TCON_BYPASS, 0);
+}
+
+void fsl_tcon_bypass_enable(struct fsl_tcon *tcon)
+{
+	regmap_update_bits(tcon->regs, FSL_TCON_CTRL1,
+			   FSL_TCON_CTRL1_TCON_BYPASS,
+			   FSL_TCON_CTRL1_TCON_BYPASS);
+}
+
+static struct regmap_config fsl_tcon_regmap_config = {
+	.reg_bits = 32,
+	.reg_stride = 4,
+	.val_bits = 32,
+
+	.name = "tcon",
+};
+
+static int fsl_tcon_init_regmap(struct device *dev,
+				struct fsl_tcon *tcon,
+				struct device_node *np)
+{
+	struct resource res;
+	void __iomem *regs;
+
+	if (of_address_to_resource(np, 0, &res))
+		return -EINVAL;
+
+	regs = devm_ioremap_resource(dev, &res);
+	if (IS_ERR(regs))
+		return PTR_ERR(regs);
+
+	tcon->regs = devm_regmap_init_mmio(dev, regs,
+					   &fsl_tcon_regmap_config);
+	if (IS_ERR(tcon->regs))
+		return PTR_ERR(tcon->regs);
+
+	return 0;
+}
+
+struct fsl_tcon *fsl_tcon_init(struct device *dev)
+{
+	struct fsl_tcon *tcon;
+	struct device_node *np;
+	int ret;
+
+	tcon = devm_kzalloc(dev, sizeof(*tcon), GFP_KERNEL);
+	if (!tcon)
+		return NULL;
+
+	np = of_parse_phandle(dev->of_node, "fsl,tcon", 0);
+	if (!np) {
+		dev_warn(dev, "Couldn't find the tcon node\n");
+		return NULL;
+	}
+
+	ret = fsl_tcon_init_regmap(dev, tcon, np);
+	if (ret) {
+		dev_err(dev, "Couldn't create the TCON regmap\n");
+		goto err_node_put;
+	}
+
+	tcon->ipg_clk = of_clk_get_by_name(np, "ipg");
+	if (IS_ERR(tcon->ipg_clk)) {
+		dev_err(dev, "Couldn't get the TCON bus clock\n");
+		goto err_node_put;
+	}
+
+	clk_prepare_enable(tcon->ipg_clk);
+
+	return tcon;
+
+err_node_put:
+	of_node_put(np);
+	return NULL;
+}
+
+void fsl_tcon_free(struct fsl_tcon *tcon)
+{
+	clk_disable_unprepare(tcon->ipg_clk);
+	clk_put(tcon->ipg_clk);
+}
+
diff --git a/drivers/gpu/drm/fsl-dcu/fsl_tcon.h b/drivers/gpu/drm/fsl-dcu/fsl_tcon.h
new file mode 100644
index 0000000..80a7617
--- /dev/null
+++ b/drivers/gpu/drm/fsl-dcu/fsl_tcon.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright 2015 Toradex AG
+ *
+ * Stefan Agner <stefan@agner.ch>
+ *
+ * Freescale TCON device driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __FSL_TCON_H__
+#define __FSL_TCON_H__
+
+#include <linux/bitops.h>
+
+#define FSL_TCON_CTRL1			0x0
+#define FSL_TCON_CTRL1_TCON_BYPASS	BIT(29)
+
+struct fsl_tcon {
+	struct regmap		*regs;
+	struct clk		*ipg_clk;
+};
+
+struct fsl_tcon *fsl_tcon_init(struct device *dev);
+void fsl_tcon_free(struct fsl_tcon *tcon);
+
+void fsl_tcon_bypass_disable(struct fsl_tcon *tcon);
+void fsl_tcon_bypass_enable(struct fsl_tcon *tcon);
+
+#endif /* __FSL_TCON_H__ */
-- 
2.7.4

[PATCH v2 7/8] ARM: dts: vf610: add display nodes

[Stefan Agner]

Add the dcu and tcon nodes to enable the Display Controller Unit
and Timing Controller in Vybrid's SoC level device-tree file.

Signed-off-by: Stefan Agner <stefan@agner.ch>
---
 arch/arm/boot/dts/vfxxx.dtsi | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/arch/arm/boot/dts/vfxxx.dtsi b/arch/arm/boot/dts/vfxxx.dtsi
index a9ceb5b..78e24c6 100644
--- a/arch/arm/boot/dts/vfxxx.dtsi
+++ b/arch/arm/boot/dts/vfxxx.dtsi
@@ -234,6 +234,14 @@
 							<20000000>;
 			};
 
+			tcon0: timing-controller@4003d000 {
+				compatible = "fsl,vf610-tcon";
+				reg = <0x4003d000 0x1000>;
+				clocks = <&clks VF610_CLK_TCON0>;
+				clock-names = "ipg";
+				status = "disabled";
+			};
+
 			wdoga5: wdog@4003e000 {
 				compatible = "fsl,vf610-wdt", "fsl,imx21-wdt";
 				reg = <0x4003e000 0x1000>;
@@ -339,6 +347,17 @@
 				status = "disabled";
 			};
 
+			dcu0: dcu@40058000 {
+				compatible = "fsl,vf610-dcu";
+				reg = <0x40058000 0x1200>;
+				interrupts = <30 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks VF610_CLK_DCU0>,
+					<&clks VF610_CLK_DCU0_DIV>;
+				clock-names = "dcu", "pix";
+				fsl,tcon = <&tcon0>;
+				status = "disabled";
+			};
+
 			i2c0: i2c@40066000 {
 				#address-cells = <1>;
 				#size-cells = <0>;
-- 
2.7.4

[PATCH v2 7/8] ARM: dts: vf610: add display nodes

[Stefan Agner]

Add the dcu and tcon nodes to enable the Display Controller Unit
and Timing Controller in Vybrid's SoC level device-tree file.

Signed-off-by: Stefan Agner <stefan@agner.ch>
---
 arch/arm/boot/dts/vfxxx.dtsi | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/arch/arm/boot/dts/vfxxx.dtsi b/arch/arm/boot/dts/vfxxx.dtsi
index a9ceb5b..78e24c6 100644
--- a/arch/arm/boot/dts/vfxxx.dtsi
+++ b/arch/arm/boot/dts/vfxxx.dtsi
@@ -234,6 +234,14 @@
 							<20000000>;
 			};
 
+			tcon0: timing-controller at 4003d000 {
+				compatible = "fsl,vf610-tcon";
+				reg = <0x4003d000 0x1000>;
+				clocks = <&clks VF610_CLK_TCON0>;
+				clock-names = "ipg";
+				status = "disabled";
+			};
+
 			wdoga5: wdog at 4003e000 {
 				compatible = "fsl,vf610-wdt", "fsl,imx21-wdt";
 				reg = <0x4003e000 0x1000>;
@@ -339,6 +347,17 @@
 				status = "disabled";
 			};
 
+			dcu0: dcu at 40058000 {
+				compatible = "fsl,vf610-dcu";
+				reg = <0x40058000 0x1200>;
+				interrupts = <30 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks VF610_CLK_DCU0>,
+					<&clks VF610_CLK_DCU0_DIV>;
+				clock-names = "dcu", "pix";
+				fsl,tcon = <&tcon0>;
+				status = "disabled";
+			};
+
 			i2c0: i2c at 40066000 {
 				#address-cells = <1>;
 				#size-cells = <0>;
-- 
2.7.4

[PATCH v2 8/8] ARM: dts: vf610-colibri: enable display controller

[Stefan Agner]

Enable dcu node which is used by the DCU DRM driver. Assign the 5.7"
EDT panel with VGA resolution which Toradex sells often with the
evaluation board.

Signed-off-by: Stefan Agner <stefan@agner.ch>
---
 arch/arm/boot/dts/vf-colibri-eval-v3.dtsi | 16 +++++++++++++++
 arch/arm/boot/dts/vf-colibri.dtsi         | 33 +++++++++++++++++++++++++++++++
 2 files changed, 49 insertions(+)

diff --git a/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi b/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi
index ed65e0f..f5d4c78 100644
--- a/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi
+++ b/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi
@@ -18,6 +18,11 @@
 		clock-frequency = <16000000>;
 	};
 
+	panel: panel {
+		compatible = "edt,et057090dhu";
+		backlight = <&bl>;
+	};
+
 	regulators {
 		compatible = "simple-bus";
 		#address-cells = <1>;
@@ -53,6 +58,13 @@
 	status  = "okay";
 };
 
+&dcu0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_dcu0_1>;
+	fsl,panel = <&panel>;
+	status = "okay";
+};
+
 &dspi1 {
 	status = "okay";
 
@@ -100,6 +112,10 @@
 	status = "okay";
 };
 
+&tcon0 {
+	status = "okay";
+};
+
 &uart0 {
 	status = "okay";
 };
diff --git a/arch/arm/boot/dts/vf-colibri.dtsi b/arch/arm/boot/dts/vf-colibri.dtsi
index 6e556be..5f1847b 100644
--- a/arch/arm/boot/dts/vf-colibri.dtsi
+++ b/arch/arm/boot/dts/vf-colibri.dtsi
@@ -159,6 +159,39 @@
 			>;
 		};
 
+		pinctrl_dcu0_1: dcu0grp_1 {
+			fsl,pins = <
+				VF610_PAD_PTE0__DCU0_HSYNC	0x1902
+				VF610_PAD_PTE1__DCU0_VSYNC	0x1902
+				VF610_PAD_PTE2__DCU0_PCLK	0x1902
+				VF610_PAD_PTE4__DCU0_DE		0x1902
+				VF610_PAD_PTE5__DCU0_R0		0x1902
+				VF610_PAD_PTE6__DCU0_R1		0x1902
+				VF610_PAD_PTE7__DCU0_R2		0x1902
+				VF610_PAD_PTE8__DCU0_R3		0x1902
+				VF610_PAD_PTE9__DCU0_R4		0x1902
+				VF610_PAD_PTE10__DCU0_R5	0x1902
+				VF610_PAD_PTE11__DCU0_R6	0x1902
+				VF610_PAD_PTE12__DCU0_R7	0x1902
+				VF610_PAD_PTE13__DCU0_G0	0x1902
+				VF610_PAD_PTE14__DCU0_G1	0x1902
+				VF610_PAD_PTE15__DCU0_G2	0x1902
+				VF610_PAD_PTE16__DCU0_G3	0x1902
+				VF610_PAD_PTE17__DCU0_G4	0x1902
+				VF610_PAD_PTE18__DCU0_G5	0x1902
+				VF610_PAD_PTE19__DCU0_G6	0x1902
+				VF610_PAD_PTE20__DCU0_G7	0x1902
+				VF610_PAD_PTE21__DCU0_B0	0x1902
+				VF610_PAD_PTE22__DCU0_B1	0x1902
+				VF610_PAD_PTE23__DCU0_B2	0x1902
+				VF610_PAD_PTE24__DCU0_B3	0x1902
+				VF610_PAD_PTE25__DCU0_B4	0x1902
+				VF610_PAD_PTE26__DCU0_B5	0x1902
+				VF610_PAD_PTE27__DCU0_B6	0x1902
+				VF610_PAD_PTE28__DCU0_B7	0x1902
+			>;
+		};
+
 		pinctrl_dspi1: dspi1grp {
 			fsl,pins = <
 				VF610_PAD_PTD5__DSPI1_CS0		0x33e2
-- 
2.7.4

[PATCH v2 8/8] ARM: dts: vf610-colibri: enable display controller

[Stefan Agner]

Enable dcu node which is used by the DCU DRM driver. Assign the 5.7"
EDT panel with VGA resolution which Toradex sells often with the
evaluation board.

Signed-off-by: Stefan Agner <stefan-XLVq0VzYD2Y@public.gmane.org>
---
 arch/arm/boot/dts/vf-colibri-eval-v3.dtsi | 16 +++++++++++++++
 arch/arm/boot/dts/vf-colibri.dtsi         | 33 +++++++++++++++++++++++++++++++
 2 files changed, 49 insertions(+)

diff --git a/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi b/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi
index ed65e0f..f5d4c78 100644
--- a/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi
+++ b/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi
@@ -18,6 +18,11 @@
 		clock-frequency = <16000000>;
 	};
 
+	panel: panel {
+		compatible = "edt,et057090dhu";
+		backlight = <&bl>;
+	};
+
 	regulators {
 		compatible = "simple-bus";
 		#address-cells = <1>;
@@ -53,6 +58,13 @@
 	status  = "okay";
 };
 
+&dcu0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_dcu0_1>;
+	fsl,panel = <&panel>;
+	status = "okay";
+};
+
 &dspi1 {
 	status = "okay";
 
@@ -100,6 +112,10 @@
 	status = "okay";
 };
 
+&tcon0 {
+	status = "okay";
+};
+
 &uart0 {
 	status = "okay";
 };
diff --git a/arch/arm/boot/dts/vf-colibri.dtsi b/arch/arm/boot/dts/vf-colibri.dtsi
index 6e556be..5f1847b 100644
--- a/arch/arm/boot/dts/vf-colibri.dtsi
+++ b/arch/arm/boot/dts/vf-colibri.dtsi
@@ -159,6 +159,39 @@
 			>;
 		};
 
+		pinctrl_dcu0_1: dcu0grp_1 {
+			fsl,pins = <
+				VF610_PAD_PTE0__DCU0_HSYNC	0x1902
+				VF610_PAD_PTE1__DCU0_VSYNC	0x1902
+				VF610_PAD_PTE2__DCU0_PCLK	0x1902
+				VF610_PAD_PTE4__DCU0_DE		0x1902
+				VF610_PAD_PTE5__DCU0_R0		0x1902
+				VF610_PAD_PTE6__DCU0_R1		0x1902
+				VF610_PAD_PTE7__DCU0_R2		0x1902
+				VF610_PAD_PTE8__DCU0_R3		0x1902
+				VF610_PAD_PTE9__DCU0_R4		0x1902
+				VF610_PAD_PTE10__DCU0_R5	0x1902
+				VF610_PAD_PTE11__DCU0_R6	0x1902
+				VF610_PAD_PTE12__DCU0_R7	0x1902
+				VF610_PAD_PTE13__DCU0_G0	0x1902
+				VF610_PAD_PTE14__DCU0_G1	0x1902
+				VF610_PAD_PTE15__DCU0_G2	0x1902
+				VF610_PAD_PTE16__DCU0_G3	0x1902
+				VF610_PAD_PTE17__DCU0_G4	0x1902
+				VF610_PAD_PTE18__DCU0_G5	0x1902
+				VF610_PAD_PTE19__DCU0_G6	0x1902
+				VF610_PAD_PTE20__DCU0_G7	0x1902
+				VF610_PAD_PTE21__DCU0_B0	0x1902
+				VF610_PAD_PTE22__DCU0_B1	0x1902
+				VF610_PAD_PTE23__DCU0_B2	0x1902
+				VF610_PAD_PTE24__DCU0_B3	0x1902
+				VF610_PAD_PTE25__DCU0_B4	0x1902
+				VF610_PAD_PTE26__DCU0_B5	0x1902
+				VF610_PAD_PTE27__DCU0_B6	0x1902
+				VF610_PAD_PTE28__DCU0_B7	0x1902
+			>;
+		};
+
 		pinctrl_dspi1: dspi1grp {
 			fsl,pins = <
 				VF610_PAD_PTD5__DSPI1_CS0		0x33e2
-- 
2.7.4

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[PATCH v2 8/8] ARM: dts: vf610-colibri: enable display controller

[Stefan Agner]

Enable dcu node which is used by the DCU DRM driver. Assign the 5.7"
EDT panel with VGA resolution which Toradex sells often with the
evaluation board.

Signed-off-by: Stefan Agner <stefan@agner.ch>
---
 arch/arm/boot/dts/vf-colibri-eval-v3.dtsi | 16 +++++++++++++++
 arch/arm/boot/dts/vf-colibri.dtsi         | 33 +++++++++++++++++++++++++++++++
 2 files changed, 49 insertions(+)

diff --git a/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi b/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi
index ed65e0f..f5d4c78 100644
--- a/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi
+++ b/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi
@@ -18,6 +18,11 @@
 		clock-frequency = <16000000>;
 	};
 
+	panel: panel {
+		compatible = "edt,et057090dhu";
+		backlight = <&bl>;
+	};
+
 	regulators {
 		compatible = "simple-bus";
 		#address-cells = <1>;
@@ -53,6 +58,13 @@
 	status  = "okay";
 };
 
+&dcu0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_dcu0_1>;
+	fsl,panel = <&panel>;
+	status = "okay";
+};
+
 &dspi1 {
 	status = "okay";
 
@@ -100,6 +112,10 @@
 	status = "okay";
 };
 
+&tcon0 {
+	status = "okay";
+};
+
 &uart0 {
 	status = "okay";
 };
diff --git a/arch/arm/boot/dts/vf-colibri.dtsi b/arch/arm/boot/dts/vf-colibri.dtsi
index 6e556be..5f1847b 100644
--- a/arch/arm/boot/dts/vf-colibri.dtsi
+++ b/arch/arm/boot/dts/vf-colibri.dtsi
@@ -159,6 +159,39 @@
 			>;
 		};
 
+		pinctrl_dcu0_1: dcu0grp_1 {
+			fsl,pins = <
+				VF610_PAD_PTE0__DCU0_HSYNC	0x1902
+				VF610_PAD_PTE1__DCU0_VSYNC	0x1902
+				VF610_PAD_PTE2__DCU0_PCLK	0x1902
+				VF610_PAD_PTE4__DCU0_DE		0x1902
+				VF610_PAD_PTE5__DCU0_R0		0x1902
+				VF610_PAD_PTE6__DCU0_R1		0x1902
+				VF610_PAD_PTE7__DCU0_R2		0x1902
+				VF610_PAD_PTE8__DCU0_R3		0x1902
+				VF610_PAD_PTE9__DCU0_R4		0x1902
+				VF610_PAD_PTE10__DCU0_R5	0x1902
+				VF610_PAD_PTE11__DCU0_R6	0x1902
+				VF610_PAD_PTE12__DCU0_R7	0x1902
+				VF610_PAD_PTE13__DCU0_G0	0x1902
+				VF610_PAD_PTE14__DCU0_G1	0x1902
+				VF610_PAD_PTE15__DCU0_G2	0x1902
+				VF610_PAD_PTE16__DCU0_G3	0x1902
+				VF610_PAD_PTE17__DCU0_G4	0x1902
+				VF610_PAD_PTE18__DCU0_G5	0x1902
+				VF610_PAD_PTE19__DCU0_G6	0x1902
+				VF610_PAD_PTE20__DCU0_G7	0x1902
+				VF610_PAD_PTE21__DCU0_B0	0x1902
+				VF610_PAD_PTE22__DCU0_B1	0x1902
+				VF610_PAD_PTE23__DCU0_B2	0x1902
+				VF610_PAD_PTE24__DCU0_B3	0x1902
+				VF610_PAD_PTE25__DCU0_B4	0x1902
+				VF610_PAD_PTE26__DCU0_B5	0x1902
+				VF610_PAD_PTE27__DCU0_B6	0x1902
+				VF610_PAD_PTE28__DCU0_B7	0x1902
+			>;
+		};
+
 		pinctrl_dspi1: dspi1grp {
 			fsl,pins = <
 				VF610_PAD_PTD5__DSPI1_CS0		0x33e2
-- 
2.7.4

Re: [PATCH v2 6/8] drm/fsl-dcu: add TCON driver

[Alexander Stein]

Hi,

some comments below.

On Monday 28 March 2016 19:00:00, Stefan Agner wrote:
> Add driver for the TCON (timing controller) module. The TCON module
> is a separate module attached after the DCU (display controller
> unit). Each DCU instance has its own, directly connected TCON
> instance. The DCU's RGB and timing signals are passing through
> the TCON module. TCON can provide timing signals for raw TFT panels
> or operate in a bypass mode which leaves all signals unaltered.
> 
> The driver currently only supports the bypass mode.
> 
> Signed-off-by: Stefan Agner <stefan@agner.ch>

> --- a/Documentation/devicetree/bindings/display/fsl,dcu.txt
> +++ b/Documentation/devicetree/bindings/display/fsl,dcu.txt
> @@ -14,6 +14,7 @@ Required properties:
>  Optional properties:
>  - clocks:		Second handle for pixel clock.
>  - clock-names:		Second name "pix" for pixel clock.
> +- fsl,tcon:		The phandle to the timing controller node.

Maybe a comment this is (currently) only for Vybrid, but not LS1021A.

> --- /dev/null
> +++ b/drivers/gpu/drm/fsl-dcu/fsl_tcon.c
> [...]
> +struct fsl_tcon *fsl_tcon_init(struct device *dev)
> +{
> +	struct fsl_tcon *tcon;
> +	struct device_node *np;
> +	int ret;
> +
> +	tcon = devm_kzalloc(dev, sizeof(*tcon), GFP_KERNEL);
> +	if (!tcon)
> +		return NULL;
> +
> +	np = of_parse_phandle(dev->of_node, "fsl,tcon", 0);
> +	if (!np) {
> +		dev_warn(dev, "Couldn't find the tcon node\n");
> +		return NULL;
> +	}

Maybe check for device tree node before allocating struct fsl_tcon? Also this 
should not be a warning, as on LS1021A this is to be expected.

Best regards,
Alexander

Re: [PATCH v2 6/8] drm/fsl-dcu: add TCON driver

[Alexander Stein]

Hi,

some comments below.

On Monday 28 March 2016 19:00:00, Stefan Agner wrote:
> Add driver for the TCON (timing controller) module. The TCON module
> is a separate module attached after the DCU (display controller
> unit). Each DCU instance has its own, directly connected TCON
> instance. The DCU's RGB and timing signals are passing through
> the TCON module. TCON can provide timing signals for raw TFT panels
> or operate in a bypass mode which leaves all signals unaltered.
> 
> The driver currently only supports the bypass mode.
> 
> Signed-off-by: Stefan Agner <stefan@agner.ch>

> --- a/Documentation/devicetree/bindings/display/fsl,dcu.txt
> +++ b/Documentation/devicetree/bindings/display/fsl,dcu.txt
> @@ -14,6 +14,7 @@ Required properties:
>  Optional properties:
>  - clocks:		Second handle for pixel clock.
>  - clock-names:		Second name "pix" for pixel clock.
> +- fsl,tcon:		The phandle to the timing controller node.

Maybe a comment this is (currently) only for Vybrid, but not LS1021A.

> --- /dev/null
> +++ b/drivers/gpu/drm/fsl-dcu/fsl_tcon.c
> [...]
> +struct fsl_tcon *fsl_tcon_init(struct device *dev)
> +{
> +	struct fsl_tcon *tcon;
> +	struct device_node *np;
> +	int ret;
> +
> +	tcon = devm_kzalloc(dev, sizeof(*tcon), GFP_KERNEL);
> +	if (!tcon)
> +		return NULL;
> +
> +	np = of_parse_phandle(dev->of_node, "fsl,tcon", 0);
> +	if (!np) {
> +		dev_warn(dev, "Couldn't find the tcon node\n");
> +		return NULL;
> +	}

Maybe check for device tree node before allocating struct fsl_tcon? Also this 
should not be a warning, as on LS1021A this is to be expected.

Best regards,
Alexander

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

[PATCH v2 6/8] drm/fsl-dcu: add TCON driver

[Alexander Stein]

Hi,

some comments below.

On Monday 28 March 2016 19:00:00, Stefan Agner wrote:
> Add driver for the TCON (timing controller) module. The TCON module
> is a separate module attached after the DCU (display controller
> unit). Each DCU instance has its own, directly connected TCON
> instance. The DCU's RGB and timing signals are passing through
> the TCON module. TCON can provide timing signals for raw TFT panels
> or operate in a bypass mode which leaves all signals unaltered.
> 
> The driver currently only supports the bypass mode.
> 
> Signed-off-by: Stefan Agner <stefan@agner.ch>

> --- a/Documentation/devicetree/bindings/display/fsl,dcu.txt
> +++ b/Documentation/devicetree/bindings/display/fsl,dcu.txt
> @@ -14,6 +14,7 @@ Required properties:
>  Optional properties:
>  - clocks:		Second handle for pixel clock.
>  - clock-names:		Second name "pix" for pixel clock.
> +- fsl,tcon:		The phandle to the timing controller node.

Maybe a comment this is (currently) only for Vybrid, but not LS1021A.

> --- /dev/null
> +++ b/drivers/gpu/drm/fsl-dcu/fsl_tcon.c
> [...]
> +struct fsl_tcon *fsl_tcon_init(struct device *dev)
> +{
> +	struct fsl_tcon *tcon;
> +	struct device_node *np;
> +	int ret;
> +
> +	tcon = devm_kzalloc(dev, sizeof(*tcon), GFP_KERNEL);
> +	if (!tcon)
> +		return NULL;
> +
> +	np = of_parse_phandle(dev->of_node, "fsl,tcon", 0);
> +	if (!np) {
> +		dev_warn(dev, "Couldn't find the tcon node\n");
> +		return NULL;
> +	}

Maybe check for device tree node before allocating struct fsl_tcon? Also this 
should not be a warning, as on LS1021A this is to be expected.

Best regards,
Alexander

Re: [PATCH v2 6/8] drm/fsl-dcu: add TCON driver

[Stefan Agner]

On 2016-03-28 23:45, Alexander Stein wrote:
> Hi,
> 
> some comments below.
> 
> On Monday 28 March 2016 19:00:00, Stefan Agner wrote:
>> Add driver for the TCON (timing controller) module. The TCON module
>> is a separate module attached after the DCU (display controller
>> unit). Each DCU instance has its own, directly connected TCON
>> instance. The DCU's RGB and timing signals are passing through
>> the TCON module. TCON can provide timing signals for raw TFT panels
>> or operate in a bypass mode which leaves all signals unaltered.
>>
>> The driver currently only supports the bypass mode.
>>
>> Signed-off-by: Stefan Agner <stefan@agner.ch>
> 
>> --- a/Documentation/devicetree/bindings/display/fsl,dcu.txt
>> +++ b/Documentation/devicetree/bindings/display/fsl,dcu.txt
>> @@ -14,6 +14,7 @@ Required properties:
>>  Optional properties:
>>  - clocks:		Second handle for pixel clock.
>>  - clock-names:		Second name "pix" for pixel clock.
>> +- fsl,tcon:		The phandle to the timing controller node.
> 
> Maybe a comment this is (currently) only for Vybrid, but not LS1021A.
> 

IMHO, such references to SoCs in a peripheral binding is somewhat
misplaced. If we would start doing this, we would end up in lots of SoC
references, and nobody knows whether they are actually accurate and up
to date... And I think we should add tcon to LS1021a, more on that
below...

>> --- /dev/null
>> +++ b/drivers/gpu/drm/fsl-dcu/fsl_tcon.c
>> [...]
>> +struct fsl_tcon *fsl_tcon_init(struct device *dev)
>> +{
>> +	struct fsl_tcon *tcon;
>> +	struct device_node *np;
>> +	int ret;
>> +
>> +	tcon = devm_kzalloc(dev, sizeof(*tcon), GFP_KERNEL);
>> +	if (!tcon)
>> +		return NULL;
>> +
>> +	np = of_parse_phandle(dev->of_node, "fsl,tcon", 0);
>> +	if (!np) {
>> +		dev_warn(dev, "Couldn't find the tcon node\n");
>> +		return NULL;
>> +	}
> 
> Maybe check for device tree node before allocating struct fsl_tcon? Also this 
> should not be a warning, as on LS1021A this is to be expected.

Agreed, definitely the smarter sequence.

Afact LS1021a has also a TCON. At least in Jianwei Wangs initial patches
it was part of the driver, see:
https://lkml.org/lkml/2015/7/13/242

Not sure how that driver can work without TCON support on LS1021a, maybe
the bootloader sets the TCON to bypass?

Since I do not have a LS1021a, I hesitated to just add it to the LS1021s
dt's, but it should be fairly straight forward.

--
Stefan

Re: [PATCH v2 6/8] drm/fsl-dcu: add TCON driver

[Stefan Agner]

On 2016-03-28 23:45, Alexander Stein wrote:
> Hi,
> 
> some comments below.
> 
> On Monday 28 March 2016 19:00:00, Stefan Agner wrote:
>> Add driver for the TCON (timing controller) module. The TCON module
>> is a separate module attached after the DCU (display controller
>> unit). Each DCU instance has its own, directly connected TCON
>> instance. The DCU's RGB and timing signals are passing through
>> the TCON module. TCON can provide timing signals for raw TFT panels
>> or operate in a bypass mode which leaves all signals unaltered.
>>
>> The driver currently only supports the bypass mode.
>>
>> Signed-off-by: Stefan Agner <stefan@agner.ch>
> 
>> --- a/Documentation/devicetree/bindings/display/fsl,dcu.txt
>> +++ b/Documentation/devicetree/bindings/display/fsl,dcu.txt
>> @@ -14,6 +14,7 @@ Required properties:
>>  Optional properties:
>>  - clocks:		Second handle for pixel clock.
>>  - clock-names:		Second name "pix" for pixel clock.
>> +- fsl,tcon:		The phandle to the timing controller node.
> 
> Maybe a comment this is (currently) only for Vybrid, but not LS1021A.
> 

IMHO, such references to SoCs in a peripheral binding is somewhat
misplaced. If we would start doing this, we would end up in lots of SoC
references, and nobody knows whether they are actually accurate and up
to date... And I think we should add tcon to LS1021a, more on that
below...

>> --- /dev/null
>> +++ b/drivers/gpu/drm/fsl-dcu/fsl_tcon.c
>> [...]
>> +struct fsl_tcon *fsl_tcon_init(struct device *dev)
>> +{
>> +	struct fsl_tcon *tcon;
>> +	struct device_node *np;
>> +	int ret;
>> +
>> +	tcon = devm_kzalloc(dev, sizeof(*tcon), GFP_KERNEL);
>> +	if (!tcon)
>> +		return NULL;
>> +
>> +	np = of_parse_phandle(dev->of_node, "fsl,tcon", 0);
>> +	if (!np) {
>> +		dev_warn(dev, "Couldn't find the tcon node\n");
>> +		return NULL;
>> +	}
> 
> Maybe check for device tree node before allocating struct fsl_tcon? Also this 
> should not be a warning, as on LS1021A this is to be expected.

Agreed, definitely the smarter sequence.

Afact LS1021a has also a TCON. At least in Jianwei Wangs initial patches
it was part of the driver, see:
https://lkml.org/lkml/2015/7/13/242

Not sure how that driver can work without TCON support on LS1021a, maybe
the bootloader sets the TCON to bypass?

Since I do not have a LS1021a, I hesitated to just add it to the LS1021s
dt's, but it should be fairly straight forward.

--
Stefan
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

[PATCH v2 6/8] drm/fsl-dcu: add TCON driver

[Stefan Agner]

On 2016-03-28 23:45, Alexander Stein wrote:
> Hi,
> 
> some comments below.
> 
> On Monday 28 March 2016 19:00:00, Stefan Agner wrote:
>> Add driver for the TCON (timing controller) module. The TCON module
>> is a separate module attached after the DCU (display controller
>> unit). Each DCU instance has its own, directly connected TCON
>> instance. The DCU's RGB and timing signals are passing through
>> the TCON module. TCON can provide timing signals for raw TFT panels
>> or operate in a bypass mode which leaves all signals unaltered.
>>
>> The driver currently only supports the bypass mode.
>>
>> Signed-off-by: Stefan Agner <stefan@agner.ch>
> 
>> --- a/Documentation/devicetree/bindings/display/fsl,dcu.txt
>> +++ b/Documentation/devicetree/bindings/display/fsl,dcu.txt
>> @@ -14,6 +14,7 @@ Required properties:
>>  Optional properties:
>>  - clocks:		Second handle for pixel clock.
>>  - clock-names:		Second name "pix" for pixel clock.
>> +- fsl,tcon:		The phandle to the timing controller node.
> 
> Maybe a comment this is (currently) only for Vybrid, but not LS1021A.
> 

IMHO, such references to SoCs in a peripheral binding is somewhat
misplaced. If we would start doing this, we would end up in lots of SoC
references, and nobody knows whether they are actually accurate and up
to date... And I think we should add tcon to LS1021a, more on that
below...

>> --- /dev/null
>> +++ b/drivers/gpu/drm/fsl-dcu/fsl_tcon.c
>> [...]
>> +struct fsl_tcon *fsl_tcon_init(struct device *dev)
>> +{
>> +	struct fsl_tcon *tcon;
>> +	struct device_node *np;
>> +	int ret;
>> +
>> +	tcon = devm_kzalloc(dev, sizeof(*tcon), GFP_KERNEL);
>> +	if (!tcon)
>> +		return NULL;
>> +
>> +	np = of_parse_phandle(dev->of_node, "fsl,tcon", 0);
>> +	if (!np) {
>> +		dev_warn(dev, "Couldn't find the tcon node\n");
>> +		return NULL;
>> +	}
> 
> Maybe check for device tree node before allocating struct fsl_tcon? Also this 
> should not be a warning, as on LS1021A this is to be expected.

Agreed, definitely the smarter sequence.

Afact LS1021a has also a TCON. At least in Jianwei Wangs initial patches
it was part of the driver, see:
https://lkml.org/lkml/2015/7/13/242

Not sure how that driver can work without TCON support on LS1021a, maybe
the bootloader sets the TCON to bypass?

Since I do not have a LS1021a, I hesitated to just add it to the LS1021s
dt's, but it should be fairly straight forward.

--
Stefan

Re: [PATCH v2 6/8] drm/fsl-dcu: add TCON driver

[Alexander Stein]

On Tuesday 29 March 2016 00:11:13, Stefan Agner wrote:
> >> --- a/Documentation/devicetree/bindings/display/fsl,dcu.txt
> >> +++ b/Documentation/devicetree/bindings/display/fsl,dcu.txt
> >> 
> >> @@ -14,6 +14,7 @@ Required properties:
> >>  Optional properties:
> >>  - clocks:		Second handle for pixel clock.
> >>  - clock-names:		Second name "pix" for pixel clock.
> >> 
> >> +- fsl,tcon:		The phandle to the timing controller node.
> > 
> > Maybe a comment this is (currently) only for Vybrid, but not LS1021A.
> 
> IMHO, such references to SoCs in a peripheral binding is somewhat
> misplaced. If we would start doing this, we would end up in lots of SoC
> references, and nobody knows whether they are actually accurate and up
> to date... And I think we should add tcon to LS1021a, more on that
> below...

Well, I don't mind after all.

> >> --- /dev/null
> >> +++ b/drivers/gpu/drm/fsl-dcu/fsl_tcon.c
> >> [...]
> >> +struct fsl_tcon *fsl_tcon_init(struct device *dev)
> >> +{
> >> +	struct fsl_tcon *tcon;
> >> +	struct device_node *np;
> >> +	int ret;
> >> +
> >> +	tcon = devm_kzalloc(dev, sizeof(*tcon), GFP_KERNEL);
> >> +	if (!tcon)
> >> +		return NULL;
> >> +
> >> +	np = of_parse_phandle(dev->of_node, "fsl,tcon", 0);
> >> +	if (!np) {
> >> +		dev_warn(dev, "Couldn't find the tcon node\n");
> >> +		return NULL;
> >> +	}
> > 
> > Maybe check for device tree node before allocating struct fsl_tcon? Also
> > this should not be a warning, as on LS1021A this is to be expected.
> 
> Agreed, definitely the smarter sequence.
> 
> Afact LS1021a has also a TCON. At least in Jianwei Wangs initial patches
> it was part of the driver, see:
> https://lkml.org/lkml/2015/7/13/242
> 
> Not sure how that driver can work without TCON support on LS1021a, maybe
> the bootloader sets the TCON to bypass?
> 
> Since I do not have a LS1021a, I hesitated to just add it to the LS1021s
> dt's, but it should be fairly straight forward.

Interesting, but in Patch 3 (https://lists.freedesktop.org/archives/dri-devel/2015-July/086381.html) no TCON node is added and using is still 
optional. Yet, I don't find any TCON hardware in the LS1021A reference manual, 
e.g. in the memory map. I hard guess is that it doesn't require/use one. 
Without memory address it would be pretty hard to add one.

Alexander

Re: [PATCH v2 6/8] drm/fsl-dcu: add TCON driver

[Alexander Stein]

On Tuesday 29 March 2016 00:11:13, Stefan Agner wrote:
> >> --- a/Documentation/devicetree/bindings/display/fsl,dcu.txt
> >> +++ b/Documentation/devicetree/bindings/display/fsl,dcu.txt
> >> 
> >> @@ -14,6 +14,7 @@ Required properties:
> >>  Optional properties:
> >>  - clocks:		Second handle for pixel clock.
> >>  - clock-names:		Second name "pix" for pixel clock.
> >> 
> >> +- fsl,tcon:		The phandle to the timing controller node.
> > 
> > Maybe a comment this is (currently) only for Vybrid, but not LS1021A.
> 
> IMHO, such references to SoCs in a peripheral binding is somewhat
> misplaced. If we would start doing this, we would end up in lots of SoC
> references, and nobody knows whether they are actually accurate and up
> to date... And I think we should add tcon to LS1021a, more on that
> below...

Well, I don't mind after all.

> >> --- /dev/null
> >> +++ b/drivers/gpu/drm/fsl-dcu/fsl_tcon.c
> >> [...]
> >> +struct fsl_tcon *fsl_tcon_init(struct device *dev)
> >> +{
> >> +	struct fsl_tcon *tcon;
> >> +	struct device_node *np;
> >> +	int ret;
> >> +
> >> +	tcon = devm_kzalloc(dev, sizeof(*tcon), GFP_KERNEL);
> >> +	if (!tcon)
> >> +		return NULL;
> >> +
> >> +	np = of_parse_phandle(dev->of_node, "fsl,tcon", 0);
> >> +	if (!np) {
> >> +		dev_warn(dev, "Couldn't find the tcon node\n");
> >> +		return NULL;
> >> +	}
> > 
> > Maybe check for device tree node before allocating struct fsl_tcon? Also
> > this should not be a warning, as on LS1021A this is to be expected.
> 
> Agreed, definitely the smarter sequence.
> 
> Afact LS1021a has also a TCON. At least in Jianwei Wangs initial patches
> it was part of the driver, see:
> https://lkml.org/lkml/2015/7/13/242
> 
> Not sure how that driver can work without TCON support on LS1021a, maybe
> the bootloader sets the TCON to bypass?
> 
> Since I do not have a LS1021a, I hesitated to just add it to the LS1021s
> dt's, but it should be fairly straight forward.

Interesting, but in Patch 3 (https://lists.freedesktop.org/archives/dri-devel/2015-July/086381.html) no TCON node is added and using is still 
optional. Yet, I don't find any TCON hardware in the LS1021A reference manual, 
e.g. in the memory map. I hard guess is that it doesn't require/use one. 
Without memory address it would be pretty hard to add one.

Alexander

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

[PATCH v2 6/8] drm/fsl-dcu: add TCON driver

[Alexander Stein]

On Tuesday 29 March 2016 00:11:13, Stefan Agner wrote:
> >> --- a/Documentation/devicetree/bindings/display/fsl,dcu.txt
> >> +++ b/Documentation/devicetree/bindings/display/fsl,dcu.txt
> >> 
> >> @@ -14,6 +14,7 @@ Required properties:
> >>  Optional properties:
> >>  - clocks:		Second handle for pixel clock.
> >>  - clock-names:		Second name "pix" for pixel clock.
> >> 
> >> +- fsl,tcon:		The phandle to the timing controller node.
> > 
> > Maybe a comment this is (currently) only for Vybrid, but not LS1021A.
> 
> IMHO, such references to SoCs in a peripheral binding is somewhat
> misplaced. If we would start doing this, we would end up in lots of SoC
> references, and nobody knows whether they are actually accurate and up
> to date... And I think we should add tcon to LS1021a, more on that
> below...

Well, I don't mind after all.

> >> --- /dev/null
> >> +++ b/drivers/gpu/drm/fsl-dcu/fsl_tcon.c
> >> [...]
> >> +struct fsl_tcon *fsl_tcon_init(struct device *dev)
> >> +{
> >> +	struct fsl_tcon *tcon;
> >> +	struct device_node *np;
> >> +	int ret;
> >> +
> >> +	tcon = devm_kzalloc(dev, sizeof(*tcon), GFP_KERNEL);
> >> +	if (!tcon)
> >> +		return NULL;
> >> +
> >> +	np = of_parse_phandle(dev->of_node, "fsl,tcon", 0);
> >> +	if (!np) {
> >> +		dev_warn(dev, "Couldn't find the tcon node\n");
> >> +		return NULL;
> >> +	}
> > 
> > Maybe check for device tree node before allocating struct fsl_tcon? Also
> > this should not be a warning, as on LS1021A this is to be expected.
> 
> Agreed, definitely the smarter sequence.
> 
> Afact LS1021a has also a TCON. At least in Jianwei Wangs initial patches
> it was part of the driver, see:
> https://lkml.org/lkml/2015/7/13/242
> 
> Not sure how that driver can work without TCON support on LS1021a, maybe
> the bootloader sets the TCON to bypass?
> 
> Since I do not have a LS1021a, I hesitated to just add it to the LS1021s
> dt's, but it should be fairly straight forward.

Interesting, but in Patch 3 (https://lists.freedesktop.org/archives/dri-devel/2015-July/086381.html) no TCON node is added and using is still 
optional. Yet, I don't find any TCON hardware in the LS1021A reference manual, 
e.g. in the memory map. I hard guess is that it doesn't require/use one. 
Without memory address it would be pretty hard to add one.

Alexander

Re: [PATCH v2 6/8] drm/fsl-dcu: add TCON driver

[Stefan Agner]

On 2016-03-29 00:26, Alexander Stein wrote:
> On Tuesday 29 March 2016 00:11:13, Stefan Agner wrote:
>> >> --- a/Documentation/devicetree/bindings/display/fsl,dcu.txt
>> >> +++ b/Documentation/devicetree/bindings/display/fsl,dcu.txt
>> >>
>> >> @@ -14,6 +14,7 @@ Required properties:
>> >>  Optional properties:
>> >>  - clocks:		Second handle for pixel clock.
>> >>  - clock-names:		Second name "pix" for pixel clock.
>> >>
>> >> +- fsl,tcon:		The phandle to the timing controller node.
>> >
>> > Maybe a comment this is (currently) only for Vybrid, but not LS1021A.
>>
>> IMHO, such references to SoCs in a peripheral binding is somewhat
>> misplaced. If we would start doing this, we would end up in lots of SoC
>> references, and nobody knows whether they are actually accurate and up
>> to date... And I think we should add tcon to LS1021a, more on that
>> below...
> 
> Well, I don't mind after all.
> 
>> >> --- /dev/null
>> >> +++ b/drivers/gpu/drm/fsl-dcu/fsl_tcon.c
>> >> [...]
>> >> +struct fsl_tcon *fsl_tcon_init(struct device *dev)
>> >> +{
>> >> +	struct fsl_tcon *tcon;
>> >> +	struct device_node *np;
>> >> +	int ret;
>> >> +
>> >> +	tcon = devm_kzalloc(dev, sizeof(*tcon), GFP_KERNEL);
>> >> +	if (!tcon)
>> >> +		return NULL;
>> >> +
>> >> +	np = of_parse_phandle(dev->of_node, "fsl,tcon", 0);
>> >> +	if (!np) {
>> >> +		dev_warn(dev, "Couldn't find the tcon node\n");
>> >> +		return NULL;
>> >> +	}
>> >
>> > Maybe check for device tree node before allocating struct fsl_tcon? Also
>> > this should not be a warning, as on LS1021A this is to be expected.
>>
>> Agreed, definitely the smarter sequence.
>>
>> Afact LS1021a has also a TCON. At least in Jianwei Wangs initial patches
>> it was part of the driver, see:
>> https://lkml.org/lkml/2015/7/13/242
>>
>> Not sure how that driver can work without TCON support on LS1021a, maybe
>> the bootloader sets the TCON to bypass?
>>
>> Since I do not have a LS1021a, I hesitated to just add it to the LS1021s
>> dt's, but it should be fairly straight forward.
> 
> Interesting, but in Patch 3
> (https://lists.freedesktop.org/archives/dri-devel/2015-July/086381.html)
> no TCON node is added and using is still
> optional. Yet, I don't find any TCON hardware in the LS1021A reference manual, 
> e.g. in the memory map. I hard guess is that it doesn't require/use one. 
> Without memory address it would be pretty hard to add one.

Ok, maybe I am completely wrong on that. I thought I have seen it...

It could be that Jianwei added TCON support for Vybrid only, in this
case I agree there shouldn't be a warning if TCON is missing. Maybe even
the other way around, write a info message in case TCON has been found.

--
Stefan

Re: [PATCH v2 6/8] drm/fsl-dcu: add TCON driver

[Stefan Agner]

On 2016-03-29 00:26, Alexander Stein wrote:
> On Tuesday 29 March 2016 00:11:13, Stefan Agner wrote:
>> >> --- a/Documentation/devicetree/bindings/display/fsl,dcu.txt
>> >> +++ b/Documentation/devicetree/bindings/display/fsl,dcu.txt
>> >>
>> >> @@ -14,6 +14,7 @@ Required properties:
>> >>  Optional properties:
>> >>  - clocks:		Second handle for pixel clock.
>> >>  - clock-names:		Second name "pix" for pixel clock.
>> >>
>> >> +- fsl,tcon:		The phandle to the timing controller node.
>> >
>> > Maybe a comment this is (currently) only for Vybrid, but not LS1021A.
>>
>> IMHO, such references to SoCs in a peripheral binding is somewhat
>> misplaced. If we would start doing this, we would end up in lots of SoC
>> references, and nobody knows whether they are actually accurate and up
>> to date... And I think we should add tcon to LS1021a, more on that
>> below...
> 
> Well, I don't mind after all.
> 
>> >> --- /dev/null
>> >> +++ b/drivers/gpu/drm/fsl-dcu/fsl_tcon.c
>> >> [...]
>> >> +struct fsl_tcon *fsl_tcon_init(struct device *dev)
>> >> +{
>> >> +	struct fsl_tcon *tcon;
>> >> +	struct device_node *np;
>> >> +	int ret;
>> >> +
>> >> +	tcon = devm_kzalloc(dev, sizeof(*tcon), GFP_KERNEL);
>> >> +	if (!tcon)
>> >> +		return NULL;
>> >> +
>> >> +	np = of_parse_phandle(dev->of_node, "fsl,tcon", 0);
>> >> +	if (!np) {
>> >> +		dev_warn(dev, "Couldn't find the tcon node\n");
>> >> +		return NULL;
>> >> +	}
>> >
>> > Maybe check for device tree node before allocating struct fsl_tcon? Also
>> > this should not be a warning, as on LS1021A this is to be expected.
>>
>> Agreed, definitely the smarter sequence.
>>
>> Afact LS1021a has also a TCON. At least in Jianwei Wangs initial patches
>> it was part of the driver, see:
>> https://lkml.org/lkml/2015/7/13/242
>>
>> Not sure how that driver can work without TCON support on LS1021a, maybe
>> the bootloader sets the TCON to bypass?
>>
>> Since I do not have a LS1021a, I hesitated to just add it to the LS1021s
>> dt's, but it should be fairly straight forward.
> 
> Interesting, but in Patch 3
> (https://lists.freedesktop.org/archives/dri-devel/2015-July/086381.html)
> no TCON node is added and using is still
> optional. Yet, I don't find any TCON hardware in the LS1021A reference manual, 
> e.g. in the memory map. I hard guess is that it doesn't require/use one. 
> Without memory address it would be pretty hard to add one.

Ok, maybe I am completely wrong on that. I thought I have seen it...

It could be that Jianwei added TCON support for Vybrid only, in this
case I agree there shouldn't be a warning if TCON is missing. Maybe even
the other way around, write a info message in case TCON has been found.

[PATCH v2 6/8] drm/fsl-dcu: add TCON driver

[Stefan Agner]

On 2016-03-29 00:26, Alexander Stein wrote:
> On Tuesday 29 March 2016 00:11:13, Stefan Agner wrote:
>> >> --- a/Documentation/devicetree/bindings/display/fsl,dcu.txt
>> >> +++ b/Documentation/devicetree/bindings/display/fsl,dcu.txt
>> >>
>> >> @@ -14,6 +14,7 @@ Required properties:
>> >>  Optional properties:
>> >>  - clocks:		Second handle for pixel clock.
>> >>  - clock-names:		Second name "pix" for pixel clock.
>> >>
>> >> +- fsl,tcon:		The phandle to the timing controller node.
>> >
>> > Maybe a comment this is (currently) only for Vybrid, but not LS1021A.
>>
>> IMHO, such references to SoCs in a peripheral binding is somewhat
>> misplaced. If we would start doing this, we would end up in lots of SoC
>> references, and nobody knows whether they are actually accurate and up
>> to date... And I think we should add tcon to LS1021a, more on that
>> below...
> 
> Well, I don't mind after all.
> 
>> >> --- /dev/null
>> >> +++ b/drivers/gpu/drm/fsl-dcu/fsl_tcon.c
>> >> [...]
>> >> +struct fsl_tcon *fsl_tcon_init(struct device *dev)
>> >> +{
>> >> +	struct fsl_tcon *tcon;
>> >> +	struct device_node *np;
>> >> +	int ret;
>> >> +
>> >> +	tcon = devm_kzalloc(dev, sizeof(*tcon), GFP_KERNEL);
>> >> +	if (!tcon)
>> >> +		return NULL;
>> >> +
>> >> +	np = of_parse_phandle(dev->of_node, "fsl,tcon", 0);
>> >> +	if (!np) {
>> >> +		dev_warn(dev, "Couldn't find the tcon node\n");
>> >> +		return NULL;
>> >> +	}
>> >
>> > Maybe check for device tree node before allocating struct fsl_tcon? Also
>> > this should not be a warning, as on LS1021A this is to be expected.
>>
>> Agreed, definitely the smarter sequence.
>>
>> Afact LS1021a has also a TCON. At least in Jianwei Wangs initial patches
>> it was part of the driver, see:
>> https://lkml.org/lkml/2015/7/13/242
>>
>> Not sure how that driver can work without TCON support on LS1021a, maybe
>> the bootloader sets the TCON to bypass?
>>
>> Since I do not have a LS1021a, I hesitated to just add it to the LS1021s
>> dt's, but it should be fairly straight forward.
> 
> Interesting, but in Patch 3
> (https://lists.freedesktop.org/archives/dri-devel/2015-July/086381.html)
> no TCON node is added and using is still
> optional. Yet, I don't find any TCON hardware in the LS1021A reference manual, 
> e.g. in the memory map. I hard guess is that it doesn't require/use one. 
> Without memory address it would be pretty hard to add one.

Ok, maybe I am completely wrong on that. I thought I have seen it...

It could be that Jianwei added TCON support for Vybrid only, in this
case I agree there shouldn't be a warning if TCON is missing. Maybe even
the other way around, write a info message in case TCON has been found.

--
Stefan

Re: [PATCH v2 6/8] drm/fsl-dcu: add TCON driver

[Rob Herring]

On Mon, Mar 28, 2016 at 07:00:00PM -0700, Stefan Agner wrote:
> Add driver for the TCON (timing controller) module. The TCON module
> is a separate module attached after the DCU (display controller
> unit). Each DCU instance has its own, directly connected TCON
> instance. The DCU's RGB and timing signals are passing through
> the TCON module. TCON can provide timing signals for raw TFT panels
> or operate in a bypass mode which leaves all signals unaltered.
> 
> The driver currently only supports the bypass mode.
> 
> Signed-off-by: Stefan Agner <stefan@agner.ch>
> ---
>  .../devicetree/bindings/display/fsl,dcu.txt        |   2 +
>  .../devicetree/bindings/display/fsl,tcon.txt       |  18 ++++
>  drivers/gpu/drm/fsl-dcu/Makefile                   |   3 +-
>  drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c          |   3 +
>  drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h          |   1 +
>  drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c          |  11 +++
>  drivers/gpu/drm/fsl-dcu/fsl_tcon.c                 | 108 +++++++++++++++++++++
>  drivers/gpu/drm/fsl-dcu/fsl_tcon.h                 |  33 +++++++
>  8 files changed, 178 insertions(+), 1 deletion(-)
>  create mode 100644 Documentation/devicetree/bindings/display/fsl,tcon.txt
>  create mode 100644 drivers/gpu/drm/fsl-dcu/fsl_tcon.c
>  create mode 100644 drivers/gpu/drm/fsl-dcu/fsl_tcon.h
> 
> diff --git a/Documentation/devicetree/bindings/display/fsl,dcu.txt b/Documentation/devicetree/bindings/display/fsl,dcu.txt
> index f299e1e..b19bf12 100644
> --- a/Documentation/devicetree/bindings/display/fsl,dcu.txt
> +++ b/Documentation/devicetree/bindings/display/fsl,dcu.txt
> @@ -14,6 +14,7 @@ Required properties:
>  Optional properties:
>  - clocks:		Second handle for pixel clock.
>  - clock-names:		Second name "pix" for pixel clock.
> +- fsl,tcon:		The phandle to the timing controller node.
>  
>  Examples:
>  dcu: dcu@2ce0000 {
> @@ -23,4 +24,5 @@ dcu: dcu@2ce0000 {
>  	clock-names = "dcu";
>  	big-endian;
>  	fsl,panel = <&panel>;
> +	fsl,tcon = <&tcon>;
>  };
> diff --git a/Documentation/devicetree/bindings/display/fsl,tcon.txt b/Documentation/devicetree/bindings/display/fsl,tcon.txt
> new file mode 100644
> index 0000000..2e1015e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/fsl,tcon.txt
> @@ -0,0 +1,18 @@
> +Device Tree bindings for Freescale TCON Driver
> +
> +Required properties:
> +- compatible:		Should be one of
> +	* "fsl,vf610-tcon".
> +
> +- reg:			Address and length of the register set for dcu.

s/dcu/tcon/

With that,

Acked-by: Rob Herring <robh@kernel.org>


> +- clocks:		From common clock binding: handle to tcon ipg clock.
> +- clock-names:		From common clock binding: Shall be "ipg".
> +
> +Examples:
> +timing-controller@4003d000 {
> +	compatible = "fsl,vf610-tcon";
> +	reg = <0x4003d000 0x1000>;
> +	clocks = <&clks VF610_CLK_TCON0>;
> +	clock-names = "ipg";
> +	status = "okay";
> +};

Re: [PATCH v2 6/8] drm/fsl-dcu: add TCON driver

[Rob Herring]

On Mon, Mar 28, 2016 at 07:00:00PM -0700, Stefan Agner wrote:
> Add driver for the TCON (timing controller) module. The TCON module
> is a separate module attached after the DCU (display controller
> unit). Each DCU instance has its own, directly connected TCON
> instance. The DCU's RGB and timing signals are passing through
> the TCON module. TCON can provide timing signals for raw TFT panels
> or operate in a bypass mode which leaves all signals unaltered.
> 
> The driver currently only supports the bypass mode.
> 
> Signed-off-by: Stefan Agner <stefan-XLVq0VzYD2Y@public.gmane.org>
> ---
>  .../devicetree/bindings/display/fsl,dcu.txt        |   2 +
>  .../devicetree/bindings/display/fsl,tcon.txt       |  18 ++++
>  drivers/gpu/drm/fsl-dcu/Makefile                   |   3 +-
>  drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c          |   3 +
>  drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h          |   1 +
>  drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c          |  11 +++
>  drivers/gpu/drm/fsl-dcu/fsl_tcon.c                 | 108 +++++++++++++++++++++
>  drivers/gpu/drm/fsl-dcu/fsl_tcon.h                 |  33 +++++++
>  8 files changed, 178 insertions(+), 1 deletion(-)
>  create mode 100644 Documentation/devicetree/bindings/display/fsl,tcon.txt
>  create mode 100644 drivers/gpu/drm/fsl-dcu/fsl_tcon.c
>  create mode 100644 drivers/gpu/drm/fsl-dcu/fsl_tcon.h
> 
> diff --git a/Documentation/devicetree/bindings/display/fsl,dcu.txt b/Documentation/devicetree/bindings/display/fsl,dcu.txt
> index f299e1e..b19bf12 100644
> --- a/Documentation/devicetree/bindings/display/fsl,dcu.txt
> +++ b/Documentation/devicetree/bindings/display/fsl,dcu.txt
> @@ -14,6 +14,7 @@ Required properties:
>  Optional properties:
>  - clocks:		Second handle for pixel clock.
>  - clock-names:		Second name "pix" for pixel clock.
> +- fsl,tcon:		The phandle to the timing controller node.
>  
>  Examples:
>  dcu: dcu@2ce0000 {
> @@ -23,4 +24,5 @@ dcu: dcu@2ce0000 {
>  	clock-names = "dcu";
>  	big-endian;
>  	fsl,panel = <&panel>;
> +	fsl,tcon = <&tcon>;
>  };
> diff --git a/Documentation/devicetree/bindings/display/fsl,tcon.txt b/Documentation/devicetree/bindings/display/fsl,tcon.txt
> new file mode 100644
> index 0000000..2e1015e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/fsl,tcon.txt
> @@ -0,0 +1,18 @@
> +Device Tree bindings for Freescale TCON Driver
> +
> +Required properties:
> +- compatible:		Should be one of
> +	* "fsl,vf610-tcon".
> +
> +- reg:			Address and length of the register set for dcu.

s/dcu/tcon/

With that,

Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>


> +- clocks:		From common clock binding: handle to tcon ipg clock.
> +- clock-names:		From common clock binding: Shall be "ipg".
> +
> +Examples:
> +timing-controller@4003d000 {
> +	compatible = "fsl,vf610-tcon";
> +	reg = <0x4003d000 0x1000>;
> +	clocks = <&clks VF610_CLK_TCON0>;
> +	clock-names = "ipg";
> +	status = "okay";
> +};
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[PATCH v2 6/8] drm/fsl-dcu: add TCON driver

[Rob Herring]

On Mon, Mar 28, 2016 at 07:00:00PM -0700, Stefan Agner wrote:
> Add driver for the TCON (timing controller) module. The TCON module
> is a separate module attached after the DCU (display controller
> unit). Each DCU instance has its own, directly connected TCON
> instance. The DCU's RGB and timing signals are passing through
> the TCON module. TCON can provide timing signals for raw TFT panels
> or operate in a bypass mode which leaves all signals unaltered.
> 
> The driver currently only supports the bypass mode.
> 
> Signed-off-by: Stefan Agner <stefan@agner.ch>
> ---
>  .../devicetree/bindings/display/fsl,dcu.txt        |   2 +
>  .../devicetree/bindings/display/fsl,tcon.txt       |  18 ++++
>  drivers/gpu/drm/fsl-dcu/Makefile                   |   3 +-
>  drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c          |   3 +
>  drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h          |   1 +
>  drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c          |  11 +++
>  drivers/gpu/drm/fsl-dcu/fsl_tcon.c                 | 108 +++++++++++++++++++++
>  drivers/gpu/drm/fsl-dcu/fsl_tcon.h                 |  33 +++++++
>  8 files changed, 178 insertions(+), 1 deletion(-)
>  create mode 100644 Documentation/devicetree/bindings/display/fsl,tcon.txt
>  create mode 100644 drivers/gpu/drm/fsl-dcu/fsl_tcon.c
>  create mode 100644 drivers/gpu/drm/fsl-dcu/fsl_tcon.h
> 
> diff --git a/Documentation/devicetree/bindings/display/fsl,dcu.txt b/Documentation/devicetree/bindings/display/fsl,dcu.txt
> index f299e1e..b19bf12 100644
> --- a/Documentation/devicetree/bindings/display/fsl,dcu.txt
> +++ b/Documentation/devicetree/bindings/display/fsl,dcu.txt
> @@ -14,6 +14,7 @@ Required properties:
>  Optional properties:
>  - clocks:		Second handle for pixel clock.
>  - clock-names:		Second name "pix" for pixel clock.
> +- fsl,tcon:		The phandle to the timing controller node.
>  
>  Examples:
>  dcu: dcu at 2ce0000 {
> @@ -23,4 +24,5 @@ dcu: dcu at 2ce0000 {
>  	clock-names = "dcu";
>  	big-endian;
>  	fsl,panel = <&panel>;
> +	fsl,tcon = <&tcon>;
>  };
> diff --git a/Documentation/devicetree/bindings/display/fsl,tcon.txt b/Documentation/devicetree/bindings/display/fsl,tcon.txt
> new file mode 100644
> index 0000000..2e1015e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/fsl,tcon.txt
> @@ -0,0 +1,18 @@
> +Device Tree bindings for Freescale TCON Driver
> +
> +Required properties:
> +- compatible:		Should be one of
> +	* "fsl,vf610-tcon".
> +
> +- reg:			Address and length of the register set for dcu.

s/dcu/tcon/

With that,

Acked-by: Rob Herring <robh@kernel.org>


> +- clocks:		From common clock binding: handle to tcon ipg clock.
> +- clock-names:		From common clock binding: Shall be "ipg".
> +
> +Examples:
> +timing-controller at 4003d000 {
> +	compatible = "fsl,vf610-tcon";
> +	reg = <0x4003d000 0x1000>;
> +	clocks = <&clks VF610_CLK_TCON0>;
> +	clock-names = "ipg";
> +	status = "okay";
> +};

Re: [PATCH v2 4/8] drm/fsl-dcu: add extra clock for pixel clock

[Rob Herring]

On Mon, Mar 28, 2016 at 06:59:58PM -0700, Stefan Agner wrote:
> The Vybrid DCU variant has two independent clock inputs, one
> for the registers (IPG bus clock) and one for the pixel clock.
> Support this distinction in the DCU DRM driver while staying
> backward compatible with devices providing only a single clock
> (e.g. LS1021a SoC's).

I'd suspect that both have 2 clocks, just the LS1021a either didn't 
model the IPG clock or connects both to the same source. The driver 
should support both, but all the dts's should be updated to have 2 
clocks.

> 
> Signed-off-by: Stefan Agner <stefan@agner.ch>
> ---
>  Documentation/devicetree/bindings/display/fsl,dcu.txt |  4 ++++
>  drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c            |  2 +-
>  drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c             | 16 +++++++++++++++-
>  drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h             |  1 +
>  4 files changed, 21 insertions(+), 2 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/display/fsl,dcu.txt b/Documentation/devicetree/bindings/display/fsl,dcu.txt
> index ebf1be9..f299e1e 100644
> --- a/Documentation/devicetree/bindings/display/fsl,dcu.txt
> +++ b/Documentation/devicetree/bindings/display/fsl,dcu.txt
> @@ -11,6 +11,10 @@ Required properties:
>  - big-endian		Boolean property, LS1021A DCU registers are big-endian.
>  - fsl,panel:		The phandle to panel node.
>  
> +Optional properties:
> +- clocks:		Second handle for pixel clock.
> +- clock-names:		Second name "pix" for pixel clock.

Document these in one place and just add a note that LS1021a only has 1 
clock.

> +
>  Examples:
>  dcu: dcu@2ce0000 {
>  	compatible = "fsl,ls1021a-dcu";
> diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c

Re: [PATCH v2 4/8] drm/fsl-dcu: add extra clock for pixel clock

[Rob Herring]

On Mon, Mar 28, 2016 at 06:59:58PM -0700, Stefan Agner wrote:
> The Vybrid DCU variant has two independent clock inputs, one
> for the registers (IPG bus clock) and one for the pixel clock.
> Support this distinction in the DCU DRM driver while staying
> backward compatible with devices providing only a single clock
> (e.g. LS1021a SoC's).

I'd suspect that both have 2 clocks, just the LS1021a either didn't 
model the IPG clock or connects both to the same source. The driver 
should support both, but all the dts's should be updated to have 2 
clocks.

> 
> Signed-off-by: Stefan Agner <stefan@agner.ch>
> ---
>  Documentation/devicetree/bindings/display/fsl,dcu.txt |  4 ++++
>  drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c            |  2 +-
>  drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c             | 16 +++++++++++++++-
>  drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h             |  1 +
>  4 files changed, 21 insertions(+), 2 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/display/fsl,dcu.txt b/Documentation/devicetree/bindings/display/fsl,dcu.txt
> index ebf1be9..f299e1e 100644
> --- a/Documentation/devicetree/bindings/display/fsl,dcu.txt
> +++ b/Documentation/devicetree/bindings/display/fsl,dcu.txt
> @@ -11,6 +11,10 @@ Required properties:
>  - big-endian		Boolean property, LS1021A DCU registers are big-endian.
>  - fsl,panel:		The phandle to panel node.
>  
> +Optional properties:
> +- clocks:		Second handle for pixel clock.
> +- clock-names:		Second name "pix" for pixel clock.

Document these in one place and just add a note that LS1021a only has 1 
clock.

> +
>  Examples:
>  dcu: dcu@2ce0000 {
>  	compatible = "fsl,ls1021a-dcu";
> diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
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[PATCH v2 4/8] drm/fsl-dcu: add extra clock for pixel clock

[Rob Herring]

On Mon, Mar 28, 2016 at 06:59:58PM -0700, Stefan Agner wrote:
> The Vybrid DCU variant has two independent clock inputs, one
> for the registers (IPG bus clock) and one for the pixel clock.
> Support this distinction in the DCU DRM driver while staying
> backward compatible with devices providing only a single clock
> (e.g. LS1021a SoC's).

I'd suspect that both have 2 clocks, just the LS1021a either didn't 
model the IPG clock or connects both to the same source. The driver 
should support both, but all the dts's should be updated to have 2 
clocks.

> 
> Signed-off-by: Stefan Agner <stefan@agner.ch>
> ---
>  Documentation/devicetree/bindings/display/fsl,dcu.txt |  4 ++++
>  drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c            |  2 +-
>  drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c             | 16 +++++++++++++++-
>  drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h             |  1 +
>  4 files changed, 21 insertions(+), 2 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/display/fsl,dcu.txt b/Documentation/devicetree/bindings/display/fsl,dcu.txt
> index ebf1be9..f299e1e 100644
> --- a/Documentation/devicetree/bindings/display/fsl,dcu.txt
> +++ b/Documentation/devicetree/bindings/display/fsl,dcu.txt
> @@ -11,6 +11,10 @@ Required properties:
>  - big-endian		Boolean property, LS1021A DCU registers are big-endian.
>  - fsl,panel:		The phandle to panel node.
>  
> +Optional properties:
> +- clocks:		Second handle for pixel clock.
> +- clock-names:		Second name "pix" for pixel clock.

Document these in one place and just add a note that LS1021a only has 1 
clock.

> +
>  Examples:
>  dcu: dcu at 2ce0000 {
>  	compatible = "fsl,ls1021a-dcu";
> diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c