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From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 5/7] drm/i915: Reset semaphore page for gen8
Date: Wed, 06 Apr 2016 13:43:54 +0300	[thread overview]
Message-ID: <1459939434.7193.20.camel@linux.intel.com> (raw)
In-Reply-To: <20160406101004.GI18736@nuc-i3427.alporthouse.com>

On ke, 2016-04-06 at 11:10 +0100, Chris Wilson wrote:
> On Wed, Apr 06, 2016 at 12:58:43PM +0300, Joonas Lahtinen wrote:
> > 
> > On ke, 2016-04-06 at 00:57 +0100, Chris Wilson wrote:
> > > 
> > > An oversight is that when we wrap the seqno, we need to reset the hw
> > > semaphore counters to 0. We did this for gen6 and gen7 and forgot to do
> > > so for the new implementation required for gen8 (legacy).
> > > 
> > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > > Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> > > Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/intel_ringbuffer.c | 8 ++++++++
> > >  1 file changed, 8 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > > index fb304df8085d..c7023d6ca0b7 100644
> > > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> > > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > > @@ -2564,6 +2564,14 @@ void intel_ring_init_seqno(struct intel_engine_cs *engine, u32 seqno)
> > >  	}
> > >  	memset(engine->semaphore.sync_seqno, 0,
> > >  	       sizeof(engine->semaphore.sync_seqno));
> > > +	if (dev_priv->semaphore_obj) {
> > > +		struct drm_i915_gem_object *obj = dev_priv->semaphore_obj;
> > > +		struct page *page = i915_gem_object_get_dirty_page(obj, 0);
> > > +		uint64_t *semaphores = kmap(page);
> > > +		memset(semaphores + engine->id * I915_NUM_ENGINES, 0,
> > > +		       sizeof(*semaphores) * I915_NUM_ENGINES);
> > There is i915_semaphore_seqno_size define which the GEN8_WAIT_OFFSET
> > and GEN8_SIGNAL_OFFSET use. So rather use that to stay consistent.
> I didn't want the size, I wanted the type. What I really wanted were
> sensible macros...

The macros could use some cleanup is what I meant.

> 
> I can change this to i915_semaphore_seqno_size (even though that is not
> the right name) and void *.
>  
> > 
> > Other than that,
> > 
> > Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> > 
> > PS. The existing semaphore code could use some cleanup, adding to
> > backlog.
> The existing semaphore code is 3 patches from working...
> 1. fix hw-id
> 2. fix signaling
> 3. reset pd after wait
> 4. enable/profit
> -Chris
> 
-- 
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
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  reply	other threads:[~2016-04-06 10:43 UTC|newest]

Thread overview: 37+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-04-05 23:57 [PATCH 1/7] drm/i915: Include engine->last_submitted_seqno in GPU error state Chris Wilson
2016-04-05 23:57 ` [PATCH 2/7] drm/i915: On GPU reset, set the HWS breadcrumb to the last seqno Chris Wilson
2016-04-06  9:29   ` Mika Kuoppala
2016-04-06 10:40   ` Joonas Lahtinen
2016-04-05 23:57 ` [PATCH 3/7] drm/i915: Remove unneeded drm_device pointer from intel_ring_init_seqno() Chris Wilson
2016-04-06  9:08   ` Joonas Lahtinen
2016-04-05 23:57 ` [PATCH 4/7] drm/i915: Move the hw semaphore initialisation from GEM to the engine Chris Wilson
2016-04-06  9:29   ` Mika Kuoppala
2016-04-06 10:27   ` Joonas Lahtinen
2016-04-05 23:57 ` [PATCH 5/7] drm/i915: Reset semaphore page for gen8 Chris Wilson
2016-04-06  9:58   ` Joonas Lahtinen
2016-04-06 10:10     ` Chris Wilson
2016-04-06 10:43       ` Joonas Lahtinen [this message]
2016-04-05 23:57 ` [PATCH 6/7] drm/i915: Reset engine->last_submitted_seqno Chris Wilson
2016-04-06  9:30   ` Mika Kuoppala
2016-04-06 10:36   ` Joonas Lahtinen
2016-04-05 23:57 ` [PATCH 7/7] drm/i915: Simplify check for idleness in hangcheck Chris Wilson
2016-04-06  9:05   ` Joonas Lahtinen
2016-04-06  9:32   ` Mika Kuoppala
2016-04-06  9:44     ` Chris Wilson
2016-04-06  8:57 ` [PATCH 1/7] drm/i915: Include engine->last_submitted_seqno in GPU error state Joonas Lahtinen
2016-04-06  8:59 ` ✗ Fi.CI.BAT: failure for series starting with [1/7] " Patchwork
2016-04-06  9:28 ` [PATCH 1/7] " Mika Kuoppala
2016-04-06 12:33 ` [PATCH v2 1/9] " Chris Wilson
2016-04-06 12:33   ` [PATCH v2 2/9] drm/i915: On GPU reset, set the HWS breadcrumb to the last seqno Chris Wilson
2016-04-06 12:33   ` [PATCH v2 3/9] drm/i915: Remove unneeded drm_device pointer from intel_ring_init_seqno() Chris Wilson
2016-04-06 12:33   ` [PATCH v2 4/9] drm/i915: Move the hw semaphore initialisation from GEM to the engine Chris Wilson
2016-04-07  6:24     ` Joonas Lahtinen
2016-04-06 12:33   ` [PATCH v2 5/9] drm/i915: Refactor gen8 semaphore offset calculation Chris Wilson
2016-04-07  6:23     ` Joonas Lahtinen
2016-04-06 12:33   ` [PATCH v2 6/9] drm/i915: Reset semaphore page for gen8 Chris Wilson
2016-04-07  6:21     ` Joonas Lahtinen
2016-04-06 12:33   ` [PATCH v2 7/9] drm/i915: Reset engine->last_submitted_seqno Chris Wilson
2016-04-06 12:33   ` [PATCH v2 8/9] drm/i915: Apply a mb between emitting the request and hangcheck Chris Wilson
2016-04-06 14:24     ` Mika Kuoppala
2016-04-06 12:33   ` [PATCH v2 9/9] drm/i915: Simplify check for idleness in hangcheck Chris Wilson
2016-04-06 14:24     ` Mika Kuoppala

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