From: Jes.Sorensen@redhat.com
To: linux-wireless@vger.kernel.org
Cc: kvalo@codeaurora.org, Larry.Finger@lwfinger.net
Subject: [PATCH 13/18] rtl8xxxu: Set REG_USB_HRPWM for 8192eu
Date: Thu, 7 Apr 2016 14:19:28 -0400 [thread overview]
Message-ID: <1460053173-8494-14-git-send-email-Jes.Sorensen@redhat.com> (raw)
In-Reply-To: <1460053173-8494-1-git-send-email-Jes.Sorensen@redhat.com>
From: Jes Sorensen <Jes.Sorensen@redhat.com>
The vendor driver set register 0xfe58 REG_USB_HWPWM in it's init
sequence for 8192eu. Do the same here.
Signed-off-by: Jes Sorensen <Jes.Sorensen@redhat.com>
---
drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.c | 2 ++
drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.c b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.c
index eac2a54..e06b25e 100644
--- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.c
+++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.c
@@ -7225,6 +7225,8 @@ static int rtl8xxxu_init_device(struct ieee80211_hw *hw)
val32 |= FPGA_RF_MODE_CCK;
rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
}
+ } else if (priv->rtl_chip == RTL8192E) {
+ rtl8xxxu_write8(priv, REG_USB_HRPWM, 0x00);
}
val32 = rtl8xxxu_read32(priv, REG_FWHW_TXQ_CTRL);
diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h
index ade42fe..82cbe85 100644
--- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h
+++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h
@@ -1043,6 +1043,7 @@
#define USB_HIMR_ROK BIT(0) /* Receive DMA OK Interrupt */
#define REG_USB_SPECIAL_OPTION 0xfe55
+#define REG_USB_HRPWM 0xfe58
#define REG_USB_DMA_AGG_TO 0xfe5b
#define REG_USB_AGG_TO 0xfe5c
#define REG_USB_AGG_TH 0xfe5d
--
2.5.5
next prev parent reply other threads:[~2016-04-07 18:19 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-04-07 18:19 [PATCH 00/18] rtl8xxxu: Additional code to support rtl8192eu Jes.Sorensen
2016-04-07 18:19 ` [PATCH 01/18] rtl8xxxu: Add MAC init table for 8192eu Jes.Sorensen
2016-04-14 12:55 ` [01/18] " Kalle Valo
2016-04-07 18:19 ` [PATCH 02/18] rtl8xxxu: Do not mess with AFE_XTAL_CTRL on 8192eu Jes.Sorensen
2016-04-07 18:19 ` [PATCH 03/18] rtl8xxxu: Set TX page boundaries for 8192eu Jes.Sorensen
2016-04-07 18:19 ` [PATCH 04/18] rtl8xxxu: Add radio init tables " Jes.Sorensen
2016-04-07 18:19 ` [PATCH 05/18] rtl8xxxu: Add 8192eu AGC tables Jes.Sorensen
2016-04-07 18:19 ` [PATCH 06/18] rtl8xxxu: Add 8192eu PHY init table Jes.Sorensen
2016-04-07 18:19 ` [PATCH 07/18] rtl8xxxu: Pick PHY init table based on chip version first Jes.Sorensen
2016-04-07 18:19 ` [PATCH 08/18] rtl8xxxu: Correctly parse 8192eu efuse Jes.Sorensen
2016-04-07 18:19 ` [PATCH 09/18] rtl8xxxu: Handle BB init for 8192eu Jes.Sorensen
2016-04-07 18:19 ` [PATCH 10/18] rtl8xxxu: Provide special handling when writing RF regs on 8192eu Jes.Sorensen
2016-04-07 18:19 ` [PATCH 11/18] rtl8xxxu: Handle XTAL value setting " Jes.Sorensen
2016-04-07 18:19 ` [PATCH 12/18] rtl8xxxu: Set correct interrupt masking registers " Jes.Sorensen
2016-04-07 18:19 ` Jes.Sorensen [this message]
2016-04-07 18:19 ` [PATCH 14/18] rtl8xxxu: Fix LDPC RX hang issue " Jes.Sorensen
2016-04-07 18:19 ` [PATCH 15/18] rtl8xxxu: Implement 8192eu device specific quirks Jes.Sorensen
2016-04-07 18:19 ` [PATCH 16/18] rtl8xxxu: Use proper register name for REG_PAD_CTRL1 Jes.Sorensen
2016-04-07 18:19 ` [PATCH 17/18] rtl8xxxu: Implement IQK calibration for 8192eu Jes.Sorensen
2016-04-07 18:19 ` [PATCH 18/18] rtl8xxxu: Adjust AFE crystal value on 8192eu Jes.Sorensen
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