* [PATCH 0/6] Unduplicate CHV phy code
@ 2016-04-08 15:31 Ander Conselvan de Oliveira
2016-04-08 15:31 ` [PATCH 1/6] drm/i915: Set crtc_state->lane_count for HDMI Ander Conselvan de Oliveira
` (6 more replies)
0 siblings, 7 replies; 11+ messages in thread
From: Ander Conselvan de Oliveira @ 2016-04-08 15:31 UTC (permalink / raw)
To: intel-gfx; +Cc: Ander Conselvan de Oliveira
There was a lot of duplication between the CHV specific code in DP and
HDMI encoders. This series moves those to a new file: intel_dpio_phy.c.
I don't really know all the details about that code, so couldn't come
up with decent names for the new funcions. Perhaps Ville can suggest
something better and also what to write for kerneldoc.
Note that I only compile-tested this.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Ander Conselvan de Oliveira (6):
drm/i915: Set crtc_state->lane_count for HDMI
drm/i915: Unduplicate CHV signal level code
drm/i915: Unduplicate chv_data_lane_soft_reset()
drm/i915: Unduplicate CHV phy-releated pre pll enabling code
drm/i915: Unduplicate CHV pre-encoder enabling phy logic
drm/i915: Undiplicate CHV encoders' post pll disable code
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/i915_drv.h | 11 +
drivers/gpu/drm/i915/intel_dp.c | 344 +------------------------------
drivers/gpu/drm/i915/intel_dpio_phy.c | 372 ++++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_drv.h | 5 +
drivers/gpu/drm/i915/intel_hdmi.c | 289 +-------------------------
6 files changed, 406 insertions(+), 616 deletions(-)
create mode 100644 drivers/gpu/drm/i915/intel_dpio_phy.c
--
2.4.11
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 1/6] drm/i915: Set crtc_state->lane_count for HDMI
2016-04-08 15:31 [PATCH 0/6] Unduplicate CHV phy code Ander Conselvan de Oliveira
@ 2016-04-08 15:31 ` Ander Conselvan de Oliveira
2016-04-11 8:23 ` [PATCH v2] " Ander Conselvan de Oliveira
2016-04-08 15:31 ` [PATCH 2/6] drm/i915: Unduplicate CHV signal level code Ander Conselvan de Oliveira
` (5 subsequent siblings)
6 siblings, 1 reply; 11+ messages in thread
From: Ander Conselvan de Oliveira @ 2016-04-08 15:31 UTC (permalink / raw)
To: intel-gfx; +Cc: Ander Conselvan de Oliveira
Set the lane count for HDMI to 4. This will make it easier to
unduplicate CHV phy code.
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
drivers/gpu/drm/i915/intel_hdmi.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index b199ede..2dc6e00 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1337,6 +1337,8 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder,
/* Set user selected PAR to incoming mode's member */
adjusted_mode->picture_aspect_ratio = intel_hdmi->aspect_ratio;
+ pipe_config->lane_count = 4;
+
return true;
}
--
2.4.11
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 2/6] drm/i915: Unduplicate CHV signal level code
2016-04-08 15:31 [PATCH 0/6] Unduplicate CHV phy code Ander Conselvan de Oliveira
2016-04-08 15:31 ` [PATCH 1/6] drm/i915: Set crtc_state->lane_count for HDMI Ander Conselvan de Oliveira
@ 2016-04-08 15:31 ` Ander Conselvan de Oliveira
2016-04-11 15:09 ` Ville Syrjälä
2016-04-08 15:31 ` [PATCH 3/6] drm/i915: Unduplicate chv_data_lane_soft_reset() Ander Conselvan de Oliveira
` (4 subsequent siblings)
6 siblings, 1 reply; 11+ messages in thread
From: Ander Conselvan de Oliveira @ 2016-04-08 15:31 UTC (permalink / raw)
To: intel-gfx; +Cc: Ander Conselvan de Oliveira
The code for programming voltage swing and emphasis was duplicated
between DP and HDMI code. Move that to a new file, intel_dpio_phy.c.
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/i915_drv.h | 5 ++
drivers/gpu/drm/i915/intel_dp.c | 103 ++--------------------------
drivers/gpu/drm/i915/intel_dpio_phy.c | 122 ++++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_hdmi.c | 72 +-------------------
5 files changed, 136 insertions(+), 167 deletions(-)
create mode 100644 drivers/gpu/drm/i915/intel_dpio_phy.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 7ffb51b..eb45e28 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -57,6 +57,7 @@ i915-y += intel_audio.o \
intel_bios.o \
intel_color.o \
intel_display.o \
+ intel_dpio_phy.o \
intel_dpll_mgr.o \
intel_fbc.o \
intel_fifo_underrun.o \
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4ebd3ff..3c393e3 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3504,6 +3504,11 @@ void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
+/* intel_dpio_phy.c */
+void chv_set_phy_signal_level(struct intel_encoder *encoder,
+ u32 deemph_reg_value, u32 margin_reg_value,
+ bool uniq_trans_scale);
+
int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index da0c3d2..5ba72b0 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3339,23 +3339,12 @@ static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
return 0;
}
-static bool chv_need_uniq_trans_scale(uint8_t train_set)
-{
- return (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) == DP_TRAIN_PRE_EMPH_LEVEL_0 &&
- (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) == DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
-}
-
static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
{
- struct drm_device *dev = intel_dp_to_dev(intel_dp);
- struct drm_i915_private *dev_priv = dev->dev_private;
- struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
- struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
- u32 deemph_reg_value, margin_reg_value, val;
+ struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
+ u32 deemph_reg_value, margin_reg_value;
+ bool uniq_trans_scale = false;
uint8_t train_set = intel_dp->train_set[0];
- enum dpio_channel ch = vlv_dport_to_channel(dport);
- enum pipe pipe = intel_crtc->pipe;
- int i;
switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
case DP_TRAIN_PRE_EMPH_LEVEL_0:
@@ -3375,7 +3364,7 @@ static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
deemph_reg_value = 128;
margin_reg_value = 154;
- /* FIXME extra to set for 1200 */
+ uniq_trans_scale = true;
break;
default:
return 0;
@@ -3427,88 +3416,8 @@ static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
return 0;
}
- mutex_lock(&dev_priv->sb_lock);
-
- /* Clear calc init */
- val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
- val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
- val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
- val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
- vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
-
- if (intel_crtc->config->lane_count > 2) {
- val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
- val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
- val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
- val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
- vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
- }
-
- val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
- val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
- val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
- vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
-
- if (intel_crtc->config->lane_count > 2) {
- val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
- val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
- val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
- vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
- }
-
- /* Program swing deemph */
- for (i = 0; i < intel_crtc->config->lane_count; i++) {
- val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
- val &= ~DPIO_SWING_DEEMPH9P5_MASK;
- val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
- vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
- }
-
- /* Program swing margin */
- for (i = 0; i < intel_crtc->config->lane_count; i++) {
- val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
-
- val &= ~DPIO_SWING_MARGIN000_MASK;
- val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
-
- /*
- * Supposedly this value shouldn't matter when unique transition
- * scale is disabled, but in fact it does matter. Let's just
- * always program the same value and hope it's OK.
- */
- val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
- val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT;
-
- vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
- }
-
- /*
- * The document said it needs to set bit 27 for ch0 and bit 26
- * for ch1. Might be a typo in the doc.
- * For now, for this unique transition scale selection, set bit
- * 27 for ch0 and ch1.
- */
- for (i = 0; i < intel_crtc->config->lane_count; i++) {
- val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
- if (chv_need_uniq_trans_scale(train_set))
- val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
- else
- val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
- vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
- }
-
- /* Start swing calculation */
- val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
- val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
- vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
-
- if (intel_crtc->config->lane_count > 2) {
- val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
- val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
- vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
- }
-
- mutex_unlock(&dev_priv->sb_lock);
+ chv_set_phy_signal_level(encoder, deemph_reg_value,
+ margin_reg_value, uniq_trans_scale);
return 0;
}
diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
new file mode 100644
index 0000000..cbe1703d
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
@@ -0,0 +1,122 @@
+/*
+ * Copyright © 2014-2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include "intel_drv.h"
+
+void chv_set_phy_signal_level(struct intel_encoder *encoder,
+ u32 deemph_reg_value, u32 margin_reg_value,
+ bool uniq_trans_scale)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
+ struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
+ enum dpio_channel ch = vlv_dport_to_channel(dport);
+ enum pipe pipe = intel_crtc->pipe;
+ u32 val;
+ int i;
+
+ mutex_lock(&dev_priv->sb_lock);
+
+ /* Clear calc init */
+ val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
+ val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
+ val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
+ val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
+ vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
+
+ if (intel_crtc->config->lane_count > 2) {
+ val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
+ val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
+ val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
+ val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
+ vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
+ }
+
+ val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
+ val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
+ val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
+ vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
+
+ if (intel_crtc->config->lane_count > 2) {
+ val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
+ val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
+ val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
+ vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
+ }
+
+ /* Program swing deemph */
+ for (i = 0; i < intel_crtc->config->lane_count; i++) {
+ val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
+ val &= ~DPIO_SWING_DEEMPH9P5_MASK;
+ val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
+ vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
+ }
+
+ /* Program swing margin */
+ for (i = 0; i < intel_crtc->config->lane_count; i++) {
+ val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
+
+ val &= ~DPIO_SWING_MARGIN000_MASK;
+ val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
+
+ /*
+ * Supposedly this value shouldn't matter when unique transition
+ * scale is disabled, but in fact it does matter. Let's just
+ * always program the same value and hope it's OK.
+ */
+ val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
+ val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT;
+
+ vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
+ }
+
+ /*
+ * The document said it needs to set bit 27 for ch0 and bit 26
+ * for ch1. Might be a typo in the doc.
+ * For now, for this unique transition scale selection, set bit
+ * 27 for ch0 and ch1.
+ */
+ for (i = 0; i < intel_crtc->config->lane_count; i++) {
+ val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
+ if (uniq_trans_scale)
+ val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
+ else
+ val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
+ vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
+ }
+
+ /* Start swing calculation */
+ val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
+ val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
+ vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
+
+ if (intel_crtc->config->lane_count > 2) {
+ val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
+ val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
+ vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
+ }
+
+ mutex_unlock(&dev_priv->sb_lock);
+
+}
+
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 2dc6e00..107a80a 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1911,78 +1911,10 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
/* Deassert data lane reset */
chv_data_lane_soft_reset(encoder, false);
- /* Clear calc init */
- val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
- val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
- val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
- val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
- vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
-
- val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
- val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
- val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
- val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
- vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
-
- val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
- val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
- val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
- vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
-
- val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
- val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
- val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
- vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
-
- /* FIXME: Program the support xxx V-dB */
- /* Use 800mV-0dB */
- for (i = 0; i < 4; i++) {
- val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
- val &= ~DPIO_SWING_DEEMPH9P5_MASK;
- val |= 128 << DPIO_SWING_DEEMPH9P5_SHIFT;
- vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
- }
-
- for (i = 0; i < 4; i++) {
- val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
-
- val &= ~DPIO_SWING_MARGIN000_MASK;
- val |= 102 << DPIO_SWING_MARGIN000_SHIFT;
-
- /*
- * Supposedly this value shouldn't matter when unique transition
- * scale is disabled, but in fact it does matter. Let's just
- * always program the same value and hope it's OK.
- */
- val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
- val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT;
-
- vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
- }
-
- /*
- * The document said it needs to set bit 27 for ch0 and bit 26
- * for ch1. Might be a typo in the doc.
- * For now, for this unique transition scale selection, set bit
- * 27 for ch0 and ch1.
- */
- for (i = 0; i < 4; i++) {
- val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
- val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
- vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
- }
-
- /* Start swing calculation */
- val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
- val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
- vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
-
- val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
- val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
- vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
-
mutex_unlock(&dev_priv->sb_lock);
+ chv_set_phy_signal_level(encoder, 128, 102, false);
+
intel_hdmi->set_infoframes(&encoder->base,
intel_crtc->config->has_hdmi_sink,
adjusted_mode);
--
2.4.11
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 3/6] drm/i915: Unduplicate chv_data_lane_soft_reset()
2016-04-08 15:31 [PATCH 0/6] Unduplicate CHV phy code Ander Conselvan de Oliveira
2016-04-08 15:31 ` [PATCH 1/6] drm/i915: Set crtc_state->lane_count for HDMI Ander Conselvan de Oliveira
2016-04-08 15:31 ` [PATCH 2/6] drm/i915: Unduplicate CHV signal level code Ander Conselvan de Oliveira
@ 2016-04-08 15:31 ` Ander Conselvan de Oliveira
2016-04-08 15:31 ` [PATCH 4/6] drm/i915: Unduplicate CHV phy-releated pre pll enabling code Ander Conselvan de Oliveira
` (3 subsequent siblings)
6 siblings, 0 replies; 11+ messages in thread
From: Ander Conselvan de Oliveira @ 2016-04-08 15:31 UTC (permalink / raw)
To: intel-gfx; +Cc: Ander Conselvan de Oliveira
The function chv_data_lane_soft_reset() was duplicated in DP and HDMI
code. Move it to intel_dpio_phy.c.
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/intel_dp.c | 44 -----------------------------------
drivers/gpu/drm/i915/intel_dpio_phy.c | 43 ++++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_hdmi.c | 44 -----------------------------------
4 files changed, 45 insertions(+), 88 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3c393e3..52e5e88 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3508,6 +3508,8 @@ void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
void chv_set_phy_signal_level(struct intel_encoder *encoder,
u32 deemph_reg_value, u32 margin_reg_value,
bool uniq_trans_scale);
+void chv_data_lane_soft_reset(struct intel_encoder *encoder,
+ bool reset);
int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 5ba72b0..4d15166 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2451,50 +2451,6 @@ static void vlv_post_disable_dp(struct intel_encoder *encoder)
intel_dp_link_down(intel_dp);
}
-static void chv_data_lane_soft_reset(struct intel_encoder *encoder,
- bool reset)
-{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
- struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
- enum pipe pipe = crtc->pipe;
- uint32_t val;
-
- val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
- if (reset)
- val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
- else
- val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
- vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
-
- if (crtc->config->lane_count > 2) {
- val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
- if (reset)
- val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
- else
- val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
- vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
- }
-
- val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
- val |= CHV_PCS_REQ_SOFTRESET_EN;
- if (reset)
- val &= ~DPIO_PCS_CLK_SOFT_RESET;
- else
- val |= DPIO_PCS_CLK_SOFT_RESET;
- vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
-
- if (crtc->config->lane_count > 2) {
- val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
- val |= CHV_PCS_REQ_SOFTRESET_EN;
- if (reset)
- val &= ~DPIO_PCS_CLK_SOFT_RESET;
- else
- val |= DPIO_PCS_CLK_SOFT_RESET;
- vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
- }
-}
-
static void chv_post_disable_dp(struct intel_encoder *encoder)
{
struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
index cbe1703d..9854c93 100644
--- a/drivers/gpu/drm/i915/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
@@ -120,3 +120,46 @@ void chv_set_phy_signal_level(struct intel_encoder *encoder,
}
+void chv_data_lane_soft_reset(struct intel_encoder *encoder,
+ bool reset)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
+ struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
+ enum pipe pipe = crtc->pipe;
+ uint32_t val;
+
+ val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
+ if (reset)
+ val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
+ else
+ val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
+ vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
+
+ if (crtc->config->lane_count > 2) {
+ val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
+ if (reset)
+ val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
+ else
+ val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
+ vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
+ }
+
+ val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
+ val |= CHV_PCS_REQ_SOFTRESET_EN;
+ if (reset)
+ val &= ~DPIO_PCS_CLK_SOFT_RESET;
+ else
+ val |= DPIO_PCS_CLK_SOFT_RESET;
+ vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
+
+ if (crtc->config->lane_count > 2) {
+ val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
+ val |= CHV_PCS_REQ_SOFTRESET_EN;
+ if (reset)
+ val &= ~DPIO_PCS_CLK_SOFT_RESET;
+ else
+ val |= DPIO_PCS_CLK_SOFT_RESET;
+ vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
+ }
+}
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 107a80a..c2d6139 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1656,50 +1656,6 @@ static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
mutex_unlock(&dev_priv->sb_lock);
}
-static void chv_data_lane_soft_reset(struct intel_encoder *encoder,
- bool reset)
-{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
- struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
- enum pipe pipe = crtc->pipe;
- uint32_t val;
-
- val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
- if (reset)
- val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
- else
- val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
- vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
-
- if (crtc->config->lane_count > 2) {
- val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
- if (reset)
- val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
- else
- val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
- vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
- }
-
- val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
- val |= CHV_PCS_REQ_SOFTRESET_EN;
- if (reset)
- val &= ~DPIO_PCS_CLK_SOFT_RESET;
- else
- val |= DPIO_PCS_CLK_SOFT_RESET;
- vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
-
- if (crtc->config->lane_count > 2) {
- val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
- val |= CHV_PCS_REQ_SOFTRESET_EN;
- if (reset)
- val &= ~DPIO_PCS_CLK_SOFT_RESET;
- else
- val |= DPIO_PCS_CLK_SOFT_RESET;
- vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
- }
-}
-
static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
{
struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
--
2.4.11
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 4/6] drm/i915: Unduplicate CHV phy-releated pre pll enabling code
2016-04-08 15:31 [PATCH 0/6] Unduplicate CHV phy code Ander Conselvan de Oliveira
` (2 preceding siblings ...)
2016-04-08 15:31 ` [PATCH 3/6] drm/i915: Unduplicate chv_data_lane_soft_reset() Ander Conselvan de Oliveira
@ 2016-04-08 15:31 ` Ander Conselvan de Oliveira
2016-04-08 15:31 ` [PATCH 5/6] drm/i915: Unduplicate CHV pre-encoder enabling phy logic Ander Conselvan de Oliveira
` (2 subsequent siblings)
6 siblings, 0 replies; 11+ messages in thread
From: Ander Conselvan de Oliveira @ 2016-04-08 15:31 UTC (permalink / raw)
To: intel-gfx; +Cc: Ander Conselvan de Oliveira
The same logic is used for DP and HDMI so move it to intel_dpio_phy.c.
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_dp.c | 83 +----------------------------------
drivers/gpu/drm/i915/intel_dpio_phy.c | 81 ++++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_drv.h | 5 +++
drivers/gpu/drm/i915/intel_hdmi.c | 74 +------------------------------
5 files changed, 89 insertions(+), 155 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 52e5e88..7b2f453 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3510,6 +3510,7 @@ void chv_set_phy_signal_level(struct intel_encoder *encoder,
bool uniq_trans_scale);
void chv_data_lane_soft_reset(struct intel_encoder *encoder,
bool reset);
+void chv_phy_pre_pll_enable(struct intel_encoder *encoder);
int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 4d15166..fb0c9c5 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -131,11 +131,6 @@ static void vlv_steal_power_sequencer(struct drm_device *dev,
enum pipe pipe);
static void intel_dp_unset_edid(struct intel_dp *intel_dp);
-static unsigned int intel_dp_unused_lane_mask(int lane_count)
-{
- return ~((1 << lane_count) - 1) & 0xf;
-}
-
static int
intel_dp_max_link_bw(struct intel_dp *intel_dp)
{
@@ -2945,85 +2940,9 @@ static void chv_pre_enable_dp(struct intel_encoder *encoder)
static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
{
- struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
- struct drm_device *dev = encoder->base.dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
- struct intel_crtc *intel_crtc =
- to_intel_crtc(encoder->base.crtc);
- enum dpio_channel ch = vlv_dport_to_channel(dport);
- enum pipe pipe = intel_crtc->pipe;
- unsigned int lane_mask =
- intel_dp_unused_lane_mask(intel_crtc->config->lane_count);
- u32 val;
-
intel_dp_prepare(encoder);
- /*
- * Must trick the second common lane into life.
- * Otherwise we can't even access the PLL.
- */
- if (ch == DPIO_CH0 && pipe == PIPE_B)
- dport->release_cl2_override =
- !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true);
-
- chv_phy_powergate_lanes(encoder, true, lane_mask);
-
- mutex_lock(&dev_priv->sb_lock);
-
- /* Assert data lane reset */
- chv_data_lane_soft_reset(encoder, true);
-
- /* program left/right clock distribution */
- if (pipe != PIPE_B) {
- val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
- val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
- if (ch == DPIO_CH0)
- val |= CHV_BUFLEFTENA1_FORCE;
- if (ch == DPIO_CH1)
- val |= CHV_BUFRIGHTENA1_FORCE;
- vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
- } else {
- val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
- val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
- if (ch == DPIO_CH0)
- val |= CHV_BUFLEFTENA2_FORCE;
- if (ch == DPIO_CH1)
- val |= CHV_BUFRIGHTENA2_FORCE;
- vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
- }
-
- /* program clock channel usage */
- val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
- val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
- if (pipe != PIPE_B)
- val &= ~CHV_PCS_USEDCLKCHANNEL;
- else
- val |= CHV_PCS_USEDCLKCHANNEL;
- vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
-
- if (intel_crtc->config->lane_count > 2) {
- val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
- val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
- if (pipe != PIPE_B)
- val &= ~CHV_PCS_USEDCLKCHANNEL;
- else
- val |= CHV_PCS_USEDCLKCHANNEL;
- vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
- }
-
- /*
- * This a a bit weird since generally CL
- * matches the pipe, but here we need to
- * pick the CL based on the port.
- */
- val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
- if (pipe != PIPE_B)
- val &= ~CHV_CMN_USEDCLKCHANNEL;
- else
- val |= CHV_CMN_USEDCLKCHANNEL;
- vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
-
- mutex_unlock(&dev_priv->sb_lock);
+ chv_phy_pre_pll_enable(encoder);
}
static void chv_dp_post_pll_disable(struct intel_encoder *encoder)
diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
index 9854c93..b4ca3ff 100644
--- a/drivers/gpu/drm/i915/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
@@ -163,3 +163,84 @@ void chv_data_lane_soft_reset(struct intel_encoder *encoder,
vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
}
}
+
+void chv_phy_pre_pll_enable(struct intel_encoder *encoder)
+{
+ struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
+ struct drm_device *dev = encoder->base.dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_crtc *intel_crtc =
+ to_intel_crtc(encoder->base.crtc);
+ enum dpio_channel ch = vlv_dport_to_channel(dport);
+ enum pipe pipe = intel_crtc->pipe;
+ unsigned int lane_mask =
+ intel_dp_unused_lane_mask(intel_crtc->config->lane_count);
+ u32 val;
+
+ /*
+ * Must trick the second common lane into life.
+ * Otherwise we can't even access the PLL.
+ */
+ if (ch == DPIO_CH0 && pipe == PIPE_B)
+ dport->release_cl2_override =
+ !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true);
+
+ chv_phy_powergate_lanes(encoder, true, lane_mask);
+
+ mutex_lock(&dev_priv->sb_lock);
+
+ /* Assert data lane reset */
+ chv_data_lane_soft_reset(encoder, true);
+
+ /* program left/right clock distribution */
+ if (pipe != PIPE_B) {
+ val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
+ val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
+ if (ch == DPIO_CH0)
+ val |= CHV_BUFLEFTENA1_FORCE;
+ if (ch == DPIO_CH1)
+ val |= CHV_BUFRIGHTENA1_FORCE;
+ vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
+ } else {
+ val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
+ val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
+ if (ch == DPIO_CH0)
+ val |= CHV_BUFLEFTENA2_FORCE;
+ if (ch == DPIO_CH1)
+ val |= CHV_BUFRIGHTENA2_FORCE;
+ vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
+ }
+
+ /* program clock channel usage */
+ val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
+ val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
+ if (pipe != PIPE_B)
+ val &= ~CHV_PCS_USEDCLKCHANNEL;
+ else
+ val |= CHV_PCS_USEDCLKCHANNEL;
+ vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
+
+ if (intel_crtc->config->lane_count > 2) {
+ val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
+ val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
+ if (pipe != PIPE_B)
+ val &= ~CHV_PCS_USEDCLKCHANNEL;
+ else
+ val |= CHV_PCS_USEDCLKCHANNEL;
+ vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
+ }
+
+ /*
+ * This a a bit weird since generally CL
+ * matches the pipe, but here we need to
+ * pick the CL based on the port.
+ */
+ val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
+ if (pipe != PIPE_B)
+ val &= ~CHV_CMN_USEDCLKCHANNEL;
+ else
+ val |= CHV_CMN_USEDCLKCHANNEL;
+ vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
+
+ mutex_unlock(&dev_priv->sb_lock);
+}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index e0fcfa1..ad11313 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1323,6 +1323,11 @@ bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
bool
intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
+static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
+{
+ return ~((1 << lane_count) - 1) & 0xf;
+}
+
/* intel_dp_mst.c */
int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index c2d6139..4501906 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1658,81 +1658,9 @@ static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
{
- struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
- struct drm_device *dev = encoder->base.dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
- struct intel_crtc *intel_crtc =
- to_intel_crtc(encoder->base.crtc);
- enum dpio_channel ch = vlv_dport_to_channel(dport);
- enum pipe pipe = intel_crtc->pipe;
- u32 val;
-
intel_hdmi_prepare(encoder);
- /*
- * Must trick the second common lane into life.
- * Otherwise we can't even access the PLL.
- */
- if (ch == DPIO_CH0 && pipe == PIPE_B)
- dport->release_cl2_override =
- !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true);
-
- chv_phy_powergate_lanes(encoder, true, 0x0);
-
- mutex_lock(&dev_priv->sb_lock);
-
- /* Assert data lane reset */
- chv_data_lane_soft_reset(encoder, true);
-
- /* program left/right clock distribution */
- if (pipe != PIPE_B) {
- val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
- val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
- if (ch == DPIO_CH0)
- val |= CHV_BUFLEFTENA1_FORCE;
- if (ch == DPIO_CH1)
- val |= CHV_BUFRIGHTENA1_FORCE;
- vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
- } else {
- val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
- val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
- if (ch == DPIO_CH0)
- val |= CHV_BUFLEFTENA2_FORCE;
- if (ch == DPIO_CH1)
- val |= CHV_BUFRIGHTENA2_FORCE;
- vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
- }
-
- /* program clock channel usage */
- val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
- val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
- if (pipe != PIPE_B)
- val &= ~CHV_PCS_USEDCLKCHANNEL;
- else
- val |= CHV_PCS_USEDCLKCHANNEL;
- vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
-
- val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
- val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
- if (pipe != PIPE_B)
- val &= ~CHV_PCS_USEDCLKCHANNEL;
- else
- val |= CHV_PCS_USEDCLKCHANNEL;
- vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
-
- /*
- * This a a bit weird since generally CL
- * matches the pipe, but here we need to
- * pick the CL based on the port.
- */
- val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
- if (pipe != PIPE_B)
- val &= ~CHV_CMN_USEDCLKCHANNEL;
- else
- val |= CHV_CMN_USEDCLKCHANNEL;
- vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
-
- mutex_unlock(&dev_priv->sb_lock);
+ chv_phy_pre_pll_enable(encoder);
}
static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder)
--
2.4.11
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 5/6] drm/i915: Unduplicate CHV pre-encoder enabling phy logic
2016-04-08 15:31 [PATCH 0/6] Unduplicate CHV phy code Ander Conselvan de Oliveira
` (3 preceding siblings ...)
2016-04-08 15:31 ` [PATCH 4/6] drm/i915: Unduplicate CHV phy-releated pre pll enabling code Ander Conselvan de Oliveira
@ 2016-04-08 15:31 ` Ander Conselvan de Oliveira
2016-04-11 15:13 ` Ville Syrjälä
2016-04-08 15:31 ` [PATCH 6/6] drm/i915: Undiplicate CHV encoders' post pll disable code Ander Conselvan de Oliveira
2016-04-11 8:58 ` ✗ Fi.CI.BAT: failure for Unduplicate CHV phy code (rev2) Patchwork
6 siblings, 1 reply; 11+ messages in thread
From: Ander Conselvan de Oliveira @ 2016-04-08 15:31 UTC (permalink / raw)
To: intel-gfx; +Cc: Ander Conselvan de Oliveira
The only difference between the DP and HDMI versions was the lane count.
Since lane_count is now set appropriately for HDMI too, get rid of the
duplication and move this to intel_dpio_phy.c
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/intel_dp.c | 84 +------------------------------
drivers/gpu/drm/i915/intel_dpio_phy.c | 93 +++++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_hdmi.c | 69 +-------------------------
4 files changed, 99 insertions(+), 149 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7b2f453..e1b2f48 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3511,6 +3511,8 @@ void chv_set_phy_signal_level(struct intel_encoder *encoder,
void chv_data_lane_soft_reset(struct intel_encoder *encoder,
bool reset);
void chv_phy_pre_pll_enable(struct intel_encoder *encoder);
+void chv_phy_pre_encoder_enable(struct intel_encoder *encoder);
+void chv_phy_release_cl2_override(struct intel_encoder *encoder);
int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index fb0c9c5..8735738 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2851,91 +2851,11 @@ static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
static void chv_pre_enable_dp(struct intel_encoder *encoder)
{
- struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
- struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
- struct drm_device *dev = encoder->base.dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
- struct intel_crtc *intel_crtc =
- to_intel_crtc(encoder->base.crtc);
- enum dpio_channel ch = vlv_dport_to_channel(dport);
- int pipe = intel_crtc->pipe;
- int data, i, stagger;
- u32 val;
-
- mutex_lock(&dev_priv->sb_lock);
-
- /* allow hardware to manage TX FIFO reset source */
- val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
- val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
- vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
-
- if (intel_crtc->config->lane_count > 2) {
- val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
- val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
- vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
- }
-
- /* Program Tx lane latency optimal setting*/
- for (i = 0; i < intel_crtc->config->lane_count; i++) {
- /* Set the upar bit */
- if (intel_crtc->config->lane_count == 1)
- data = 0x0;
- else
- data = (i == 1) ? 0x0 : 0x1;
- vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
- data << DPIO_UPAR_SHIFT);
- }
-
- /* Data lane stagger programming */
- if (intel_crtc->config->port_clock > 270000)
- stagger = 0x18;
- else if (intel_crtc->config->port_clock > 135000)
- stagger = 0xd;
- else if (intel_crtc->config->port_clock > 67500)
- stagger = 0x7;
- else if (intel_crtc->config->port_clock > 33750)
- stagger = 0x4;
- else
- stagger = 0x2;
-
- val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
- val |= DPIO_TX2_STAGGER_MASK(0x1f);
- vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
-
- if (intel_crtc->config->lane_count > 2) {
- val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
- val |= DPIO_TX2_STAGGER_MASK(0x1f);
- vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
- }
-
- vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch),
- DPIO_LANESTAGGER_STRAP(stagger) |
- DPIO_LANESTAGGER_STRAP_OVRD |
- DPIO_TX1_STAGGER_MASK(0x1f) |
- DPIO_TX1_STAGGER_MULT(6) |
- DPIO_TX2_STAGGER_MULT(0));
-
- if (intel_crtc->config->lane_count > 2) {
- vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch),
- DPIO_LANESTAGGER_STRAP(stagger) |
- DPIO_LANESTAGGER_STRAP_OVRD |
- DPIO_TX1_STAGGER_MASK(0x1f) |
- DPIO_TX1_STAGGER_MULT(7) |
- DPIO_TX2_STAGGER_MULT(5));
- }
-
- /* Deassert data lane reset */
- chv_data_lane_soft_reset(encoder, false);
-
- mutex_unlock(&dev_priv->sb_lock);
+ chv_phy_pre_encoder_enable(encoder);
intel_enable_dp(encoder);
- /* Second common lane will stay alive on its own now */
- if (dport->release_cl2_override) {
- chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false);
- dport->release_cl2_override = false;
- }
+ chv_phy_release_cl2_override(encoder);
}
static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
index b4ca3ff..6078e74 100644
--- a/drivers/gpu/drm/i915/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
@@ -244,3 +244,96 @@ void chv_phy_pre_pll_enable(struct intel_encoder *encoder)
mutex_unlock(&dev_priv->sb_lock);
}
+
+void chv_phy_pre_encoder_enable(struct intel_encoder *encoder)
+{
+ struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
+ struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
+ struct drm_device *dev = encoder->base.dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_crtc *intel_crtc =
+ to_intel_crtc(encoder->base.crtc);
+ enum dpio_channel ch = vlv_dport_to_channel(dport);
+ int pipe = intel_crtc->pipe;
+ int data, i, stagger;
+ u32 val;
+
+ mutex_lock(&dev_priv->sb_lock);
+
+ /* allow hardware to manage TX FIFO reset source */
+ val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
+ val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
+ vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
+
+ if (intel_crtc->config->lane_count > 2) {
+ val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
+ val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
+ vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
+ }
+
+ /* Program Tx lane latency optimal setting*/
+ for (i = 0; i < intel_crtc->config->lane_count; i++) {
+ /* Set the upar bit */
+ if (intel_crtc->config->lane_count == 1)
+ data = 0x0;
+ else
+ data = (i == 1) ? 0x0 : 0x1;
+ vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
+ data << DPIO_UPAR_SHIFT);
+ }
+
+ /* Data lane stagger programming */
+ if (intel_crtc->config->port_clock > 270000)
+ stagger = 0x18;
+ else if (intel_crtc->config->port_clock > 135000)
+ stagger = 0xd;
+ else if (intel_crtc->config->port_clock > 67500)
+ stagger = 0x7;
+ else if (intel_crtc->config->port_clock > 33750)
+ stagger = 0x4;
+ else
+ stagger = 0x2;
+
+ val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
+ val |= DPIO_TX2_STAGGER_MASK(0x1f);
+ vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
+
+ if (intel_crtc->config->lane_count > 2) {
+ val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
+ val |= DPIO_TX2_STAGGER_MASK(0x1f);
+ vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
+ }
+
+ vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch),
+ DPIO_LANESTAGGER_STRAP(stagger) |
+ DPIO_LANESTAGGER_STRAP_OVRD |
+ DPIO_TX1_STAGGER_MASK(0x1f) |
+ DPIO_TX1_STAGGER_MULT(6) |
+ DPIO_TX2_STAGGER_MULT(0));
+
+ if (intel_crtc->config->lane_count > 2) {
+ vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch),
+ DPIO_LANESTAGGER_STRAP(stagger) |
+ DPIO_LANESTAGGER_STRAP_OVRD |
+ DPIO_TX1_STAGGER_MASK(0x1f) |
+ DPIO_TX1_STAGGER_MULT(7) |
+ DPIO_TX2_STAGGER_MULT(5));
+ }
+
+ /* Deassert data lane reset */
+ chv_data_lane_soft_reset(encoder, false);
+
+ mutex_unlock(&dev_priv->sb_lock);
+}
+
+void chv_phy_release_cl2_override(struct intel_encoder *encoder)
+{
+ struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+
+ /* Second common lane will stay alive on its own now */
+ if (dport->release_cl2_override) {
+ chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false);
+ dport->release_cl2_override = false;
+ }
+}
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 4501906..1eb6667 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1734,69 +1734,8 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
struct intel_crtc *intel_crtc =
to_intel_crtc(encoder->base.crtc);
const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
- enum dpio_channel ch = vlv_dport_to_channel(dport);
- int pipe = intel_crtc->pipe;
- int data, i, stagger;
- u32 val;
-
- mutex_lock(&dev_priv->sb_lock);
-
- /* allow hardware to manage TX FIFO reset source */
- val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
- val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
- vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
-
- val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
- val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
- vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
-
- /* Program Tx latency optimal setting */
- for (i = 0; i < 4; i++) {
- /* Set the upar bit */
- data = (i == 1) ? 0x0 : 0x1;
- vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
- data << DPIO_UPAR_SHIFT);
- }
-
- /* Data lane stagger programming */
- if (intel_crtc->config->port_clock > 270000)
- stagger = 0x18;
- else if (intel_crtc->config->port_clock > 135000)
- stagger = 0xd;
- else if (intel_crtc->config->port_clock > 67500)
- stagger = 0x7;
- else if (intel_crtc->config->port_clock > 33750)
- stagger = 0x4;
- else
- stagger = 0x2;
-
- val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
- val |= DPIO_TX2_STAGGER_MASK(0x1f);
- vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
-
- val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
- val |= DPIO_TX2_STAGGER_MASK(0x1f);
- vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
-
- vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch),
- DPIO_LANESTAGGER_STRAP(stagger) |
- DPIO_LANESTAGGER_STRAP_OVRD |
- DPIO_TX1_STAGGER_MASK(0x1f) |
- DPIO_TX1_STAGGER_MULT(6) |
- DPIO_TX2_STAGGER_MULT(0));
-
- vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch),
- DPIO_LANESTAGGER_STRAP(stagger) |
- DPIO_LANESTAGGER_STRAP_OVRD |
- DPIO_TX1_STAGGER_MASK(0x1f) |
- DPIO_TX1_STAGGER_MULT(7) |
- DPIO_TX2_STAGGER_MULT(5));
-
- /* Deassert data lane reset */
- chv_data_lane_soft_reset(encoder, false);
-
- mutex_unlock(&dev_priv->sb_lock);
+ chv_phy_pre_encoder_enable(encoder);
chv_set_phy_signal_level(encoder, 128, 102, false);
intel_hdmi->set_infoframes(&encoder->base,
@@ -1807,11 +1746,7 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
vlv_wait_port_ready(dev_priv, dport, 0x0);
- /* Second common lane will stay alive on its own now */
- if (dport->release_cl2_override) {
- chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false);
- dport->release_cl2_override = false;
- }
+ chv_phy_release_cl2_override(encoder);
}
static void intel_hdmi_destroy(struct drm_connector *connector)
--
2.4.11
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 6/6] drm/i915: Undiplicate CHV encoders' post pll disable code
2016-04-08 15:31 [PATCH 0/6] Unduplicate CHV phy code Ander Conselvan de Oliveira
` (4 preceding siblings ...)
2016-04-08 15:31 ` [PATCH 5/6] drm/i915: Unduplicate CHV pre-encoder enabling phy logic Ander Conselvan de Oliveira
@ 2016-04-08 15:31 ` Ander Conselvan de Oliveira
2016-04-11 8:58 ` ✗ Fi.CI.BAT: failure for Unduplicate CHV phy code (rev2) Patchwork
6 siblings, 0 replies; 11+ messages in thread
From: Ander Conselvan de Oliveira @ 2016-04-08 15:31 UTC (permalink / raw)
To: intel-gfx; +Cc: Ander Conselvan de Oliveira
The exact same code was used by HDMI and DP encoders, so move it to
intel_dpio_phy.c.
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_dp.c | 30 +-----------------------------
drivers/gpu/drm/i915/intel_dpio_phy.c | 33 +++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_hdmi.c | 30 +-----------------------------
4 files changed, 36 insertions(+), 58 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e1b2f48..5db6459 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3513,6 +3513,7 @@ void chv_data_lane_soft_reset(struct intel_encoder *encoder,
void chv_phy_pre_pll_enable(struct intel_encoder *encoder);
void chv_phy_pre_encoder_enable(struct intel_encoder *encoder);
void chv_phy_release_cl2_override(struct intel_encoder *encoder);
+void chv_phy_post_disable(struct intel_encoder *encoder);
int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 8735738..7fe3326 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2867,35 +2867,7 @@ static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
static void chv_dp_post_pll_disable(struct intel_encoder *encoder)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;
- u32 val;
-
- mutex_lock(&dev_priv->sb_lock);
-
- /* disable left/right clock distribution */
- if (pipe != PIPE_B) {
- val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
- val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
- vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
- } else {
- val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
- val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
- vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
- }
-
- mutex_unlock(&dev_priv->sb_lock);
-
- /*
- * Leave the power down bit cleared for at least one
- * lane so that chv_powergate_phy_ch() will power
- * on something when the channel is otherwise unused.
- * When the port is off and the override is removed
- * the lanes power down anyway, so otherwise it doesn't
- * really matter what the state of power down bits is
- * after this.
- */
- chv_phy_powergate_lanes(encoder, false, 0x0);
+ chv_phy_post_disable(encoder);
}
/*
diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
index 6078e74..1796f9b 100644
--- a/drivers/gpu/drm/i915/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
@@ -337,3 +337,36 @@ void chv_phy_release_cl2_override(struct intel_encoder *encoder)
dport->release_cl2_override = false;
}
}
+
+void chv_phy_post_disable(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;
+ u32 val;
+
+ mutex_lock(&dev_priv->sb_lock);
+
+ /* disable left/right clock distribution */
+ if (pipe != PIPE_B) {
+ val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
+ val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
+ vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
+ } else {
+ val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
+ val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
+ vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
+ }
+
+ mutex_unlock(&dev_priv->sb_lock);
+
+ /*
+ * Leave the power down bit cleared for at least one
+ * lane so that chv_powergate_phy_ch() will power
+ * on something when the channel is otherwise unused.
+ * When the port is off and the override is removed
+ * the lanes power down anyway, so otherwise it doesn't
+ * really matter what the state of power down bits is
+ * after this.
+ */
+ chv_phy_powergate_lanes(encoder, false, 0x0);
+}
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 1eb6667..9d23953 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1665,35 +1665,7 @@ static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;
- u32 val;
-
- mutex_lock(&dev_priv->sb_lock);
-
- /* disable left/right clock distribution */
- if (pipe != PIPE_B) {
- val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
- val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
- vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
- } else {
- val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
- val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
- vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
- }
-
- mutex_unlock(&dev_priv->sb_lock);
-
- /*
- * Leave the power down bit cleared for at least one
- * lane so that chv_powergate_phy_ch() will power
- * on something when the channel is otherwise unused.
- * When the port is off and the override is removed
- * the lanes power down anyway, so otherwise it doesn't
- * really matter what the state of power down bits is
- * after this.
- */
- chv_phy_powergate_lanes(encoder, false, 0x0);
+ chv_phy_post_disable(encoder);
}
static void vlv_hdmi_post_disable(struct intel_encoder *encoder)
--
2.4.11
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^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v2] drm/i915: Set crtc_state->lane_count for HDMI
2016-04-08 15:31 ` [PATCH 1/6] drm/i915: Set crtc_state->lane_count for HDMI Ander Conselvan de Oliveira
@ 2016-04-11 8:23 ` Ander Conselvan de Oliveira
0 siblings, 0 replies; 11+ messages in thread
From: Ander Conselvan de Oliveira @ 2016-04-11 8:23 UTC (permalink / raw)
To: intel-gfx; +Cc: Ander Conselvan de Oliveira
Set the lane count for HDMI to 4. This will make it easier to
unduplicate CHV phy code.
v2: Set lane_count in *_get_config() to please state checker. (0day)
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
drivers/gpu/drm/i915/intel_ddi.c | 1 +
drivers/gpu/drm/i915/intel_hdmi.c | 4 ++++
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 921edf1..96d7716 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1999,6 +1999,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
case TRANS_DDI_MODE_SELECT_HDMI:
pipe_config->has_hdmi_sink = true;
+ pipe_config->lane_count = 4;
intel_hdmi = enc_to_intel_hdmi(&encoder->base);
if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config))
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index b199ede..80d9841 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -953,6 +953,8 @@ static void intel_hdmi_get_config(struct intel_encoder *encoder,
dotclock /= pipe_config->pixel_multiplier;
pipe_config->base.adjusted_mode.crtc_clock = dotclock;
+
+ pipe_config->lane_count = 4;
}
static void intel_enable_hdmi_audio(struct intel_encoder *encoder)
@@ -1337,6 +1339,8 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder,
/* Set user selected PAR to incoming mode's member */
adjusted_mode->picture_aspect_ratio = intel_hdmi->aspect_ratio;
+ pipe_config->lane_count = 4;
+
return true;
}
--
2.4.11
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^ permalink raw reply related [flat|nested] 11+ messages in thread
* ✗ Fi.CI.BAT: failure for Unduplicate CHV phy code (rev2)
2016-04-08 15:31 [PATCH 0/6] Unduplicate CHV phy code Ander Conselvan de Oliveira
` (5 preceding siblings ...)
2016-04-08 15:31 ` [PATCH 6/6] drm/i915: Undiplicate CHV encoders' post pll disable code Ander Conselvan de Oliveira
@ 2016-04-11 8:58 ` Patchwork
6 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2016-04-11 8:58 UTC (permalink / raw)
To: Ander Conselvan de Oliveira; +Cc: intel-gfx
== Series Details ==
Series: Unduplicate CHV phy code (rev2)
URL : https://patchwork.freedesktop.org/series/5463/
State : failure
== Summary ==
Series 5463v2 Unduplicate CHV phy code
http://patchwork.freedesktop.org/api/1.0/series/5463/revisions/2/mbox/
Test drv_module_reload_basic:
pass -> DMESG-WARN (bsw-nuc-2)
pass -> DMESG-WARN (skl-nuci5)
pass -> DMESG-WARN (skl-i7k-2)
Test gem_exec_suspend:
Subgroup basic-s3:
pass -> DMESG-WARN (skl-nuci5)
pass -> DMESG-WARN (skl-i7k-2)
Test gem_storedw_loop:
Subgroup basic-blt:
pass -> SKIP (bsw-nuc-2)
Test kms_flip:
Subgroup basic-flip-vs-dpms:
pass -> DMESG-WARN (skl-nuci5)
pass -> DMESG-WARN (hsw-gt2)
pass -> DMESG-WARN (hsw-brixbox)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup basic-flip-vs-modeset:
pass -> DMESG-WARN (skl-nuci5)
pass -> DMESG-WARN (hsw-gt2)
pass -> DMESG-WARN (hsw-brixbox)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup basic-flip-vs-wf_vblank:
pass -> DMESG-WARN (skl-nuci5)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup basic-plain-flip:
pass -> DMESG-FAIL (bsw-nuc-2)
pass -> DMESG-WARN (skl-nuci5)
pass -> DMESG-WARN (skl-i7k-2)
Test kms_frontbuffer_tracking:
Subgroup basic:
pass -> DMESG-WARN (skl-nuci5)
pass -> DMESG-WARN (skl-i7k-2)
Test kms_pipe_crc_basic:
Subgroup hang-read-crc-pipe-a:
pass -> DMESG-WARN (skl-nuci5)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup hang-read-crc-pipe-b:
pass -> DMESG-WARN (skl-nuci5)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup hang-read-crc-pipe-c:
pass -> DMESG-WARN (skl-nuci5)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup nonblocking-crc-pipe-a:
pass -> DMESG-WARN (skl-nuci5)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup nonblocking-crc-pipe-a-frame-sequence:
pass -> DMESG-WARN (skl-nuci5)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup nonblocking-crc-pipe-b:
pass -> DMESG-WARN (skl-nuci5)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup nonblocking-crc-pipe-b-frame-sequence:
pass -> DMESG-WARN (skl-nuci5)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup nonblocking-crc-pipe-c:
pass -> DMESG-WARN (skl-nuci5)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup nonblocking-crc-pipe-c-frame-sequence:
pass -> DMESG-WARN (skl-nuci5)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup read-crc-pipe-a:
pass -> DMESG-WARN (skl-nuci5)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup read-crc-pipe-a-frame-sequence:
pass -> DMESG-WARN (skl-nuci5)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup read-crc-pipe-b:
pass -> DMESG-WARN (skl-nuci5)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup read-crc-pipe-b-frame-sequence:
pass -> DMESG-WARN (skl-nuci5)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup read-crc-pipe-c:
pass -> DMESG-WARN (skl-nuci5)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup read-crc-pipe-c-frame-sequence:
pass -> DMESG-WARN (skl-nuci5)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup suspend-read-crc-pipe-a:
pass -> DMESG-WARN (skl-nuci5)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup suspend-read-crc-pipe-b:
pass -> DMESG-WARN (skl-nuci5)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup suspend-read-crc-pipe-c:
pass -> DMESG-WARN (skl-nuci5)
pass -> DMESG-WARN (skl-i7k-2)
Test pm_rpm:
Subgroup basic-pci-d3-state:
pass -> DMESG-WARN (skl-nuci5)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup basic-rte:
pass -> DMESG-WARN (skl-nuci5)
pass -> DMESG-WARN (skl-i7k-2)
pass -> DMESG-WARN (byt-nuc) UNSTABLE
bdw-nuci7 total:196 pass:184 dwarn:0 dfail:0 fail:0 skip:12
bdw-ultra total:196 pass:175 dwarn:0 dfail:0 fail:0 skip:21
bsw-nuc-2 total:196 pass:156 dwarn:1 dfail:1 fail:0 skip:38
byt-nuc total:196 pass:160 dwarn:1 dfail:0 fail:0 skip:35
hsw-brixbox total:196 pass:172 dwarn:2 dfail:0 fail:0 skip:22
hsw-gt2 total:196 pass:177 dwarn:2 dfail:0 fail:0 skip:17
ivb-t430s total:196 pass:171 dwarn:0 dfail:0 fail:0 skip:25
skl-i7k-2 total:196 pass:146 dwarn:27 dfail:0 fail:0 skip:23
skl-nuci5 total:196 pass:158 dwarn:27 dfail:0 fail:0 skip:11
snb-dellxps total:196 pass:162 dwarn:0 dfail:0 fail:0 skip:34
snb-x220t total:196 pass:162 dwarn:0 dfail:0 fail:1 skip:33
BOOT FAILED for ilk-hp8440p
Results at /archive/results/CI_IGT_test/Patchwork_1858/
56aa709c9614bf7f39ee255fd0ddf4f1b2743387 drm-intel-nightly: 2016y-04m-09d-11h-10m-49s UTC integration manifest
61f4d77f519166d5dcd1f582483cd89554eacd0e drm/i915: Undiplicate CHV encoders' post pll disable code
2901269dbcc7274da49a0480353afabcd5503e48 drm/i915: Unduplicate CHV pre-encoder enabling phy logic
dd24bdbb9e94083c812e5a0eb8ce51c0df8f890c drm/i915: Unduplicate CHV phy-releated pre pll enabling code
8b5488b016589d9a65c648d0c0a1d8a2e2748448 drm/i915: Unduplicate chv_data_lane_soft_reset()
74da835937ce7aad70d8ebed2e83b13056076c54 drm/i915: Unduplicate CHV signal level code
5a531fa667e7505b0597b80fac79fa4ea88c4abf drm/i915: Set crtc_state->lane_count for HDMI
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 2/6] drm/i915: Unduplicate CHV signal level code
2016-04-08 15:31 ` [PATCH 2/6] drm/i915: Unduplicate CHV signal level code Ander Conselvan de Oliveira
@ 2016-04-11 15:09 ` Ville Syrjälä
0 siblings, 0 replies; 11+ messages in thread
From: Ville Syrjälä @ 2016-04-11 15:09 UTC (permalink / raw)
To: Ander Conselvan de Oliveira; +Cc: intel-gfx
On Fri, Apr 08, 2016 at 06:31:42PM +0300, Ander Conselvan de Oliveira wrote:
> The code for programming voltage swing and emphasis was duplicated
> between DP and HDMI code. Move that to a new file, intel_dpio_phy.c.
>
> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> drivers/gpu/drm/i915/i915_drv.h | 5 ++
> drivers/gpu/drm/i915/intel_dp.c | 103 ++--------------------------
> drivers/gpu/drm/i915/intel_dpio_phy.c | 122 ++++++++++++++++++++++++++++++++++
> drivers/gpu/drm/i915/intel_hdmi.c | 72 +-------------------
> 5 files changed, 136 insertions(+), 167 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/intel_dpio_phy.c
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 7ffb51b..eb45e28 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -57,6 +57,7 @@ i915-y += intel_audio.o \
> intel_bios.o \
> intel_color.o \
> intel_display.o \
> + intel_dpio_phy.o \
> intel_dpll_mgr.o \
> intel_fbc.o \
> intel_fifo_underrun.o \
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 4ebd3ff..3c393e3 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -3504,6 +3504,11 @@ void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
> u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
> void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
>
> +/* intel_dpio_phy.c */
> +void chv_set_phy_signal_level(struct intel_encoder *encoder,
> + u32 deemph_reg_value, u32 margin_reg_value,
> + bool uniq_trans_scale);
> +
> int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
> int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index da0c3d2..5ba72b0 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -3339,23 +3339,12 @@ static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
> return 0;
> }
>
> -static bool chv_need_uniq_trans_scale(uint8_t train_set)
> -{
> - return (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) == DP_TRAIN_PRE_EMPH_LEVEL_0 &&
> - (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) == DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
> -}
> -
> static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
> {
> - struct drm_device *dev = intel_dp_to_dev(intel_dp);
> - struct drm_i915_private *dev_priv = dev->dev_private;
> - struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
> - struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
> - u32 deemph_reg_value, margin_reg_value, val;
> + struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> + u32 deemph_reg_value, margin_reg_value;
> + bool uniq_trans_scale = false;
> uint8_t train_set = intel_dp->train_set[0];
> - enum dpio_channel ch = vlv_dport_to_channel(dport);
> - enum pipe pipe = intel_crtc->pipe;
> - int i;
>
> switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
> case DP_TRAIN_PRE_EMPH_LEVEL_0:
> @@ -3375,7 +3364,7 @@ static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
> case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
> deemph_reg_value = 128;
> margin_reg_value = 154;
> - /* FIXME extra to set for 1200 */
> + uniq_trans_scale = true;
> break;
> default:
> return 0;
> @@ -3427,88 +3416,8 @@ static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
> return 0;
> }
>
> - mutex_lock(&dev_priv->sb_lock);
> -
> - /* Clear calc init */
> - val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
> - val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
> - val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
> - val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
> - vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
> -
> - if (intel_crtc->config->lane_count > 2) {
> - val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
> - val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
> - val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
> - val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
> - vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
> - }
> -
> - val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
> - val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
> - val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
> - vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
> -
> - if (intel_crtc->config->lane_count > 2) {
> - val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
> - val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
> - val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
> - vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
> - }
> -
> - /* Program swing deemph */
> - for (i = 0; i < intel_crtc->config->lane_count; i++) {
> - val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
> - val &= ~DPIO_SWING_DEEMPH9P5_MASK;
> - val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
> - vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
> - }
> -
> - /* Program swing margin */
> - for (i = 0; i < intel_crtc->config->lane_count; i++) {
> - val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
> -
> - val &= ~DPIO_SWING_MARGIN000_MASK;
> - val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
> -
> - /*
> - * Supposedly this value shouldn't matter when unique transition
> - * scale is disabled, but in fact it does matter. Let's just
> - * always program the same value and hope it's OK.
> - */
> - val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
> - val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT;
> -
> - vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
> - }
> -
> - /*
> - * The document said it needs to set bit 27 for ch0 and bit 26
> - * for ch1. Might be a typo in the doc.
> - * For now, for this unique transition scale selection, set bit
> - * 27 for ch0 and ch1.
> - */
> - for (i = 0; i < intel_crtc->config->lane_count; i++) {
> - val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
> - if (chv_need_uniq_trans_scale(train_set))
> - val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
> - else
> - val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
> - vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
> - }
> -
> - /* Start swing calculation */
> - val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
> - val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
> - vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
> -
> - if (intel_crtc->config->lane_count > 2) {
> - val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
> - val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
> - vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
> - }
> -
> - mutex_unlock(&dev_priv->sb_lock);
> + chv_set_phy_signal_level(encoder, deemph_reg_value,
> + margin_reg_value, uniq_trans_scale);
>
> return 0;
> }
> diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
> new file mode 100644
> index 0000000..cbe1703d
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
> @@ -0,0 +1,122 @@
> +/*
> + * Copyright © 2014-2016 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
> + * DEALINGS IN THE SOFTWARE.
> + */
> +
> +#include "intel_drv.h"
> +
> +void chv_set_phy_signal_level(struct intel_encoder *encoder,
> + u32 deemph_reg_value, u32 margin_reg_value,
> + bool uniq_trans_scale)
> +{
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
> + struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
Could do some s/intel_crtc/crtc/ while moving.
> + enum dpio_channel ch = vlv_dport_to_channel(dport);
> + enum pipe pipe = intel_crtc->pipe;
> + u32 val;
> + int i;
> +
> + mutex_lock(&dev_priv->sb_lock);
> +
> + /* Clear calc init */
> + val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
> + val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
> + val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
> + val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
> + vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
> +
> + if (intel_crtc->config->lane_count > 2) {
> + val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
> + val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
> + val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
> + val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
> + vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
> + }
> +
> + val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
> + val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
> + val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
> + vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
> +
> + if (intel_crtc->config->lane_count > 2) {
> + val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
> + val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
> + val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
> + vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
> + }
> +
> + /* Program swing deemph */
> + for (i = 0; i < intel_crtc->config->lane_count; i++) {
> + val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
> + val &= ~DPIO_SWING_DEEMPH9P5_MASK;
> + val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
> + vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
> + }
> +
> + /* Program swing margin */
> + for (i = 0; i < intel_crtc->config->lane_count; i++) {
> + val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
> +
> + val &= ~DPIO_SWING_MARGIN000_MASK;
> + val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
> +
> + /*
> + * Supposedly this value shouldn't matter when unique transition
> + * scale is disabled, but in fact it does matter. Let's just
> + * always program the same value and hope it's OK.
> + */
> + val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
> + val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT;
> +
> + vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
> + }
> +
> + /*
> + * The document said it needs to set bit 27 for ch0 and bit 26
> + * for ch1. Might be a typo in the doc.
> + * For now, for this unique transition scale selection, set bit
> + * 27 for ch0 and ch1.
> + */
> + for (i = 0; i < intel_crtc->config->lane_count; i++) {
> + val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
> + if (uniq_trans_scale)
> + val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
> + else
> + val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
> + vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
> + }
> +
> + /* Start swing calculation */
> + val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
> + val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
> + vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
> +
> + if (intel_crtc->config->lane_count > 2) {
> + val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
> + val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
> + vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
> + }
> +
> + mutex_unlock(&dev_priv->sb_lock);
> +
> +}
> +
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index 2dc6e00..107a80a 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -1911,78 +1911,10 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
> /* Deassert data lane reset */
> chv_data_lane_soft_reset(encoder, false);
>
> - /* Clear calc init */
> - val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
> - val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
> - val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
> - val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
> - vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
> -
> - val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
> - val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
> - val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
> - val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
> - vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
> -
> - val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
> - val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
> - val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
> - vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
> -
> - val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
> - val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
> - val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
> - vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
> -
> - /* FIXME: Program the support xxx V-dB */
> - /* Use 800mV-0dB */
I'd keep this comment so that people don't have to wonder where the
128 and 102 magic numbers came from.
> - for (i = 0; i < 4; i++) {
> - val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
> - val &= ~DPIO_SWING_DEEMPH9P5_MASK;
> - val |= 128 << DPIO_SWING_DEEMPH9P5_SHIFT;
> - vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
> - }
> -
> - for (i = 0; i < 4; i++) {
> - val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
> -
> - val &= ~DPIO_SWING_MARGIN000_MASK;
> - val |= 102 << DPIO_SWING_MARGIN000_SHIFT;
> -
> - /*
> - * Supposedly this value shouldn't matter when unique transition
> - * scale is disabled, but in fact it does matter. Let's just
> - * always program the same value and hope it's OK.
> - */
> - val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
> - val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT;
> -
> - vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
> - }
> -
> - /*
> - * The document said it needs to set bit 27 for ch0 and bit 26
> - * for ch1. Might be a typo in the doc.
> - * For now, for this unique transition scale selection, set bit
> - * 27 for ch0 and ch1.
> - */
> - for (i = 0; i < 4; i++) {
> - val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
> - val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
> - vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
> - }
> -
> - /* Start swing calculation */
> - val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
> - val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
> - vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
> -
> - val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
> - val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
> - vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
> -
> mutex_unlock(&dev_priv->sb_lock);
>
> + chv_set_phy_signal_level(encoder, 128, 102, false);
> +
> intel_hdmi->set_infoframes(&encoder->base,
> intel_crtc->config->has_hdmi_sink,
> adjusted_mode);
> --
> 2.4.11
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 5/6] drm/i915: Unduplicate CHV pre-encoder enabling phy logic
2016-04-08 15:31 ` [PATCH 5/6] drm/i915: Unduplicate CHV pre-encoder enabling phy logic Ander Conselvan de Oliveira
@ 2016-04-11 15:13 ` Ville Syrjälä
0 siblings, 0 replies; 11+ messages in thread
From: Ville Syrjälä @ 2016-04-11 15:13 UTC (permalink / raw)
To: Ander Conselvan de Oliveira; +Cc: intel-gfx
On Fri, Apr 08, 2016 at 06:31:45PM +0300, Ander Conselvan de Oliveira wrote:
> The only difference between the DP and HDMI versions was the lane count.
> Since lane_count is now set appropriately for HDMI too, get rid of the
> duplication and move this to intel_dpio_phy.c
>
> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 +
> drivers/gpu/drm/i915/intel_dp.c | 84 +------------------------------
> drivers/gpu/drm/i915/intel_dpio_phy.c | 93 +++++++++++++++++++++++++++++++++++
> drivers/gpu/drm/i915/intel_hdmi.c | 69 +-------------------------
> 4 files changed, 99 insertions(+), 149 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 7b2f453..e1b2f48 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -3511,6 +3511,8 @@ void chv_set_phy_signal_level(struct intel_encoder *encoder,
> void chv_data_lane_soft_reset(struct intel_encoder *encoder,
> bool reset);
> void chv_phy_pre_pll_enable(struct intel_encoder *encoder);
> +void chv_phy_pre_encoder_enable(struct intel_encoder *encoder);
> +void chv_phy_release_cl2_override(struct intel_encoder *encoder);
>
> int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
> int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index fb0c9c5..8735738 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -2851,91 +2851,11 @@ static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
>
> static void chv_pre_enable_dp(struct intel_encoder *encoder)
> {
> - struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> - struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
> - struct drm_device *dev = encoder->base.dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> - struct intel_crtc *intel_crtc =
> - to_intel_crtc(encoder->base.crtc);
> - enum dpio_channel ch = vlv_dport_to_channel(dport);
> - int pipe = intel_crtc->pipe;
> - int data, i, stagger;
> - u32 val;
> -
> - mutex_lock(&dev_priv->sb_lock);
> -
> - /* allow hardware to manage TX FIFO reset source */
> - val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
> - val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
> - vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
> -
> - if (intel_crtc->config->lane_count > 2) {
> - val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
> - val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
> - vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
> - }
> -
> - /* Program Tx lane latency optimal setting*/
> - for (i = 0; i < intel_crtc->config->lane_count; i++) {
> - /* Set the upar bit */
> - if (intel_crtc->config->lane_count == 1)
> - data = 0x0;
> - else
> - data = (i == 1) ? 0x0 : 0x1;
> - vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
> - data << DPIO_UPAR_SHIFT);
> - }
> -
> - /* Data lane stagger programming */
> - if (intel_crtc->config->port_clock > 270000)
> - stagger = 0x18;
> - else if (intel_crtc->config->port_clock > 135000)
> - stagger = 0xd;
> - else if (intel_crtc->config->port_clock > 67500)
> - stagger = 0x7;
> - else if (intel_crtc->config->port_clock > 33750)
> - stagger = 0x4;
> - else
> - stagger = 0x2;
> -
> - val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
> - val |= DPIO_TX2_STAGGER_MASK(0x1f);
> - vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
> -
> - if (intel_crtc->config->lane_count > 2) {
> - val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
> - val |= DPIO_TX2_STAGGER_MASK(0x1f);
> - vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
> - }
> -
> - vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch),
> - DPIO_LANESTAGGER_STRAP(stagger) |
> - DPIO_LANESTAGGER_STRAP_OVRD |
> - DPIO_TX1_STAGGER_MASK(0x1f) |
> - DPIO_TX1_STAGGER_MULT(6) |
> - DPIO_TX2_STAGGER_MULT(0));
> -
> - if (intel_crtc->config->lane_count > 2) {
> - vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch),
> - DPIO_LANESTAGGER_STRAP(stagger) |
> - DPIO_LANESTAGGER_STRAP_OVRD |
> - DPIO_TX1_STAGGER_MASK(0x1f) |
> - DPIO_TX1_STAGGER_MULT(7) |
> - DPIO_TX2_STAGGER_MULT(5));
> - }
> -
> - /* Deassert data lane reset */
> - chv_data_lane_soft_reset(encoder, false);
> -
> - mutex_unlock(&dev_priv->sb_lock);
> + chv_phy_pre_encoder_enable(encoder);
>
> intel_enable_dp(encoder);
>
> - /* Second common lane will stay alive on its own now */
These comments would be better left in the caller.
> - if (dport->release_cl2_override) {
> - chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false);
> - dport->release_cl2_override = false;
> - }
> + chv_phy_release_cl2_override(encoder);
> }
>
> static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
> diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
> index b4ca3ff..6078e74 100644
> --- a/drivers/gpu/drm/i915/intel_dpio_phy.c
> +++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
> @@ -244,3 +244,96 @@ void chv_phy_pre_pll_enable(struct intel_encoder *encoder)
>
> mutex_unlock(&dev_priv->sb_lock);
> }
> +
> +void chv_phy_pre_encoder_enable(struct intel_encoder *encoder)
> +{
> + struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> + struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
> + struct drm_device *dev = encoder->base.dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + struct intel_crtc *intel_crtc =
> + to_intel_crtc(encoder->base.crtc);
> + enum dpio_channel ch = vlv_dport_to_channel(dport);
> + int pipe = intel_crtc->pipe;
> + int data, i, stagger;
> + u32 val;
> +
> + mutex_lock(&dev_priv->sb_lock);
> +
> + /* allow hardware to manage TX FIFO reset source */
> + val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
> + val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
> + vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
> +
> + if (intel_crtc->config->lane_count > 2) {
> + val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
> + val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
> + vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
> + }
> +
> + /* Program Tx lane latency optimal setting*/
> + for (i = 0; i < intel_crtc->config->lane_count; i++) {
> + /* Set the upar bit */
> + if (intel_crtc->config->lane_count == 1)
> + data = 0x0;
> + else
> + data = (i == 1) ? 0x0 : 0x1;
> + vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
> + data << DPIO_UPAR_SHIFT);
> + }
> +
> + /* Data lane stagger programming */
> + if (intel_crtc->config->port_clock > 270000)
> + stagger = 0x18;
> + else if (intel_crtc->config->port_clock > 135000)
> + stagger = 0xd;
> + else if (intel_crtc->config->port_clock > 67500)
> + stagger = 0x7;
> + else if (intel_crtc->config->port_clock > 33750)
> + stagger = 0x4;
> + else
> + stagger = 0x2;
> +
> + val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
> + val |= DPIO_TX2_STAGGER_MASK(0x1f);
> + vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
> +
> + if (intel_crtc->config->lane_count > 2) {
> + val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
> + val |= DPIO_TX2_STAGGER_MASK(0x1f);
> + vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
> + }
> +
> + vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch),
> + DPIO_LANESTAGGER_STRAP(stagger) |
> + DPIO_LANESTAGGER_STRAP_OVRD |
> + DPIO_TX1_STAGGER_MASK(0x1f) |
> + DPIO_TX1_STAGGER_MULT(6) |
> + DPIO_TX2_STAGGER_MULT(0));
> +
> + if (intel_crtc->config->lane_count > 2) {
> + vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch),
> + DPIO_LANESTAGGER_STRAP(stagger) |
> + DPIO_LANESTAGGER_STRAP_OVRD |
> + DPIO_TX1_STAGGER_MASK(0x1f) |
> + DPIO_TX1_STAGGER_MULT(7) |
> + DPIO_TX2_STAGGER_MULT(5));
> + }
> +
> + /* Deassert data lane reset */
> + chv_data_lane_soft_reset(encoder, false);
> +
> + mutex_unlock(&dev_priv->sb_lock);
> +}
> +
> +void chv_phy_release_cl2_override(struct intel_encoder *encoder)
> +{
> + struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +
> + /* Second common lane will stay alive on its own now */
> + if (dport->release_cl2_override) {
> + chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false);
> + dport->release_cl2_override = false;
> + }
> +}
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index 4501906..1eb6667 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -1734,69 +1734,8 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
> struct intel_crtc *intel_crtc =
> to_intel_crtc(encoder->base.crtc);
> const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
> - enum dpio_channel ch = vlv_dport_to_channel(dport);
> - int pipe = intel_crtc->pipe;
> - int data, i, stagger;
> - u32 val;
> -
> - mutex_lock(&dev_priv->sb_lock);
> -
> - /* allow hardware to manage TX FIFO reset source */
> - val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
> - val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
> - vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
> -
> - val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
> - val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
> - vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
> -
> - /* Program Tx latency optimal setting */
> - for (i = 0; i < 4; i++) {
> - /* Set the upar bit */
> - data = (i == 1) ? 0x0 : 0x1;
> - vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
> - data << DPIO_UPAR_SHIFT);
> - }
> -
> - /* Data lane stagger programming */
> - if (intel_crtc->config->port_clock > 270000)
> - stagger = 0x18;
> - else if (intel_crtc->config->port_clock > 135000)
> - stagger = 0xd;
> - else if (intel_crtc->config->port_clock > 67500)
> - stagger = 0x7;
> - else if (intel_crtc->config->port_clock > 33750)
> - stagger = 0x4;
> - else
> - stagger = 0x2;
> -
> - val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
> - val |= DPIO_TX2_STAGGER_MASK(0x1f);
> - vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
> -
> - val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
> - val |= DPIO_TX2_STAGGER_MASK(0x1f);
> - vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
> -
> - vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch),
> - DPIO_LANESTAGGER_STRAP(stagger) |
> - DPIO_LANESTAGGER_STRAP_OVRD |
> - DPIO_TX1_STAGGER_MASK(0x1f) |
> - DPIO_TX1_STAGGER_MULT(6) |
> - DPIO_TX2_STAGGER_MULT(0));
> -
> - vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch),
> - DPIO_LANESTAGGER_STRAP(stagger) |
> - DPIO_LANESTAGGER_STRAP_OVRD |
> - DPIO_TX1_STAGGER_MASK(0x1f) |
> - DPIO_TX1_STAGGER_MULT(7) |
> - DPIO_TX2_STAGGER_MULT(5));
> -
> - /* Deassert data lane reset */
> - chv_data_lane_soft_reset(encoder, false);
> -
> - mutex_unlock(&dev_priv->sb_lock);
>
> + chv_phy_pre_encoder_enable(encoder);
> chv_set_phy_signal_level(encoder, 128, 102, false);
>
> intel_hdmi->set_infoframes(&encoder->base,
> @@ -1807,11 +1746,7 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
>
> vlv_wait_port_ready(dev_priv, dport, 0x0);
>
> - /* Second common lane will stay alive on its own now */
> - if (dport->release_cl2_override) {
> - chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false);
> - dport->release_cl2_override = false;
> - }
> + chv_phy_release_cl2_override(encoder);
> }
>
> static void intel_hdmi_destroy(struct drm_connector *connector)
> --
> 2.4.11
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2016-04-11 15:13 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-04-08 15:31 [PATCH 0/6] Unduplicate CHV phy code Ander Conselvan de Oliveira
2016-04-08 15:31 ` [PATCH 1/6] drm/i915: Set crtc_state->lane_count for HDMI Ander Conselvan de Oliveira
2016-04-11 8:23 ` [PATCH v2] " Ander Conselvan de Oliveira
2016-04-08 15:31 ` [PATCH 2/6] drm/i915: Unduplicate CHV signal level code Ander Conselvan de Oliveira
2016-04-11 15:09 ` Ville Syrjälä
2016-04-08 15:31 ` [PATCH 3/6] drm/i915: Unduplicate chv_data_lane_soft_reset() Ander Conselvan de Oliveira
2016-04-08 15:31 ` [PATCH 4/6] drm/i915: Unduplicate CHV phy-releated pre pll enabling code Ander Conselvan de Oliveira
2016-04-08 15:31 ` [PATCH 5/6] drm/i915: Unduplicate CHV pre-encoder enabling phy logic Ander Conselvan de Oliveira
2016-04-11 15:13 ` Ville Syrjälä
2016-04-08 15:31 ` [PATCH 6/6] drm/i915: Undiplicate CHV encoders' post pll disable code Ander Conselvan de Oliveira
2016-04-11 8:58 ` ✗ Fi.CI.BAT: failure for Unduplicate CHV phy code (rev2) Patchwork
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