From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39705) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aod1w-0003aw-Qm for qemu-devel@nongnu.org; Fri, 08 Apr 2016 16:29:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aod1v-00022E-Ns for qemu-devel@nongnu.org; Fri, 08 Apr 2016 16:29:24 -0400 Received: from mail-wm0-x242.google.com ([2a00:1450:400c:c09::242]:35329) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aod1v-000229-Df for qemu-devel@nongnu.org; Fri, 08 Apr 2016 16:29:23 -0400 Received: by mail-wm0-x242.google.com with SMTP id a140so6837526wma.2 for ; Fri, 08 Apr 2016 13:29:23 -0700 (PDT) Received: from 640k.lan (94-39-141-76.adsl-ull.clienti.tiscali.it. [94.39.141.76]) by smtp.gmail.com with ESMTPSA id w10sm3849168wjz.9.2016.04.08.13.29.21 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 08 Apr 2016 13:29:22 -0700 (PDT) Sender: Paolo Bonzini From: Paolo Bonzini Date: Fri, 8 Apr 2016 22:28:29 +0200 Message-Id: <1460147350-7601-10-git-send-email-pbonzini@redhat.com> In-Reply-To: <1460147350-7601-1-git-send-email-pbonzini@redhat.com> References: <1460147350-7601-1-git-send-email-pbonzini@redhat.com> Subject: [Qemu-devel] [PATCH 09/50] target-lm32: make cpu-qom.h not target specific List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Make LM32CPU an opaque type within cpu-qom.h, and move all definitions of private methods, as well as all type definitions that require knowledge of the layout to cpu.h. This helps making files independent of NEED_CPU_H if they only need to pass around CPU pointers. Signed-off-by: Paolo Bonzini --- target-lm32/cpu-qom.h | 41 +---------------------------------------- target-lm32/cpu.h | 44 ++++++++++++++++++++++++++++++++++++++++++-- 2 files changed, 43 insertions(+), 42 deletions(-) diff --git a/target-lm32/cpu-qom.h b/target-lm32/cpu-qom.h index 54989e4..b423d25 100644 --- a/target-lm32/cpu-qom.h +++ b/target-lm32/cpu-qom.h @@ -47,45 +47,6 @@ typedef struct LM32CPUClass { void (*parent_reset)(CPUState *cpu); } LM32CPUClass; -/** - * LM32CPU: - * @env: #CPULM32State - * - * A LatticeMico32 CPU. - */ -typedef struct LM32CPU { - /*< private >*/ - CPUState parent_obj; - /*< public >*/ - - CPULM32State env; - - uint32_t revision; - uint8_t num_interrupts; - uint8_t num_breakpoints; - uint8_t num_watchpoints; - uint32_t features; -} LM32CPU; - -static inline LM32CPU *lm32_env_get_cpu(CPULM32State *env) -{ - return container_of(env, LM32CPU, env); -} - -#define ENV_GET_CPU(e) CPU(lm32_env_get_cpu(e)) - -#define ENV_OFFSET offsetof(LM32CPU, env) - -#ifndef CONFIG_USER_ONLY -extern const struct VMStateDescription vmstate_lm32_cpu; -#endif - -void lm32_cpu_do_interrupt(CPUState *cpu); -bool lm32_cpu_exec_interrupt(CPUState *cs, int int_req); -void lm32_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, - int flags); -hwaddr lm32_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); -int lm32_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); -int lm32_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); +typedef struct LM32CPU LM32CPU; #endif diff --git a/target-lm32/cpu.h b/target-lm32/cpu.h index f220fc0..22ffa68 100644 --- a/target-lm32/cpu.h +++ b/target-lm32/cpu.h @@ -25,6 +25,7 @@ #define CPUArchState struct CPULM32State #include "qemu-common.h" +#include "cpu-qom.h" #include "exec/cpu-defs.h" struct CPULM32State; typedef struct CPULM32State CPULM32State; @@ -180,6 +181,47 @@ struct CPULM32State { }; +/** + * LM32CPU: + * @env: #CPULM32State + * + * A LatticeMico32 CPU. + */ +struct LM32CPU { + /*< private >*/ + CPUState parent_obj; + /*< public >*/ + + CPULM32State env; + + uint32_t revision; + uint8_t num_interrupts; + uint8_t num_breakpoints; + uint8_t num_watchpoints; + uint32_t features; +}; + +static inline LM32CPU *lm32_env_get_cpu(CPULM32State *env) +{ + return container_of(env, LM32CPU, env); +} + +#define ENV_GET_CPU(e) CPU(lm32_env_get_cpu(e)) + +#define ENV_OFFSET offsetof(LM32CPU, env) + +#ifndef CONFIG_USER_ONLY +extern const struct VMStateDescription vmstate_lm32_cpu; +#endif + +void lm32_cpu_do_interrupt(CPUState *cpu); +bool lm32_cpu_exec_interrupt(CPUState *cs, int int_req); +void lm32_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, + int flags); +hwaddr lm32_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); +int lm32_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); +int lm32_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); + typedef enum { LM32_WP_DISABLED = 0, LM32_WP_READ, @@ -193,8 +235,6 @@ static inline lm32_wp_t lm32_wp_type(uint32_t dc, int idx) return (dc >> (idx+1)*2) & 0x3; } -#include "cpu-qom.h" - LM32CPU *cpu_lm32_init(const char *cpu_model); int cpu_lm32_exec(CPUState *cpu); /* you can call this signal handler from your SIGBUS and SIGSEGV -- 1.8.3.1