From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39751) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aod21-0003mY-UN for qemu-devel@nongnu.org; Fri, 08 Apr 2016 16:29:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aod1z-00023K-Od for qemu-devel@nongnu.org; Fri, 08 Apr 2016 16:29:29 -0400 Received: from mail-wm0-x241.google.com ([2a00:1450:400c:c09::241]:36458) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aod1z-00023C-El for qemu-devel@nongnu.org; Fri, 08 Apr 2016 16:29:27 -0400 Received: by mail-wm0-x241.google.com with SMTP id l6so6823674wml.3 for ; Fri, 08 Apr 2016 13:29:27 -0700 (PDT) Received: from 640k.lan (94-39-141-76.adsl-ull.clienti.tiscali.it. [94.39.141.76]) by smtp.gmail.com with ESMTPSA id w10sm3849168wjz.9.2016.04.08.13.29.25 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 08 Apr 2016 13:29:26 -0700 (PDT) Sender: Paolo Bonzini From: Paolo Bonzini Date: Fri, 8 Apr 2016 22:28:33 +0200 Message-Id: <1460147350-7601-14-git-send-email-pbonzini@redhat.com> In-Reply-To: <1460147350-7601-1-git-send-email-pbonzini@redhat.com> References: <1460147350-7601-1-git-send-email-pbonzini@redhat.com> Subject: [Qemu-devel] [PATCH 13/50] target-ppc: do not use target_ulong in cpu-qom.h List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Bring the PowerPCCPUClass handle_mmu_fault method type into line with the one in CPUState. Using vaddr also makes the cpu-qom.h file target independent. Signed-off-by: Paolo Bonzini --- target-ppc/cpu-qom.h | 3 +-- target-ppc/mmu-hash32.c | 2 +- target-ppc/mmu-hash32.h | 2 +- target-ppc/mmu-hash64.c | 2 +- target-ppc/mmu-hash64.h | 2 +- 5 files changed, 5 insertions(+), 6 deletions(-) diff --git a/target-ppc/cpu-qom.h b/target-ppc/cpu-qom.h index eb822a3..bab501f 100644 --- a/target-ppc/cpu-qom.h +++ b/target-ppc/cpu-qom.h @@ -73,8 +73,7 @@ typedef struct PowerPCCPUClass { void (*init_proc)(CPUPPCState *env); int (*check_pow)(CPUPPCState *env); #if defined(CONFIG_SOFTMMU) - int (*handle_mmu_fault)(PowerPCCPU *cpu, target_ulong eaddr, int rwx, - int mmu_idx); + int (*handle_mmu_fault)(PowerPCCPU *cpu, vaddr eaddr, int rwx, int mmu_idx); #endif bool (*interrupts_big_endian)(PowerPCCPU *cpu); } PowerPCCPUClass; diff --git a/target-ppc/mmu-hash32.c b/target-ppc/mmu-hash32.c index 39abb2f..06ce4d6 100644 --- a/target-ppc/mmu-hash32.c +++ b/target-ppc/mmu-hash32.c @@ -383,7 +383,7 @@ static hwaddr ppc_hash32_pte_raddr(target_ulong sr, ppc_hash_pte32_t pte, return (rpn & ~mask) | (eaddr & mask); } -int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr, int rwx, +int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx, int mmu_idx) { CPUState *cs = CPU(cpu); diff --git a/target-ppc/mmu-hash32.h b/target-ppc/mmu-hash32.h index afbb9dd..aaceacd 100644 --- a/target-ppc/mmu-hash32.h +++ b/target-ppc/mmu-hash32.h @@ -5,7 +5,7 @@ hwaddr get_pteg_offset32(PowerPCCPU *cpu, hwaddr hash); hwaddr ppc_hash32_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr); -int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, target_ulong address, int rw, +int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, vaddr address, int rw, int mmu_idx); /* diff --git a/target-ppc/mmu-hash64.c b/target-ppc/mmu-hash64.c index 72c4ab5..5184626 100644 --- a/target-ppc/mmu-hash64.c +++ b/target-ppc/mmu-hash64.c @@ -589,7 +589,7 @@ unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu, return 0; } -int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr, +int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx, int mmu_idx) { CPUState *cs = CPU(cpu); diff --git a/target-ppc/mmu-hash64.h b/target-ppc/mmu-hash64.h index 9bf8b9b..6423b9f 100644 --- a/target-ppc/mmu-hash64.h +++ b/target-ppc/mmu-hash64.h @@ -9,7 +9,7 @@ void dump_slb(FILE *f, fprintf_function cpu_fprintf, PowerPCCPU *cpu); int ppc_store_slb(PowerPCCPU *cpu, target_ulong slot, target_ulong esid, target_ulong vsid); hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr); -int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, target_ulong address, int rw, +int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr address, int rw, int mmu_idx); void ppc_hash64_store_hpte(PowerPCCPU *cpu, target_ulong index, target_ulong pte0, target_ulong pte1); -- 1.8.3.1