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From: Chris Wilson <chris@chris-wilson.co.uk>
To: intel-gfx@lists.freedesktop.org,
	Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Subject: [PATCH 7/9] drm/i915: Move the magical deferred context allocation into the request
Date: Tue, 19 Apr 2016 07:49:18 +0100	[thread overview]
Message-ID: <1461048560-31983-8-git-send-email-chris@chris-wilson.co.uk> (raw)
In-Reply-To: <1461048560-31983-1-git-send-email-chris@chris-wilson.co.uk>

We can hide more details of execlists from higher level code by removing
the explicit call to create an execlist context into its first use.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/i915_gem_execbuffer.c |  8 --------
 drivers/gpu/drm/i915/intel_lrc.c           | 21 ++++++++++++++-------
 drivers/gpu/drm/i915/intel_lrc.h           |  2 --
 3 files changed, 14 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 0d210c383487..3da5978ac0f7 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -1080,14 +1080,6 @@ i915_gem_validate_context(struct drm_device *dev, struct drm_file *file,
 		return ERR_PTR(-EIO);
 	}
 
-	if (i915.enable_execlists && !ctx->engine[engine->id].state) {
-		int ret = intel_lr_context_deferred_alloc(ctx, engine);
-		if (ret) {
-			DRM_DEBUG("Could not create LRC %u: %d\n", ctx_id, ret);
-			return ERR_PTR(ret);
-		}
-	}
-
 	return ctx;
 }
 
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index c104015813d3..b0d20af38574 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -227,6 +227,8 @@ enum {
 #define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT	0x17
 #define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT	0x26
 
+static int execlists_context_deferred_alloc(struct intel_context *ctx,
+					    struct intel_engine_cs *engine);
 static int intel_lr_context_pin(struct intel_context *ctx,
 				struct intel_engine_cs *engine);
 
@@ -672,8 +674,6 @@ int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request
 	struct intel_engine_cs *engine = request->engine;
 	int ret;
 
-	request->ringbuf = request->ctx->engine[engine->id].ringbuf;
-
 	if (i915.enable_guc_submission) {
 		/*
 		 * Check that the GuC has space for the request before
@@ -687,6 +687,14 @@ int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request
 			return ret;
 	}
 
+	if (request->ctx->engine[engine->id].state == NULL) {
+		ret = execlists_context_deferred_alloc(request->ctx, engine);
+		if (ret)
+			return ret;
+	}
+
+	request->ringbuf = request->ctx->engine[engine->id].ringbuf;
+
 	ret = intel_lr_context_pin(request->ctx, engine);
 	if (ret)
 		return ret;
@@ -2091,7 +2099,7 @@ logical_ring_init(struct intel_engine_cs *engine)
 	if (ret)
 		goto error;
 
-	ret = intel_lr_context_deferred_alloc(dctx, engine);
+	ret = execlists_context_deferred_alloc(dctx, engine);
 	if (ret)
 		goto error;
 
@@ -2541,7 +2549,7 @@ uint32_t intel_lr_context_size(struct intel_engine_cs *engine)
 }
 
 /**
- * intel_lr_context_deferred_alloc() - create the LRC specific bits of a context
+ * execlists_context_deferred_alloc() - create the LRC specific bits of a context
  * @ctx: LR context to create.
  * @ring: engine to be used with the context.
  *
@@ -2553,9 +2561,8 @@ uint32_t intel_lr_context_size(struct intel_engine_cs *engine)
  *
  * Return: non-zero on error.
  */
-
-int intel_lr_context_deferred_alloc(struct intel_context *ctx,
-				    struct intel_engine_cs *engine)
+static int execlists_context_deferred_alloc(struct intel_context *ctx,
+					    struct intel_engine_cs *engine)
 {
 	struct drm_i915_gem_object *ctx_obj;
 	uint32_t context_size;
diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
index b17ab79333aa..8bea937973f6 100644
--- a/drivers/gpu/drm/i915/intel_lrc.h
+++ b/drivers/gpu/drm/i915/intel_lrc.h
@@ -102,8 +102,6 @@ static inline void intel_logical_ring_emit_reg(struct intel_ringbuffer *ringbuf,
 
 void intel_lr_context_free(struct intel_context *ctx);
 uint32_t intel_lr_context_size(struct intel_engine_cs *engine);
-int intel_lr_context_deferred_alloc(struct intel_context *ctx,
-				    struct intel_engine_cs *engine);
 void intel_lr_context_unpin(struct intel_context *ctx,
 			    struct intel_engine_cs *engine);
 
-- 
2.8.0.rc3

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  parent reply	other threads:[~2016-04-19  6:49 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-04-15 11:54 [PATCH 0/3] GuC premature LRC unpin Tvrtko Ursulin
2016-04-15 11:54 ` [PATCH 1/3] drm/i915: Refactor execlists default context pinning Tvrtko Ursulin
2016-04-15 12:16   ` Chris Wilson
2016-04-15 13:21     ` Tvrtko Ursulin
2016-04-15 11:54 ` [PATCH 2/3] drm/i915/guc: Keep the previous context pinned until the next one has been completed Tvrtko Ursulin
2016-04-15 12:12   ` Chris Wilson
2016-04-15 13:16     ` Tvrtko Ursulin
2016-04-15 11:54 ` [PATCH 3/3] DO NOT MERGE: drm/i915: Enable GuC submission Tvrtko Ursulin
2016-04-15 15:24 ` ✗ Fi.CI.BAT: warning for GuC premature LRC unpin Patchwork
2016-04-19  6:49 ` Premature " Chris Wilson
2016-04-19  6:49   ` [PATCH 1/9] drm/i915: Assign every HW context a unique ID Chris Wilson
2016-04-19  8:57     ` Tvrtko Ursulin
2016-04-19  9:04       ` Chris Wilson
2016-04-19  9:20         ` Tvrtko Ursulin
2016-04-19  6:49   ` [PATCH 2/9] drm/i915: Replace the pinned context address with its " Chris Wilson
2016-04-19  9:03     ` Tvrtko Ursulin
2016-04-19  6:49   ` [PATCH 3/9] drm/i915: Refactor execlists default context pinning Chris Wilson
2016-04-19  9:16     ` Tvrtko Ursulin
2016-04-19  9:55       ` [PATCH] " Chris Wilson
2016-04-19  6:49   ` [PATCH 4/9] drm/i915: Remove early l3-remap Chris Wilson
2016-04-19  9:41     ` Tvrtko Ursulin
2016-04-19 10:07       ` [PATCH 1/3] drm/i915: L3 cache remapping is part of context switching Chris Wilson
2016-04-19 10:07         ` [PATCH 2/3] drm/i915: Consolidate L3 remapping LRI Chris Wilson
2016-04-19 10:21           ` Tvrtko Ursulin
2016-04-19 10:07         ` [PATCH 3/3] drm/i915: Remove early l3-remap Chris Wilson
2016-04-19 10:23           ` Tvrtko Ursulin
2016-04-19 10:20         ` [PATCH 1/3] drm/i915: L3 cache remapping is part of context switching Tvrtko Ursulin
2016-04-19  6:49   ` [PATCH 5/9] drm/i915: Rearrange switch_context to load the aliasing ppgtt on first use Chris Wilson
2016-04-19  9:52     ` Tvrtko Ursulin
2016-04-19  6:49   ` [PATCH 6/9] drm/i915: Move context initialisation to first-use Chris Wilson
2016-04-19  9:57     ` Tvrtko Ursulin
2016-04-19 10:15     ` Tvrtko Ursulin
2016-04-19 10:55       ` Chris Wilson
2016-04-19  6:49   ` Chris Wilson [this message]
2016-04-19 10:28     ` [PATCH 7/9] drm/i915: Move the magical deferred context allocation into the request Tvrtko Ursulin
2016-04-19  6:49   ` [PATCH 8/9] drm/i915: Track the previous pinned context inside " Chris Wilson
2016-04-19 12:02     ` Tvrtko Ursulin
2016-04-19 12:14       ` Chris Wilson
2016-04-19  6:49   ` [PATCH 9/9] drm/i915: Move releasing of the GEM request from free to retire/cancel Chris Wilson
2016-04-19 12:16     ` Tvrtko Ursulin

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