From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753488AbcDVHEm (ORCPT ); Fri, 22 Apr 2016 03:04:42 -0400 Received: from mail-by2on0116.outbound.protection.outlook.com ([207.46.100.116]:20256 "EHLO na01-by2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751681AbcDVHEl (ORCPT ); Fri, 22 Apr 2016 03:04:41 -0400 X-Greylist: delayed 917 seconds by postgrey-1.27 at vger.kernel.org; Fri, 22 Apr 2016 03:04:40 EDT Authentication-Results: spf=neutral (sender IP is 192.88.158.2) smtp.mailfrom=freescale.com; nxp.com; dkim=none (message not signed) header.d=none;nxp.com; dmarc=none action=none header.from=freescale.com; From: Yunhui Cui To: , , CC: , , , , Yunhui Cui Subject: [PATCH v2 5/9] mtd: spi-nor: fsl-quadspi:Support qspi for ls2080a Date: Fri, 22 Apr 2016 14:39:48 +0800 Message-ID: <1461307192-866-5-git-send-email-B56489@freescale.com> X-Mailer: git-send-email 2.1.0.27.g96db324 In-Reply-To: <1461307192-866-1-git-send-email-B56489@freescale.com> References: <1461307192-866-1-git-send-email-B56489@freescale.com> X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:192.88.158.2;IPV:NLI;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10019020)(6009001)(2980300002)(189002)(199003)(47776003)(5003940100001)(4001450100002)(48376002)(1096002)(105586002)(5008740100001)(586003)(76176999)(104016004)(229853001)(50986999)(2201001)(86362001)(6806005)(1220700001)(106466001)(4326007)(50466002)(19580395003)(87936001)(19580405001)(2950100001)(50226001)(11100500001)(81166005)(92566002)(5001770100001)(189998001)(77096005)(2906002)(36756003)(7059030);DIR:OUT;SFP:1102;SCL:1;SRVR:BY2PR03MB074;H:az84smr01.freescale.net;FPR:;SPF:Neutral;MLV:sfv;MX:1;A:1;LANG:en; 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So as to software, the driver need support to the feature. Signed-off-by: Yunhui Cui Signed-off-by: Yunhui Cui --- drivers/mtd/spi-nor/fsl-quadspi.c | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-quadspi.c index 16ebabbd..5d9d192 100644 --- a/drivers/mtd/spi-nor/fsl-quadspi.c +++ b/drivers/mtd/spi-nor/fsl-quadspi.c @@ -41,6 +41,8 @@ #define QUADSPI_QUIRK_TKT253890 (1 << 2) /* Controller cannot wake up from wait mode, TKT245618 */ #define QUADSPI_QUIRK_TKT245618 (1 << 3) +/* QSPI_AMBA_BASE is internally added by SOC design */ +#define QUADSPI_AMBA_BASE_INTERNAL (0x10000) /* The registers */ #define QUADSPI_MCR 0x00 @@ -217,6 +219,7 @@ enum fsl_qspi_devtype { FSL_QUADSPI_IMX7D, FSL_QUADSPI_IMX6UL, FSL_QUADSPI_LS1021A, + FSL_QUADSPI_LS2080A, }; struct fsl_qspi_devtype_data { @@ -270,6 +273,14 @@ static struct fsl_qspi_devtype_data ls1021a_data = { .driver_data = 0, }; +static struct fsl_qspi_devtype_data ls2080a_data = { + .devtype = FSL_QUADSPI_LS2080A, + .rxfifo = 128, + .txfifo = 64, + .ahb_buf_size = 1024, + .driver_data = QUADSPI_AMBA_BASE_INTERNAL, +}; + #define FSL_QSPI_MAX_CHIP 4 struct fsl_qspi { struct spi_nor nor[FSL_QSPI_MAX_CHIP]; @@ -312,6 +323,11 @@ static inline int needs_wakeup_wait_mode(struct fsl_qspi *q) return q->devtype_data->driver_data & QUADSPI_QUIRK_TKT245618; } +static inline int has_added_amba_base_internal(struct fsl_qspi *q) +{ + return q->devtype_data->driver_data & QUADSPI_AMBA_BASE_INTERNAL; +} + /* * R/W functions for big- or little-endian registers: * The qSPI controller's endian is independent of the CPU core's endian. @@ -558,8 +574,11 @@ fsl_qspi_runcmd(struct fsl_qspi *q, u8 cmd, unsigned int addr, int len) /* save the reg */ reg = qspi_readl(q, base + QUADSPI_MCR); - qspi_writel(q, q->memmap_phy + q->chip_base_addr + addr, - base + QUADSPI_SFAR); + if (has_added_amba_base_internal(q)) + qspi_writel(q, q->chip_base_addr + addr, base + QUADSPI_SFAR); + else + qspi_writel(q, q->memmap_phy + q->chip_base_addr + addr, + base + QUADSPI_SFAR); qspi_writel(q, QUADSPI_RBCT_WMRK_MASK | QUADSPI_RBCT_RXBRD_USEIPS, base + QUADSPI_RBCT); qspi_writel(q, reg | QUADSPI_MCR_CLR_RXF_MASK, base + QUADSPI_MCR); @@ -849,6 +868,7 @@ static const struct of_device_id fsl_qspi_dt_ids[] = { { .compatible = "fsl,imx7d-qspi", .data = (void *)&imx7d_data, }, { .compatible = "fsl,imx6ul-qspi", .data = (void *)&imx6ul_data, }, { .compatible = "fsl,ls1021a-qspi", .data = (void *)&ls1021a_data, }, + { .compatible = "fsl,ls2080a-qspi", .data = (void *)&ls2080a_data, }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, fsl_qspi_dt_ids); -- 2.1.0.27.g96db324 From mboxrd@z Thu Jan 1 00:00:00 1970 From: B56489@freescale.com (Yunhui Cui) Date: Fri, 22 Apr 2016 14:39:48 +0800 Subject: [PATCH v2 5/9] mtd: spi-nor: fsl-quadspi:Support qspi for ls2080a In-Reply-To: <1461307192-866-1-git-send-email-B56489@freescale.com> References: <1461307192-866-1-git-send-email-B56489@freescale.com> Message-ID: <1461307192-866-5-git-send-email-B56489@freescale.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org There is a hardware feature that qspi_amba_base is added internally by SOC design on ls2080a. So as to software, the driver need support to the feature. Signed-off-by: Yunhui Cui Signed-off-by: Yunhui Cui --- drivers/mtd/spi-nor/fsl-quadspi.c | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-quadspi.c index 16ebabbd..5d9d192 100644 --- a/drivers/mtd/spi-nor/fsl-quadspi.c +++ b/drivers/mtd/spi-nor/fsl-quadspi.c @@ -41,6 +41,8 @@ #define QUADSPI_QUIRK_TKT253890 (1 << 2) /* Controller cannot wake up from wait mode, TKT245618 */ #define QUADSPI_QUIRK_TKT245618 (1 << 3) +/* QSPI_AMBA_BASE is internally added by SOC design */ +#define QUADSPI_AMBA_BASE_INTERNAL (0x10000) /* The registers */ #define QUADSPI_MCR 0x00 @@ -217,6 +219,7 @@ enum fsl_qspi_devtype { FSL_QUADSPI_IMX7D, FSL_QUADSPI_IMX6UL, FSL_QUADSPI_LS1021A, + FSL_QUADSPI_LS2080A, }; struct fsl_qspi_devtype_data { @@ -270,6 +273,14 @@ static struct fsl_qspi_devtype_data ls1021a_data = { .driver_data = 0, }; +static struct fsl_qspi_devtype_data ls2080a_data = { + .devtype = FSL_QUADSPI_LS2080A, + .rxfifo = 128, + .txfifo = 64, + .ahb_buf_size = 1024, + .driver_data = QUADSPI_AMBA_BASE_INTERNAL, +}; + #define FSL_QSPI_MAX_CHIP 4 struct fsl_qspi { struct spi_nor nor[FSL_QSPI_MAX_CHIP]; @@ -312,6 +323,11 @@ static inline int needs_wakeup_wait_mode(struct fsl_qspi *q) return q->devtype_data->driver_data & QUADSPI_QUIRK_TKT245618; } +static inline int has_added_amba_base_internal(struct fsl_qspi *q) +{ + return q->devtype_data->driver_data & QUADSPI_AMBA_BASE_INTERNAL; +} + /* * R/W functions for big- or little-endian registers: * The qSPI controller's endian is independent of the CPU core's endian. @@ -558,8 +574,11 @@ fsl_qspi_runcmd(struct fsl_qspi *q, u8 cmd, unsigned int addr, int len) /* save the reg */ reg = qspi_readl(q, base + QUADSPI_MCR); - qspi_writel(q, q->memmap_phy + q->chip_base_addr + addr, - base + QUADSPI_SFAR); + if (has_added_amba_base_internal(q)) + qspi_writel(q, q->chip_base_addr + addr, base + QUADSPI_SFAR); + else + qspi_writel(q, q->memmap_phy + q->chip_base_addr + addr, + base + QUADSPI_SFAR); qspi_writel(q, QUADSPI_RBCT_WMRK_MASK | QUADSPI_RBCT_RXBRD_USEIPS, base + QUADSPI_RBCT); qspi_writel(q, reg | QUADSPI_MCR_CLR_RXF_MASK, base + QUADSPI_MCR); @@ -849,6 +868,7 @@ static const struct of_device_id fsl_qspi_dt_ids[] = { { .compatible = "fsl,imx7d-qspi", .data = (void *)&imx7d_data, }, { .compatible = "fsl,imx6ul-qspi", .data = (void *)&imx6ul_data, }, { .compatible = "fsl,ls1021a-qspi", .data = (void *)&ls1021a_data, }, + { .compatible = "fsl,ls2080a-qspi", .data = (void *)&ls2080a_data, }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, fsl_qspi_dt_ids); -- 2.1.0.27.g96db324