[PATCH v4 00/21] Add support for GuC-based SLPC

[PATCH v4 00/21] Add support for GuC-based SLPC

[tom.orourke]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

SLPC (Single Loop Power Controller) is a replacement for
some host-based power management features.  The SLPC
implemenation runs in firmware on GuC.

This series has been tested with SKL guc firmware
version 6.1.

The graphics power management features in SLPC in those
versions are called GTPERF, BALANCER, and DCC.

GTPERF is a combination of DFPS (Dynamic FPS) and Turbo.
DFPS adjusts requested graphics frequency to maintain
target framerate.  Turbo adjusts requested graphics
frequency to maintain target GT busyness; this includes
an adaptive boost turbo method.

BALANCER adjusts balance between power budgets for IA
and GT in power limited scenarios.  BALANCER is only
active when all display pipes are in "game" mode.

DCC (Duty Cycle Control) adjusts requested graphics
frequency and stalls guc-scheduler to maintain actual
graphics frequency in efficient range.

The v3 series can be found in the archive at
"[Intel-gfx] [PATCH v3 00/25] Add support for GuC-based SLPC"
https://lists.freedesktop.org/archives/intel-gfx/2016-April/091771.html

This v4 series incorporates feedback from internal code 
reviews for Android and Yocto projects.  This series also 
drops the Broxton patches; the Broxton firmware has not 
been published yet.  Broxton support can be added later 
when the Broxton firmware is available. 

Also, the "DO NOT MERGE" patches to enable SLPC and guc 
submission by default have been dropped.  These can be 
added later after SLPC has been shown to outperform 
host-based power management; this may require a newer 
version of the GuC firmware.

With SLPC disabled by default, this series should be 
safe to merge now. 

VIZ-6773, VIZ-6889

Sagar Arun Kamble (4):
  drm/i915/slpc: Add Display mode event related data structures
  drm/i915/slpc: Notification of Display mode change
  drm/i915/slpc: Notification of Refresh Rate change
  drm/i915/slpc: Fail intel_runtime_suspend if SLPC or RPS not active

Tom O'Rourke (17):
  drm/i915/slpc: Expose guc functions for use with SLPC
  drm/i915/slpc: Add has_slpc capability flag
  drm/i915/slpc: Add slpc_version_check
  drm/i915/slpc: Add enable_slpc module parameter
  drm/i915/slpc: Use intel_slpc_* functions if supported
  drm/i915/slpc: Enable SLPC in guc if supported
  drm/i915/slpc: If using SLPC, do not set frequency
  drm/i915/slpc: Allocate/Release/Initialize SLPC shared data
  drm/i915/slpc: Setup rps frequency values during SLPC init
  drm/i915/slpc: Update current requested frequency
  drm/i915/slpc: Send reset event
  drm/i915/slpc: Send shutdown event
  drm/i915/slpc: Add slpc_status enum values
  drm/i915/slpc: Add parameter unset/set/get functions
  drm/i915/slpc: Add slpc support for max/min freq
  drm/i915/slpc: Add enable/disable debugfs for slpc
  drm/i915/slpc: Add i915_slpc_info to debugfs

 drivers/gpu/drm/i915/Makefile              |   5 +-
 drivers/gpu/drm/i915/i915_debugfs.c        | 456 +++++++++++++++++++++++++
 drivers/gpu/drm/i915/i915_drv.c            |   4 +-
 drivers/gpu/drm/i915/i915_drv.h            |   7 +
 drivers/gpu/drm/i915/i915_guc_submission.c |   6 +-
 drivers/gpu/drm/i915/i915_params.c         |   6 +
 drivers/gpu/drm/i915/i915_params.h         |   1 +
 drivers/gpu/drm/i915/i915_reg.h            |   1 +
 drivers/gpu/drm/i915/i915_sysfs.c          |  21 ++
 drivers/gpu/drm/i915/intel_display.c       |   2 +
 drivers/gpu/drm/i915/intel_dp.c            |   2 +
 drivers/gpu/drm/i915/intel_drv.h           |  11 +
 drivers/gpu/drm/i915/intel_guc.h           |  13 +
 drivers/gpu/drm/i915/intel_guc_loader.c    |  36 ++
 drivers/gpu/drm/i915/intel_pm.c            |  42 ++-
 drivers/gpu/drm/i915/intel_slpc.c          | 516 +++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_slpc.h          | 217 ++++++++++++
 17 files changed, 1329 insertions(+), 17 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_slpc.c
 create mode 100644 drivers/gpu/drm/i915/intel_slpc.h

-- 
1.9.1

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[PATCH 01/21] drm/i915/slpc: Expose guc functions for use with SLPC

[tom.orourke]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

Expose host2guc_action for use by SLPC in intel_slpc.c.

Expose functions to allocate and release objects used
by GuC to be used for SLPC shared memory object.

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
---
 drivers/gpu/drm/i915/i915_guc_submission.c | 6 +++---
 drivers/gpu/drm/i915/intel_guc.h           | 4 ++++
 2 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
index 72d6665..aba1155 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -75,7 +75,7 @@ static inline bool host2guc_action_response(struct drm_i915_private *dev_priv,
 	return GUC2HOST_IS_RESPONSE(val);
 }
 
-static int host2guc_action(struct intel_guc *guc, u32 *data, u32 len)
+int host2guc_action(struct intel_guc *guc, u32 *data, u32 len)
 {
 	struct drm_i915_private *dev_priv = guc_to_i915(guc);
 	u32 status;
@@ -581,7 +581,7 @@ int i915_guc_submit(struct i915_guc_client *client,
  *
  * Return:	A drm_i915_gem_object if successful, otherwise NULL.
  */
-static struct drm_i915_gem_object *gem_allocate_guc_obj(struct drm_device *dev,
+struct drm_i915_gem_object *gem_allocate_guc_obj(struct drm_device *dev,
 							u32 size)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -612,7 +612,7 @@ static struct drm_i915_gem_object *gem_allocate_guc_obj(struct drm_device *dev,
  * gem_release_guc_obj() - Release gem object allocated for GuC usage
  * @obj:	gem obj to be released
  */
-static void gem_release_guc_obj(struct drm_i915_gem_object *obj)
+void gem_release_guc_obj(struct drm_i915_gem_object *obj)
 {
 	if (!obj)
 		return;
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 9d79c4c..4d24856 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -146,10 +146,14 @@ extern int intel_guc_suspend(struct drm_device *dev);
 extern int intel_guc_resume(struct drm_device *dev);
 
 /* i915_guc_submission.c */
+int host2guc_action(struct intel_guc *guc, u32 *data, u32 len);
 int i915_guc_submission_init(struct drm_device *dev);
 int i915_guc_submission_enable(struct drm_device *dev);
 int i915_guc_submit(struct i915_guc_client *client,
 		    struct drm_i915_gem_request *rq);
+struct drm_i915_gem_object *gem_allocate_guc_obj(struct drm_device *dev,
+							u32 size);
+void gem_release_guc_obj(struct drm_i915_gem_object *obj);
 void i915_guc_submission_disable(struct drm_device *dev);
 void i915_guc_submission_fini(struct drm_device *dev);
 int i915_guc_wq_check_space(struct i915_guc_client *client);
-- 
1.9.1

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[PATCH 02/21] drm/i915/slpc: Add has_slpc capability flag

[tom.orourke]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

Add has_slpc capablity flag to indicate GuC firmware
supports single loop power control (SLPC).  SLPC is
a replacement for some host-based power management
features.

v2: fix whitespace (Sagar)

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 32f0597..393da67 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -740,6 +740,7 @@ struct intel_csr {
 	func(is_kabylake) sep \
 	func(is_preliminary) sep \
 	func(has_fbc) sep \
+	func(has_slpc) sep \
 	func(has_pipe_cxsr) sep \
 	func(has_hotplug) sep \
 	func(cursor_needs_physical) sep \
@@ -2692,6 +2693,7 @@ struct drm_i915_cmd_table {
 
 #define HAS_GUC_UCODE(dev)	(IS_GEN9(dev) && !IS_KABYLAKE(dev))
 #define HAS_GUC_SCHED(dev)	(IS_GEN9(dev) && !IS_KABYLAKE(dev))
+#define HAS_SLPC(dev)		(INTEL_INFO(dev)->has_slpc)
 
 #define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
 				    INTEL_INFO(dev)->gen >= 8)
-- 
1.9.1

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[PATCH 03/21] drm/i915/slpc: Add slpc_version_check

[tom.orourke]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

The SLPC interface has changed and could continue to
change.  Only GuC versions known to be compatible are
supported here.

On Skylake, GuC firmware v6 is supported.  Other
platforms and versions can be added here later.

This patch also adds has_slpc to skylake info.

v2: Move slpc_version_check to intel_guc_ucode_init
v3: fix whitespace (Sagar)
---
 drivers/gpu/drm/i915/i915_drv.c         |  1 +
 drivers/gpu/drm/i915/intel_guc_loader.c | 14 ++++++++++++++
 2 files changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index d37c0a6..cc22fa0 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -334,6 +334,7 @@ static const struct intel_device_info intel_skylake_info = {
 	BDW_FEATURES,
 	.is_skylake = 1,
 	.gen = 9,
+	.has_slpc = 1,
 };
 
 static const struct intel_device_info intel_skylake_gt3_info = {
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 876e5da..87702cd 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -116,6 +116,18 @@ static void direct_interrupts_to_guc(struct drm_i915_private *dev_priv)
 	I915_WRITE(GUC_WD_VECS_IER, ~irqs);
 }
 
+static void slpc_version_check(struct drm_device *dev,
+			       struct intel_guc_fw *guc_fw)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_device_info *info;
+
+	if (IS_SKYLAKE(dev) && (guc_fw->guc_fw_major_found != 6)) {
+		info = (struct intel_device_info *) &dev_priv->info;
+		info->has_slpc = 0;
+	}
+}
+
 static u32 get_gttype(struct drm_i915_private *dev_priv)
 {
 	/* XXX: GT type based on PCI device ID? field seems unused by fw */
@@ -666,6 +678,8 @@ void intel_guc_ucode_init(struct drm_device *dev)
 	DRM_DEBUG_DRIVER("GuC firmware pending, path %s\n", fw_path);
 	guc_fw_fetch(dev, guc_fw);
 	/* status must now be FAIL or SUCCESS */
+
+	slpc_version_check(dev, guc_fw);
 }
 
 /**
-- 
1.9.1

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[PATCH 04/21] drm/i915/slpc: Add enable_slpc module parameter

[tom.orourke]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

i915.enable_slpc is used to override the default for slpc usage.
The expected values are -1=auto, 0=disabled [default], 1=enabled.

slpc_enable_sanitize() converts i915.enable_slpc to either 0 or 1.
Interpretation of default value is based on HAS_SLPC(), after
slpc_version_check().  This function also enforces the requirement
that guc_submission is required for slpc.

intel_slpc_enabled() returns 1 if SLPC should be used.

v2: Add early call to sanitize enable_slpc in intel_guc_ucode_init

Suggested-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
---
 drivers/gpu/drm/i915/i915_params.c      |  6 ++++++
 drivers/gpu/drm/i915/i915_params.h      |  1 +
 drivers/gpu/drm/i915/intel_guc.h        |  6 ++++++
 drivers/gpu/drm/i915/intel_guc_loader.c | 19 +++++++++++++++++++
 4 files changed, 32 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
index 383c076..9617bc2 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -36,6 +36,7 @@ struct i915_params i915 __read_mostly = {
 	.enable_dc = -1,
 	.enable_fbc = -1,
 	.enable_execlists = -1,
+	.enable_slpc = 0,
 	.enable_hangcheck = true,
 	.enable_ppgtt = -1,
 	.enable_psr = -1,
@@ -128,6 +129,11 @@ MODULE_PARM_DESC(enable_execlists,
 	"Override execlists usage. "
 	"(-1=auto [default], 0=disabled, 1=enabled)");
 
+module_param_named_unsafe(enable_slpc, i915.enable_slpc, int, 0400);
+MODULE_PARM_DESC(enable_slpc,
+	"Override single-loop-power-controller (slpc) usage. "
+	"(-1=auto, 0=disabled [default], 1=enabled)");
+
 module_param_named_unsafe(enable_psr, i915.enable_psr, int, 0600);
 MODULE_PARM_DESC(enable_psr, "Enable PSR "
 		 "(0=disabled, 1=enabled - link mode chosen per-platform, 2=force link-standby mode, 3=force link-off mode) "
diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
index 65e73dd..e9f7eed 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -39,6 +39,7 @@ struct i915_params {
 	int enable_fbc;
 	int enable_ppgtt;
 	int enable_execlists;
+	int enable_slpc;
 	int enable_psr;
 	unsigned int preliminary_hw_support;
 	int disable_power_well;
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 4d24856..cecfe4e 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -137,6 +137,12 @@ struct intel_guc {
 	uint32_t last_seqno[GUC_MAX_ENGINES_NUM];
 };
 
+static inline int intel_slpc_enabled(void)
+{
+	WARN_ON(i915.enable_slpc < 0);
+	return i915.enable_slpc;
+}
+
 /* intel_guc_loader.c */
 extern void intel_guc_ucode_init(struct drm_device *dev);
 extern int intel_guc_ucode_load(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 87702cd..174cc34 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -116,6 +116,21 @@ static void direct_interrupts_to_guc(struct drm_i915_private *dev_priv)
 	I915_WRITE(GUC_WD_VECS_IER, ~irqs);
 }
 
+static void slpc_enable_sanitize(struct drm_device *dev)
+{
+	/* handle default case */
+	if (i915.enable_slpc < 0)
+		i915.enable_slpc = HAS_SLPC(dev);
+
+	/* slpc requires hardware support and compatible firmware */
+	if (!HAS_SLPC(dev))
+		i915.enable_slpc = 0;
+
+	/* slpc requires guc submission */
+	if (!i915.enable_guc_submission)
+		i915.enable_slpc = 0;
+}
+
 static void slpc_version_check(struct drm_device *dev,
 			       struct intel_guc_fw *guc_fw)
 {
@@ -126,6 +141,8 @@ static void slpc_version_check(struct drm_device *dev,
 		info = (struct intel_device_info *) &dev_priv->info;
 		info->has_slpc = 0;
 	}
+
+	slpc_enable_sanitize(dev);
 }
 
 static u32 get_gttype(struct drm_i915_private *dev_priv)
@@ -657,6 +674,8 @@ void intel_guc_ucode_init(struct drm_device *dev)
 		fw_path = "";	/* unknown device */
 	}
 
+	slpc_enable_sanitize(dev);
+
 	if (!i915.enable_guc_submission)
 		return;
 
-- 
1.9.1

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[PATCH 05/21] drm/i915/slpc: Use intel_slpc_* functions if supported

[tom.orourke]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

On platforms with SLPC support: call intel_slpc_*()
functions from corresponding intel_*_gt_powersave()
functions; and do not use rps functions.

v2: return void instead of ignored error code (Paulo)
    enable/disable RC6 in SLPC flows (Sagar)
    replace HAS_SLPC() use with intel_slpc_enabled()
	or intel_slpc_active() (Paulo)
v3: Fix for renaming gen9_disable_rps to gen9_disable_rc6 in
    "drm/i915/bxt: Explicitly clear the Turbo control register"

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
---
 drivers/gpu/drm/i915/Makefile     |  5 ++--
 drivers/gpu/drm/i915/intel_drv.h  |  4 +++
 drivers/gpu/drm/i915/intel_guc.h  |  1 +
 drivers/gpu/drm/i915/intel_pm.c   | 37 +++++++++++++++++++-------
 drivers/gpu/drm/i915/intel_slpc.c | 56 +++++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_slpc.h | 35 ++++++++++++++++++++++++
 6 files changed, 126 insertions(+), 12 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_slpc.c
 create mode 100644 drivers/gpu/drm/i915/intel_slpc.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 723c502..0122673 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -43,8 +43,9 @@ i915-y += i915_cmd_parser.o \
 	  intel_uncore.o
 
 # general-purpose microcontroller (GuC) support
-i915-y += intel_guc_loader.o \
-	  i915_guc_submission.o
+i915-y += i915_guc_submission.o \
+	  intel_guc_loader.o \
+	  intel_slpc.o
 
 # autogenerated null render state
 i915-y += intel_renderstate_gen6.o \
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index ce78afe..9d02835 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1591,6 +1591,10 @@ void chv_phy_powergate_lanes(struct intel_encoder *encoder,
 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
 			  enum dpio_channel ch, bool override);
 
+static inline int intel_slpc_active(struct drm_device *dev)
+{
+	return 0;
+}
 
 /* intel_pm.c */
 void intel_init_clock_gating(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index cecfe4e..2d4571e 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -26,6 +26,7 @@
 
 #include "intel_guc_fwif.h"
 #include "i915_guc_reg.h"
+#include "intel_slpc.h"
 
 struct drm_i915_gem_request;
 
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 695a464..35d7f19 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6227,7 +6227,9 @@ void intel_init_gt_powersave(struct drm_device *dev)
 		intel_runtime_pm_get(dev_priv);
 	}
 
-	if (IS_CHERRYVIEW(dev))
+	if (intel_slpc_enabled())
+		intel_slpc_init(dev);
+	else if (IS_CHERRYVIEW(dev))
 		cherryview_init_gt_powersave(dev);
 	else if (IS_VALLEYVIEW(dev))
 		valleyview_init_gt_powersave(dev);
@@ -6237,7 +6239,9 @@ void intel_cleanup_gt_powersave(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
-	if (IS_CHERRYVIEW(dev))
+	if (intel_slpc_active(dev))
+		intel_slpc_cleanup(dev);
+	else if (IS_CHERRYVIEW(dev))
 		return;
 	else if (IS_VALLEYVIEW(dev))
 		valleyview_cleanup_gt_powersave(dev);
@@ -6270,17 +6274,24 @@ void intel_suspend_gt_powersave(struct drm_device *dev)
 	if (INTEL_INFO(dev)->gen < 6)
 		return;
 
-	gen6_suspend_rps(dev);
+	if (intel_slpc_active(dev)) {
+		intel_slpc_suspend(dev);
+	} else {
+		gen6_suspend_rps(dev);
 
-	/* Force GPU to min freq during suspend */
-	gen6_rps_idle(dev_priv);
+		/* Force GPU to min freq during suspend */
+		gen6_rps_idle(dev_priv);
+	}
 }
 
 void intel_disable_gt_powersave(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
-	if (IS_IRONLAKE_M(dev)) {
+	if (intel_slpc_active(dev)) {
+		intel_slpc_disable(dev);
+		gen9_disable_rc6(dev);
+	} else if (IS_IRONLAKE_M(dev)) {
 		ironlake_disable_drps(dev);
 	} else if (INTEL_INFO(dev)->gen >= 6) {
 		intel_suspend_gt_powersave(dev);
@@ -6288,7 +6299,6 @@ void intel_disable_gt_powersave(struct drm_device *dev)
 		mutex_lock(&dev_priv->rps.hw_lock);
 		if (INTEL_INFO(dev)->gen >= 9) {
 			gen9_disable_rc6(dev);
-			gen9_disable_rps(dev);
 		} else if (IS_CHERRYVIEW(dev))
 			cherryview_disable_rps(dev);
 		else if (IS_VALLEYVIEW(dev))
@@ -6352,7 +6362,10 @@ void intel_enable_gt_powersave(struct drm_device *dev)
 	if (intel_vgpu_active(dev))
 		return;
 
-	if (IS_IRONLAKE_M(dev)) {
+	if (intel_slpc_active(dev)) {
+		gen9_enable_rc6(dev);
+		intel_slpc_enable(dev);
+	} else if (IS_IRONLAKE_M(dev)) {
 		ironlake_enable_drps(dev);
 		mutex_lock(&dev->struct_mutex);
 		intel_init_emon(dev);
@@ -6383,8 +6396,12 @@ void intel_reset_gt_powersave(struct drm_device *dev)
 	if (INTEL_INFO(dev)->gen < 6)
 		return;
 
-	gen6_suspend_rps(dev);
-	dev_priv->rps.enabled = false;
+	if (intel_slpc_active(dev)) {
+		intel_slpc_reset(dev);
+	} else {
+		gen6_suspend_rps(dev);
+		dev_priv->rps.enabled = false;
+	}
 }
 
 static void ibx_init_clock_gating(struct drm_device *dev)
diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
new file mode 100644
index 0000000..474fac0
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -0,0 +1,56 @@
+/*
+ * Copyright © 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+#include <linux/firmware.h>
+#include "i915_drv.h"
+#include "intel_guc.h"
+
+void intel_slpc_init(struct drm_device *dev)
+{
+	return;
+}
+
+void intel_slpc_cleanup(struct drm_device *dev)
+{
+	return;
+}
+
+void intel_slpc_suspend(struct drm_device *dev)
+{
+	return;
+}
+
+void intel_slpc_disable(struct drm_device *dev)
+{
+	return;
+}
+
+void intel_slpc_enable(struct drm_device *dev)
+{
+	return;
+}
+
+void intel_slpc_reset(struct drm_device *dev)
+{
+	return;
+}
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
new file mode 100644
index 0000000..6cfadb3
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright © 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+#ifndef _INTEL_SLPC_H_
+#define _INTEL_SLPC_H_
+
+/* intel_slpc.c */
+void intel_slpc_init(struct drm_device *dev);
+void intel_slpc_cleanup(struct drm_device *dev);
+void intel_slpc_suspend(struct drm_device *dev);
+void intel_slpc_disable(struct drm_device *dev);
+void intel_slpc_enable(struct drm_device *dev);
+void intel_slpc_reset(struct drm_device *dev);
+
+#endif
-- 
1.9.1

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[PATCH 06/21] drm/i915/slpc: Enable SLPC in guc if supported

[tom.orourke]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

If slpc enabled, then add enable SLPC flag to guc
control parameter during guc load.

v2: Use intel_slpc_enabled() (Paulo)

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
---
 drivers/gpu/drm/i915/intel_guc_loader.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 174cc34..e9181b1 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -188,6 +188,9 @@ static void set_guc_init_params(struct drm_i915_private *dev_priv)
 	params[GUC_CTL_FEATURE] |= GUC_CTL_DISABLE_SCHEDULER |
 			GUC_CTL_VCS2_ENABLED;
 
+	if (intel_slpc_enabled())
+		params[GUC_CTL_FEATURE] |= GUC_CTL_ENABLE_SLPC;
+
 	if (i915.guc_log_level >= 0) {
 		params[GUC_CTL_LOG_PARAMS] = guc->log_flags;
 		params[GUC_CTL_DEBUG] =
-- 
1.9.1

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[PATCH 07/21] drm/i915/slpc: If using SLPC, do not set frequency

[tom.orourke]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

When frequency requests are made by SLPC, host driver
should not attempt to make frequency requests due to
potential conflicts.

Host-based turbo operations are already avoided when
SLPC is used.  This change covers other frequency
requests such as from sysfs or debugfs interfaces.

A later patch in this series updates sysfs/debugfs
interfaces for setting max/min frequencies with SLPC.

v2: Use intel_slpc_active instead of HAS_SLPC (Paulo)

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 35d7f19..f480551 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4581,6 +4581,9 @@ void gen6_rps_boost(struct drm_i915_private *dev_priv,
 
 void intel_set_rps(struct drm_device *dev, u8 val)
 {
+	if (intel_slpc_active(dev))
+		return;
+
 	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 		valleyview_set_rps(dev, val);
 	else
-- 
1.9.1

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[PATCH 08/21] drm/i915/slpc: Allocate/Release/Initialize SLPC shared data

[tom.orourke]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

SLPC shared data is used to pass information
to/from SLPC firmware.

For Skylake, platform sku type and slice count
are identified from device id and fuse values.

Support for other platforms needs to be added.

v2: Update for SLPC interface version 2015.2.4
    intel_slpc_active() returns 1 if slpc initialized (Paulo)
v3: change default host_os to "Windows"
v4: Spelling fixes (Sagar Kamble and Nick Hoath)

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
---
 drivers/gpu/drm/i915/intel_drv.h  |  8 +++-
 drivers/gpu/drm/i915/intel_guc.h  |  2 +
 drivers/gpu/drm/i915/intel_slpc.c | 84 ++++++++++++++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/intel_slpc.h | 75 ++++++++++++++++++++++++++++++++++
 4 files changed, 166 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 9d02835..47e538a 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1593,7 +1593,13 @@ bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
 
 static inline int intel_slpc_active(struct drm_device *dev)
 {
-	return 0;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	int ret = 0;
+
+	if (dev_priv->guc.slpc.shared_data_obj)
+		ret = 1;
+
+	return ret;
 }
 
 /* intel_pm.c */
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 2d4571e..c55fb5b 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -136,6 +136,8 @@ struct intel_guc {
 
 	uint64_t submissions[GUC_MAX_ENGINES_NUM];
 	uint32_t last_seqno[GUC_MAX_ENGINES_NUM];
+
+	struct intel_slpc slpc;
 };
 
 static inline int intel_slpc_enabled(void)
diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index 474fac0..5e039d5 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -22,17 +22,97 @@
  *
  */
 #include <linux/firmware.h>
+#include <asm/msr-index.h>
 #include "i915_drv.h"
 #include "intel_guc.h"
 
+static u8 slpc_get_platform_sku(struct drm_i915_gem_object *obj)
+{
+	struct drm_device *dev = obj->base.dev;
+	enum slpc_platform_sku platform_sku;
+
+	if (IS_SKL_ULX(dev))
+		platform_sku = SLPC_PLATFORM_SKU_ULX;
+	else if (IS_SKL_ULT(dev))
+		platform_sku = SLPC_PLATFORM_SKU_ULT;
+	else
+		platform_sku = SLPC_PLATFORM_SKU_DT;
+
+	return (u8) platform_sku;
+}
+
+static u8 slpc_get_slice_count(struct drm_i915_gem_object *obj)
+{
+	struct drm_device *dev = obj->base.dev;
+	u8 slice_count = 1;
+
+	if (IS_SKYLAKE(dev))
+		slice_count = INTEL_INFO(dev)->slice_total;
+
+	return slice_count;
+}
+
+static void slpc_shared_data_init(struct drm_i915_gem_object *obj)
+{
+	struct page *page;
+	struct slpc_shared_data *data;
+	u64 msr_value;
+
+	page = i915_gem_object_get_page(obj, 0);
+	if (page) {
+		data = kmap_atomic(page);
+		memset(data, 0, sizeof(struct slpc_shared_data));
+
+		data->slpc_version = SLPC_VERSION;
+		data->shared_data_size = sizeof(struct slpc_shared_data);
+		data->global_state = (u32) SLPC_GLOBAL_STATE_NOT_RUNNING;
+		data->platform_info.platform_sku = slpc_get_platform_sku(obj);
+		data->platform_info.slice_count = slpc_get_slice_count(obj);
+		data->platform_info.host_os = (u8) SLPC_HOST_OS_WINDOWS_8;
+		data->platform_info.power_plan_source =
+			(u8) SLPC_POWER_PLAN_SOURCE(SLPC_POWER_PLAN_BALANCED,
+						    SLPC_POWER_SOURCE_AC);
+		rdmsrl(MSR_TURBO_RATIO_LIMIT, msr_value);
+		data->platform_info.P0_freq = (u8) msr_value;
+		rdmsrl(MSR_PLATFORM_INFO, msr_value);
+		data->platform_info.P1_freq = (u8) (msr_value >> 8);
+		data->platform_info.Pe_freq = (u8) (msr_value >> 40);
+		data->platform_info.Pn_freq = (u8) (msr_value >> 48);
+		rdmsrl(MSR_PKG_POWER_LIMIT, msr_value);
+		data->platform_info.package_rapl_limit_high =
+							(u32) (msr_value >> 32);
+		data->platform_info.package_rapl_limit_low = (u32) msr_value;
+
+		kunmap_atomic(data);
+	}
+}
+
 void intel_slpc_init(struct drm_device *dev)
 {
-	return;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_i915_gem_object *obj;
+
+	/* Allocate shared data structure */
+	obj = dev_priv->guc.slpc.shared_data_obj;
+	if (!obj) {
+		obj = gem_allocate_guc_obj(dev_priv->dev,
+				PAGE_ALIGN(sizeof(struct slpc_shared_data)));
+		dev_priv->guc.slpc.shared_data_obj = obj;
+	}
+
+	if (!obj)
+		DRM_ERROR("slpc_shared_data allocation failed\n");
+	else
+		slpc_shared_data_init(obj);
 }
 
 void intel_slpc_cleanup(struct drm_device *dev)
 {
-	return;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
+	/* Release shared data structure */
+	gem_release_guc_obj(dev_priv->guc.slpc.shared_data_obj);
+	dev_priv->guc.slpc.shared_data_obj = NULL;
 }
 
 void intel_slpc_suspend(struct drm_device *dev)
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index 6cfadb3..9badca9 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -24,6 +24,81 @@
 #ifndef _INTEL_SLPC_H_
 #define _INTEL_SLPC_H_
 
+#define SLPC_MAJOR_VER 2
+#define SLPC_MINOR_VER 4
+#define SLPC_VERSION ((2015 << 16) | (SLPC_MAJOR_VER << 8) | (SLPC_MINOR_VER))
+
+enum slpc_global_state {
+	SLPC_GLOBAL_STATE_NOT_RUNNING = 0,
+	SLPC_GLOBAL_STATE_INITIALIZING = 1,
+	SLPC_GLOBAL_STATE_RESETTING = 2,
+	SLPC_GLOBAL_STATE_RUNNING = 3,
+	SLPC_GLOBAL_STATE_SHUTTING_DOWN = 4,
+	SLPC_GLOBAL_STATE_ERROR = 5
+};
+
+enum slpc_host_os {
+	SLPC_HOST_OS_UNDEFINED = 0,
+	SLPC_HOST_OS_WINDOWS_8 = 1,
+};
+
+enum slpc_platform_sku {
+	SLPC_PLATFORM_SKU_UNDEFINED = 0,
+	SLPC_PLATFORM_SKU_ULX = 1,
+	SLPC_PLATFORM_SKU_ULT = 2,
+	SLPC_PLATFORM_SKU_T = 3,
+	SLPC_PLATFORM_SKU_MOBL = 4,
+	SLPC_PLATFORM_SKU_DT = 5,
+	SLPC_PLATFORM_SKU_UNKNOWN = 6,
+};
+
+enum slpc_power_plan {
+	SLPC_POWER_PLAN_UNDEFINED = 0,
+	SLPC_POWER_PLAN_BATTERY_SAVER = 1,
+	SLPC_POWER_PLAN_BALANCED = 2,
+	SLPC_POWER_PLAN_PERFORMANCE = 3,
+	SLPC_POWER_PLAN_UNKNOWN = 4,
+};
+
+enum slpc_power_source {
+	SLPC_POWER_SOURCE_UNDEFINED = 0,
+	SLPC_POWER_SOURCE_AC = 1,
+	SLPC_POWER_SOURCE_DC = 2,
+	SLPC_POWER_SOURCE_UNKNOWN = 3,
+};
+
+#define SLPC_POWER_PLAN_SOURCE(plan, source) ((plan) | ((source) << 6))
+
+struct slpc_platform_info {
+	u8 platform_sku;
+	u8 slice_count;
+	u8 host_os;
+	u8 power_plan_source;
+	u8 P0_freq;
+	u8 P1_freq;
+	u8 Pe_freq;
+	u8 Pn_freq;
+	u32 package_rapl_limit_high;
+	u32 package_rapl_limit_low;
+} __packed;
+
+#define SLPC_MAX_OVERRIDE_PARAMETERS 192
+#define SLPC_OVERRIDE_BITFIELD_SIZE ((SLPC_MAX_OVERRIDE_PARAMETERS + 31) / 32)
+
+struct slpc_shared_data {
+	u32 slpc_version;
+	u32 shared_data_size;
+	u32 global_state;
+	struct slpc_platform_info platform_info;
+	u32 task_state_data;
+	u32 override_parameters_set_bits[SLPC_OVERRIDE_BITFIELD_SIZE];
+	u32 override_parameters_values[SLPC_MAX_OVERRIDE_PARAMETERS];
+} __packed;
+
+struct intel_slpc {
+	struct drm_i915_gem_object *shared_data_obj;
+};
+
 /* intel_slpc.c */
 void intel_slpc_init(struct drm_device *dev);
 void intel_slpc_cleanup(struct drm_device *dev);
-- 
1.9.1

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[PATCH 09/21] drm/i915/slpc: Setup rps frequency values during SLPC init

[tom.orourke]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

v2: Add mutex lock/unlock

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
---
 drivers/gpu/drm/i915/intel_drv.h  | 1 +
 drivers/gpu/drm/i915/intel_pm.c   | 2 +-
 drivers/gpu/drm/i915/intel_slpc.c | 5 +++++
 3 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 47e538a..006a8c7 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1612,6 +1612,7 @@ void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
 void intel_pm_setup(struct drm_device *dev);
 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
 void intel_gpu_ips_teardown(void);
+void gen6_init_rps_frequencies(struct drm_device *dev);
 void intel_init_gt_powersave(struct drm_device *dev);
 void intel_cleanup_gt_powersave(struct drm_device *dev);
 void intel_enable_gt_powersave(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index f480551..b4f753e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4738,7 +4738,7 @@ int intel_enable_rc6(const struct drm_device *dev)
 	return i915.enable_rc6;
 }
 
-static void gen6_init_rps_frequencies(struct drm_device *dev)
+void gen6_init_rps_frequencies(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	uint32_t rp_state_cap;
diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index 5e039d5..bacbfed 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -92,6 +92,11 @@ void intel_slpc_init(struct drm_device *dev)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct drm_i915_gem_object *obj;
 
+	/* Initialize the rps frequecny values */
+	mutex_lock(&dev_priv->rps.hw_lock);
+	gen6_init_rps_frequencies(dev);
+	mutex_unlock(&dev_priv->rps.hw_lock);
+
 	/* Allocate shared data structure */
 	obj = dev_priv->guc.slpc.shared_data_obj;
 	if (!obj) {
-- 
1.9.1

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[PATCH 10/21] drm/i915/slpc: Update current requested frequency

[tom.orourke]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

When SLPC is controlling requested frequency, the rps.cur_freq
value is not used to make the frequency request.

Before using rps.cur_freq in sysfs or debugfs, read
requested frequency from register to get the value
most recently requested by SLPC firmware.

v2: replace HAS_SLPC with intel_slpc_active (Paulo)
v3: Avoid magic numbers (Nick)
    Use a function for repeated code (Jon)

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 6 ++++++
 drivers/gpu/drm/i915/i915_drv.h     | 5 +++++
 drivers/gpu/drm/i915/i915_reg.h     | 1 +
 drivers/gpu/drm/i915/i915_sysfs.c   | 3 +++
 4 files changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 8b8d6f0..1295d8b 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1168,6 +1168,9 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
 
 	flush_delayed_work(&dev_priv->rps.delayed_resume_work);
 
+	if (intel_slpc_active(dev))
+		dev_priv->rps.cur_freq = gen9_read_requested_freq(dev_priv);
+
 	if (IS_GEN5(dev)) {
 		u16 rgvswctl = I915_READ16(MEMSWCTL);
 		u16 rgvstat = I915_READ16(MEMSTAT_ILK);
@@ -2399,6 +2402,9 @@ static int i915_rps_boost_info(struct seq_file *m, void *data)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct drm_file *file;
 
+	if (intel_slpc_active(dev))
+		dev_priv->rps.cur_freq = gen9_read_requested_freq(dev_priv);
+
 	seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
 	seq_printf(m, "GPU busy? %d\n", dev_priv->mm.busy);
 	seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 393da67..55d31f1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3728,4 +3728,9 @@ static inline void i915_trace_irq_get(struct intel_engine_cs *engine,
 		i915_gem_request_assign(&engine->trace_irq_req, req);
 }
 
+static inline u8 gen9_read_requested_freq(struct drm_i915_private *dev_priv)
+{
+	return (u8) GEN9_GET_FREQUENCY(I915_READ(GEN6_RPNSWREQ));
+}
+
 #endif
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0a2fd30..a7beb10 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6956,6 +6956,7 @@ enum skl_disp_power_wells {
 #define   GEN6_FREQUENCY(x)			((x)<<25)
 #define   HSW_FREQUENCY(x)			((x)<<24)
 #define   GEN9_FREQUENCY(x)			((x)<<23)
+#define   GEN9_GET_FREQUENCY(x)			((x)>>23)
 #define   GEN6_OFFSET(x)			((x)<<19)
 #define   GEN6_AGGRESSIVE_TURBO			(0<<15)
 #define GEN6_RC_VIDEO_FREQ			_MMIO(0xA00C)
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index 2d576b7..826e40c 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -318,6 +318,9 @@ static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
 	intel_runtime_pm_get(dev_priv);
 
 	mutex_lock(&dev_priv->rps.hw_lock);
+	if (intel_slpc_active(dev))
+		dev_priv->rps.cur_freq = gen9_read_requested_freq(dev_priv);
+
 	ret = intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq);
 	mutex_unlock(&dev_priv->rps.hw_lock);
 
-- 
1.9.1

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[PATCH 11/21] drm/i915/slpc: Send reset event

[tom.orourke]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

Add host2guc SLPC reset event and send reset event
during enable.

v2: extract host2guc_slpc to handle slpc status code
    coding style changes (Paulo)

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
---
 drivers/gpu/drm/i915/intel_slpc.c | 33 ++++++++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/intel_slpc.h | 14 ++++++++++++++
 2 files changed, 46 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index bacbfed..3fd46ac 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -26,6 +26,36 @@
 #include "i915_drv.h"
 #include "intel_guc.h"
 
+static void host2guc_slpc(struct drm_i915_private *dev_priv, u32 *data, u32 len)
+{
+	int ret = host2guc_action(&dev_priv->guc, data, len);
+
+	if (!ret) {
+		ret = I915_READ(SOFT_SCRATCH(1));
+		ret &= SLPC_EVENT_STATUS_MASK;
+	}
+
+	if (ret)
+		DRM_ERROR("event 0x%x status %d\n", (data[1] >> 8), ret);
+}
+
+static void host2guc_slpc_reset(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_i915_gem_object *obj = dev_priv->guc.slpc.shared_data_obj;
+	u32 data[4];
+	u64 shared_data_gtt_offset = i915_gem_obj_ggtt_offset(obj);
+
+	data[0] = HOST2GUC_ACTION_SLPC_REQUEST;
+	data[1] = SLPC_EVENT(SLPC_EVENT_RESET, 2);
+	data[2] = lower_32_bits(shared_data_gtt_offset);
+	data[3] = upper_32_bits(shared_data_gtt_offset);
+
+	WARN_ON(data[3] != 0);
+
+	host2guc_slpc(dev_priv, data, 4);
+}
+
 static u8 slpc_get_platform_sku(struct drm_i915_gem_object *obj)
 {
 	struct drm_device *dev = obj->base.dev;
@@ -132,7 +162,8 @@ void intel_slpc_disable(struct drm_device *dev)
 
 void intel_slpc_enable(struct drm_device *dev)
 {
-	return;
+	if (intel_slpc_active(dev))
+		host2guc_slpc_reset(dev);
 }
 
 void intel_slpc_reset(struct drm_device *dev)
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index 9badca9..0a9c0f2 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -28,6 +28,20 @@
 #define SLPC_MINOR_VER 4
 #define SLPC_VERSION ((2015 << 16) | (SLPC_MAJOR_VER << 8) | (SLPC_MINOR_VER))
 
+enum slpc_event_id {
+	SLPC_EVENT_RESET = 0,
+	SLPC_EVENT_SHUTDOWN = 1,
+	SLPC_EVENT_PLATFORM_INFO_CHANGE = 2,
+	SLPC_EVENT_DISPLAY_MODE_CHANGE = 3,
+	SLPC_EVENT_FLIP_COMPLETE = 4,
+	SLPC_EVENT_QUERY_TASK_STATE = 5,
+	SLPC_EVENT_PARAMETER_SET = 6,
+	SLPC_EVENT_PARAMETER_UNSET = 7,
+};
+
+#define SLPC_EVENT(id, argc) ((u32) (id) << 8 | (argc))
+#define SLPC_EVENT_STATUS_MASK	0xFF
+
 enum slpc_global_state {
 	SLPC_GLOBAL_STATE_NOT_RUNNING = 0,
 	SLPC_GLOBAL_STATE_INITIALIZING = 1,
-- 
1.9.1

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[PATCH 12/21] drm/i915/slpc: Send shutdown event

[tom.orourke]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

Send SLPC shutdown event during disable, suspend, and reset
operations.  Sending shutdown event while already shutdown
is OK.

v2: return void instead of ignored error code (Paulo)

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
---
 drivers/gpu/drm/i915/intel_slpc.c | 28 +++++++++++++++++++++++++---
 1 file changed, 25 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index 3fd46ac..076d07b 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -56,6 +56,23 @@ static void host2guc_slpc_reset(struct drm_device *dev)
 	host2guc_slpc(dev_priv, data, 4);
 }
 
+static void host2guc_slpc_shutdown(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_i915_gem_object *obj = dev_priv->guc.slpc.shared_data_obj;
+	u32 data[4];
+	u64 shared_data_gtt_offset = i915_gem_obj_ggtt_offset(obj);
+
+	data[0] = HOST2GUC_ACTION_SLPC_REQUEST;
+	data[1] = SLPC_EVENT(SLPC_EVENT_SHUTDOWN, 2);
+	data[2] = lower_32_bits(shared_data_gtt_offset);
+	data[3] = upper_32_bits(shared_data_gtt_offset);
+
+	WARN_ON(0 != data[3]);
+
+	host2guc_slpc(dev_priv, data, 4);
+}
+
 static u8 slpc_get_platform_sku(struct drm_i915_gem_object *obj)
 {
 	struct drm_device *dev = obj->base.dev;
@@ -152,12 +169,14 @@ void intel_slpc_cleanup(struct drm_device *dev)
 
 void intel_slpc_suspend(struct drm_device *dev)
 {
-	return;
+	if (intel_slpc_active(dev))
+		host2guc_slpc_shutdown(dev);
 }
 
 void intel_slpc_disable(struct drm_device *dev)
 {
-	return;
+	if (intel_slpc_active(dev))
+		host2guc_slpc_shutdown(dev);
 }
 
 void intel_slpc_enable(struct drm_device *dev)
@@ -168,5 +187,8 @@ void intel_slpc_enable(struct drm_device *dev)
 
 void intel_slpc_reset(struct drm_device *dev)
 {
-	return;
+	if (intel_slpc_active(dev)) {
+		host2guc_slpc_shutdown(dev);
+		host2guc_slpc_reset(dev);
+	}
 }
-- 
1.9.1

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[PATCH 13/21] drm/i915/slpc: Add Display mode event related data structures

[tom.orourke]

From: Sagar Arun Kamble <sagar.a.kamble@intel.com>

v2: Cleaning up defines for number of pipes and other cosmetic changes.

v3: Checkpatch fixes.

Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Acked-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
---
 drivers/gpu/drm/i915/intel_slpc.h | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index 0a9c0f2..b342fa2 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -109,8 +109,38 @@ struct slpc_shared_data {
 	u32 override_parameters_values[SLPC_MAX_OVERRIDE_PARAMETERS];
 } __packed;
 
+#define SLPC_MAX_NUM_OF_PIPES 4
+
+struct intel_display_pipe_info {
+	union {
+		u32 data;
+		struct {
+			u32 is_widi:1;
+			u32 refresh_rate:7;
+			u32 vsync_ft_usec:24;
+		};
+	};
+} __packed;
+
+struct intel_slpc_display_mode_event_params {
+	struct {
+		struct intel_display_pipe_info
+					per_pipe_info[SLPC_MAX_NUM_OF_PIPES];
+		union {
+			u32 global_data;
+			struct {
+				u32 active_pipes_bitmask:SLPC_MAX_NUM_OF_PIPES;
+				u32 fullscreen_pipes:SLPC_MAX_NUM_OF_PIPES;
+				u32 vbi_sync_on_pipes:SLPC_MAX_NUM_OF_PIPES;
+				u32 num_active_pipes:2;
+			};
+		};
+	};
+} __packed;
+
 struct intel_slpc {
 	struct drm_i915_gem_object *shared_data_obj;
+	struct intel_slpc_display_mode_event_params display_mode_params;
 };
 
 /* intel_slpc.c */
-- 
1.9.1

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[PATCH 14/21] drm/i915/slpc: Notification of Display mode change

[tom.orourke]

From: Sagar Arun Kamble <sagar.a.kamble@intel.com>

GuC SLPC needs to be sent data related to Active pipes, refresh rates,
widi pipes, fullscreen pipes related via host to GuC display mode
change event. Based on this, SLPC will track FPS on active pipes.
This patch defines the events and implements trigger of the events.

v2: Addressed review comments from Paulo and Ville. Changed the way
display mode information is collected in intel_atomic_commit. Coupled
display mode change event with SLPC enable/reset event. Updated inactive
crtc state in display mode data. Updated refresh rate and vsync_ft_usec
calculations to get more accurate value. (Paulo)
v2(torourke): Updates suggested by Paulo: replace HAS_SLPC with
intel_slpc_active. Return void instead of ignored error code.

v3: Addressed checkpatch issues. (Sagar)
Commit message update and bitmask op changes in display mode events.
(Nick)
Added check for mode parameters clock, htotal, vtotal. (Jon)

Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |   2 +
 drivers/gpu/drm/i915/intel_slpc.c    | 174 ++++++++++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/intel_slpc.h    |   3 +
 3 files changed, 178 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index eb7cb94..3bc61b7 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13716,6 +13716,8 @@ static int intel_atomic_commit(struct drm_device *dev,
 	drm_atomic_helper_cleanup_planes(dev, state);
 	mutex_unlock(&dev->struct_mutex);
 
+	intel_slpc_update_atomic_commit_info(dev, state);
+
 	drm_atomic_state_free(state);
 
 	/* As one of the primary mmio accessors, KMS has a high likelihood
diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index 076d07b..7f26284 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -73,6 +73,24 @@ static void host2guc_slpc_shutdown(struct drm_device *dev)
 	host2guc_slpc(dev_priv, data, 4);
 }
 
+static void host2guc_slpc_display_mode_change(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	u32 data[3 + SLPC_MAX_NUM_OF_PIPES];
+	int i;
+	struct intel_slpc_display_mode_event_params *display_mode_params;
+
+	display_mode_params = &dev_priv->guc.slpc.display_mode_params;
+	data[0] = HOST2GUC_ACTION_SLPC_REQUEST;
+	data[1] = SLPC_EVENT(SLPC_EVENT_DISPLAY_MODE_CHANGE,
+					SLPC_MAX_NUM_OF_PIPES + 1);
+	data[2] = display_mode_params->global_data;
+	for(i = 0; i < SLPC_MAX_NUM_OF_PIPES; ++i)
+		data[3+i] = display_mode_params->per_pipe_info[i].data;
+
+	host2guc_slpc(dev_priv, data, 3 + SLPC_MAX_NUM_OF_PIPES);
+}
+
 static u8 slpc_get_platform_sku(struct drm_i915_gem_object *obj)
 {
 	struct drm_device *dev = obj->base.dev;
@@ -181,8 +199,10 @@ void intel_slpc_disable(struct drm_device *dev)
 
 void intel_slpc_enable(struct drm_device *dev)
 {
-	if (intel_slpc_active(dev))
+	if (intel_slpc_active(dev)) {
 		host2guc_slpc_reset(dev);
+		intel_slpc_update_display_mode_info(dev);
+	}
 }
 
 void intel_slpc_reset(struct drm_device *dev)
@@ -192,3 +212,155 @@ void intel_slpc_reset(struct drm_device *dev)
 		host2guc_slpc_reset(dev);
 	}
 }
+
+void intel_slpc_update_display_mode_info(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_crtc *intel_crtc;
+	struct intel_display_pipe_info *per_pipe_info;
+	struct intel_slpc_display_mode_event_params *cur_params, old_params;
+	bool notify = false;
+
+	if (!intel_slpc_active(dev))
+		return;
+
+	/* Copy display mode parameters for comparison */
+	cur_params = &dev_priv->guc.slpc.display_mode_params;
+	old_params.global_data  = cur_params->global_data;
+	cur_params->global_data = 0;
+
+	intel_runtime_pm_get(dev_priv);
+	drm_modeset_lock_all(dev);
+
+	for_each_intel_crtc(dev, intel_crtc) {
+		per_pipe_info = &cur_params->per_pipe_info[intel_crtc->pipe];
+		old_params.per_pipe_info[intel_crtc->pipe].data =
+							per_pipe_info->data;
+		per_pipe_info->data = 0;
+
+		if (intel_crtc->active) {
+			struct drm_display_mode *mode = &intel_crtc->base.mode;
+
+			if (mode->clock == 0 || mode->htotal == 0 ||
+			    mode->vtotal == 0) {
+				DRM_DEBUG_DRIVER(
+					"Display Mode Info not sent to SLPC\n");
+				drm_modeset_unlock_all(dev);
+				intel_runtime_pm_put(dev_priv);
+				return;
+			}
+			/* FIXME: Update is_widi based on encoder */
+			per_pipe_info->is_widi = 0;
+			per_pipe_info->refresh_rate =
+						(mode->clock * 1000) /
+						(mode->htotal * mode->vtotal);
+			per_pipe_info->vsync_ft_usec =
+					(mode->htotal * mode->vtotal * 1000) /
+						mode->clock;
+			cur_params->active_pipes_bitmask |=
+							(1 << intel_crtc->pipe);
+			cur_params->vbi_sync_on_pipes |=
+							(1 << intel_crtc->pipe);
+		} else {
+			cur_params->active_pipes_bitmask &=
+						~(1 << intel_crtc->pipe);
+			cur_params->vbi_sync_on_pipes &=
+						~(1 << intel_crtc->pipe);
+		}
+
+		if (old_params.per_pipe_info[intel_crtc->pipe].data !=
+							per_pipe_info->data)
+			notify = true;
+	}
+
+	drm_modeset_unlock_all(dev);
+
+	cur_params->num_active_pipes =
+				hweight32(cur_params->active_pipes_bitmask);
+
+	/*
+	 * Compare old display mode with current mode.
+	 * Notify SLPC if it is changed.
+	*/
+	if (cur_params->global_data != old_params.global_data)
+		notify = true;
+
+	if (notify)
+		host2guc_slpc_display_mode_change(dev);
+
+	intel_runtime_pm_put(dev_priv);
+}
+
+void intel_slpc_update_atomic_commit_info(struct drm_device *dev,
+					  struct drm_atomic_state *state)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_crtc *crtc;
+	struct drm_crtc_state *crtc_state;
+	struct intel_display_pipe_info *per_pipe_info;
+	struct intel_slpc_display_mode_event_params *cur_params, old_params;
+	bool notify = false;
+	int i;
+
+	if (!intel_slpc_active(dev))
+		return;
+
+	/* Copy display mode parameters for comparison */
+	cur_params = &dev_priv->guc.slpc.display_mode_params;
+	old_params.global_data  = cur_params->global_data;
+
+	for_each_crtc_in_state(state, crtc, crtc_state, i) {
+		struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+
+		per_pipe_info = &cur_params->per_pipe_info[intel_crtc->pipe];
+		old_params.per_pipe_info[intel_crtc->pipe].data =
+							per_pipe_info->data;
+
+		per_pipe_info->data = 0;
+		cur_params->active_pipes_bitmask &=
+						~(1 << intel_crtc->pipe);
+		cur_params->vbi_sync_on_pipes &=
+						~(1 << intel_crtc->pipe);
+
+		if (crtc_state->active) {
+			struct drm_display_mode *mode = &crtc->mode;
+
+			if (mode->clock == 0 || mode->htotal == 0 ||
+			    mode->vtotal == 0) {
+				DRM_DEBUG_DRIVER(
+					"Display Mode Info not sent to SLPC\n");
+				return;
+			}
+
+			/* FIXME: Update is_widi based on encoder */
+			per_pipe_info->is_widi = 0;
+			per_pipe_info->refresh_rate =
+						(mode->clock * 1000) /
+						(mode->htotal * mode->vtotal);
+			per_pipe_info->vsync_ft_usec =
+					(mode->htotal * mode->vtotal * 1000) /
+						mode->clock;
+			cur_params->active_pipes_bitmask |=
+							(1 << intel_crtc->pipe);
+			cur_params->vbi_sync_on_pipes |=
+							(1 << intel_crtc->pipe);
+		}
+
+		if (old_params.per_pipe_info[intel_crtc->pipe].data !=
+							per_pipe_info->data)
+			notify = true;
+	}
+
+	cur_params->num_active_pipes =
+				hweight32(cur_params->active_pipes_bitmask);
+
+	/*
+	 * Compare old display mode with current mode.
+	 * Notify SLPC if it is changed.
+	*/
+	if (cur_params->global_data != old_params.global_data)
+		notify = true;
+
+	if (notify)
+		host2guc_slpc_display_mode_change(dev);
+}
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index b342fa2..39b4657 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -150,5 +150,8 @@ void intel_slpc_suspend(struct drm_device *dev);
 void intel_slpc_disable(struct drm_device *dev);
 void intel_slpc_enable(struct drm_device *dev);
 void intel_slpc_reset(struct drm_device *dev);
+void intel_slpc_update_display_mode_info(struct drm_device *dev);
+void intel_slpc_update_atomic_commit_info(struct drm_device *dev,
+					  struct drm_atomic_state *state);
 
 #endif
-- 
1.9.1

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[PATCH 15/21] drm/i915/slpc: Notification of Refresh Rate change

[tom.orourke]

From: Sagar Arun Kamble <sagar.a.kamble@intel.com>

This patch will inform GuC SLPC about changes in the refresh rate
due to Seamless DRRS. Refresh rate changes due to Static DRRS will
be notified via commit path.

v2: Rebased on previous changed patch and printed error message if
H2G action fails.
v2(torourke): Updates suggested by Paulo: replace HAS_SLPC with
intel_slpc_active. return void instead of ignored error code.

Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c   |  2 ++
 drivers/gpu/drm/i915/intel_slpc.c | 23 +++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_slpc.h |  1 +
 3 files changed, 26 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index c12c414..3d41f7b 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -5379,6 +5379,8 @@ static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
 	dev_priv->drrs.refresh_rate_type = index;
 
 	DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
+
+	intel_slpc_update_display_rr_info(dev, refresh_rate);
 }
 
 /**
diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index 7f26284..9e0bc96 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -364,3 +364,26 @@ void intel_slpc_update_atomic_commit_info(struct drm_device *dev,
 	if (notify)
 		host2guc_slpc_display_mode_change(dev);
 }
+
+void intel_slpc_update_display_rr_info(struct drm_device *dev, u32 refresh_rate)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_crtc *crtc;
+	struct intel_display_pipe_info *per_pipe_info;
+	struct intel_slpc_display_mode_event_params *display_params;
+
+	if (!intel_slpc_active(dev))
+		return;
+
+	if (!refresh_rate)
+		return;
+
+	display_params = &dev_priv->guc.slpc.display_mode_params;
+	crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
+
+	per_pipe_info = &display_params->per_pipe_info[to_intel_crtc(crtc)->pipe];
+	per_pipe_info->refresh_rate = refresh_rate;
+	per_pipe_info->vsync_ft_usec = 1000000 / refresh_rate;
+
+	host2guc_slpc_display_mode_change(dev);
+}
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index 39b4657..0b251a1 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -153,5 +153,6 @@ void intel_slpc_reset(struct drm_device *dev);
 void intel_slpc_update_display_mode_info(struct drm_device *dev);
 void intel_slpc_update_atomic_commit_info(struct drm_device *dev,
 					  struct drm_atomic_state *state);
+void intel_slpc_update_display_rr_info(struct drm_device *dev, u32 refresh_rate);
 
 #endif
-- 
1.9.1

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[PATCH 16/21] drm/i915/slpc: Add slpc_status enum values

[tom.orourke]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

v2: fix whitespace (Sagar)

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
---
 drivers/gpu/drm/i915/intel_slpc.h | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index 0b251a1..508642b 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -28,6 +28,33 @@
 #define SLPC_MINOR_VER 4
 #define SLPC_VERSION ((2015 << 16) | (SLPC_MAJOR_VER << 8) | (SLPC_MINOR_VER))
 
+enum slpc_status {
+	SLPC_STATUS_OK = 0,
+	SLPC_STATUS_ERROR = 1,
+	SLPC_STATUS_ILLEGAL_COMMAND = 2,
+	SLPC_STATUS_INVALID_ARGS = 3,
+	SLPC_STATUS_INVALID_PARAMS = 4,
+	SLPC_STATUS_INVALID_DATA = 5,
+	SLPC_STATUS_OUT_OF_RANGE = 6,
+	SLPC_STATUS_NOT_SUPPORTED = 7,
+	SLPC_STATUS_NOT_IMPLEMENTED = 8,
+	SLPC_STATUS_NO_DATA = 9,
+	SLPC_STATUS_EVENT_NOT_REGISTERED = 10,
+	SLPC_STATUS_REGISTER_LOCKED = 11,
+	SLPC_STATUS_TEMPORARILY_UNAVAILABLE = 12,
+	SLPC_STATUS_VALUE_ALREADY_SET = 13,
+	SLPC_STATUS_VALUE_ALREADY_UNSET = 14,
+	SLPC_STATUS_VALUE_NOT_CHANGED = 15,
+	SLPC_STATUS_MISMATCHING_VERSION = 16,
+	SLPC_STATUS_MEMIO_ERROR = 17,
+	SLPC_STATUS_EVENT_QUEUED_REQ_DPC = 18,
+	SLPC_STATUS_EVENT_QUEUED_NOREQ_DPC = 19,
+	SLPC_STATUS_NO_EVENT_QUEUED = 20,
+	SLPC_STATUS_OUT_OF_SPACE = 21,
+	SLPC_STATUS_TIMEOUT = 22,
+	SLPC_STATUS_NO_LOCK = 23,
+};
+
 enum slpc_event_id {
 	SLPC_EVENT_RESET = 0,
 	SLPC_EVENT_SHUTDOWN = 1,
-- 
1.9.1

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[PATCH 17/21] drm/i915/slpc: Add parameter unset/set/get functions

[tom.orourke]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

Add slpc_param_id enum values.
Add events for setting/unsetting parameters.

v2: use host2guc_slpc
    update slcp_param_id enum values for SLPC 2015.2.4
    return void instead of ignored error code (Paulo)

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
---
 drivers/gpu/drm/i915/intel_slpc.c | 104 ++++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_slpc.h |  26 +++++++++-
 2 files changed, 129 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index 9e0bc96..7b14a45 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -91,6 +91,33 @@ static void host2guc_slpc_display_mode_change(struct drm_device *dev)
 	host2guc_slpc(dev_priv, data, 3 + SLPC_MAX_NUM_OF_PIPES);
 }
 
+static void host2guc_slpc_set_param(struct drm_device *dev,
+				    enum slpc_param_id id, u32 value)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	u32 data[4];
+
+	data[0] = HOST2GUC_ACTION_SLPC_REQUEST;
+	data[1] = SLPC_EVENT(SLPC_EVENT_PARAMETER_SET, 2);
+	data[2] = (u32) id;
+	data[3] = value;
+
+	host2guc_slpc(dev_priv, data, 4);
+}
+
+static void host2guc_slpc_unset_param(struct drm_device *dev,
+				      enum slpc_param_id id)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	u32 data[3];
+
+	data[0] = HOST2GUC_ACTION_SLPC_REQUEST;
+	data[1] = SLPC_EVENT(SLPC_EVENT_PARAMETER_UNSET, 1);
+	data[2] = (u32) id;
+
+	host2guc_slpc(dev_priv, data, 3);
+}
+
 static u8 slpc_get_platform_sku(struct drm_i915_gem_object *obj)
 {
 	struct drm_device *dev = obj->base.dev;
@@ -387,3 +414,80 @@ void intel_slpc_update_display_rr_info(struct drm_device *dev, u32 refresh_rate)
 
 	host2guc_slpc_display_mode_change(dev);
 }
+
+void intel_slpc_unset_param(struct drm_device *dev, enum slpc_param_id id)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_i915_gem_object *obj;
+	struct page *page;
+	struct slpc_shared_data *data = NULL;
+
+	obj = dev_priv->guc.slpc.shared_data_obj;
+	if (obj) {
+		page = i915_gem_object_get_page(obj, 0);
+		if (page)
+			data = kmap_atomic(page);
+	}
+
+	if (data) {
+		data->override_parameters_set_bits[id >> 5]
+							&= (~(1 << (id % 32)));
+		data->override_parameters_values[id] = 0;
+		kunmap_atomic(data);
+
+		host2guc_slpc_unset_param(dev, id);
+	}
+}
+
+void intel_slpc_set_param(struct drm_device *dev, enum slpc_param_id id,
+			  u32 value)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_i915_gem_object *obj;
+	struct page *page;
+	struct slpc_shared_data *data = NULL;
+
+	obj = dev_priv->guc.slpc.shared_data_obj;
+	if (obj) {
+		page = i915_gem_object_get_page(obj, 0);
+		if (page)
+			data = kmap_atomic(page);
+	}
+
+	if (data) {
+		data->override_parameters_set_bits[id >> 5]
+							|= (1 << (id % 32));
+		data->override_parameters_values[id] = value;
+		kunmap_atomic(data);
+
+		host2guc_slpc_set_param(dev, id, value);
+	}
+}
+
+void intel_slpc_get_param(struct drm_device *dev, enum slpc_param_id id,
+			  int *overriding, u32 *value)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_i915_gem_object *obj;
+	struct page *page;
+	struct slpc_shared_data *data = NULL;
+	u32 bits;
+
+	obj = dev_priv->guc.slpc.shared_data_obj;
+	if (obj) {
+		page = i915_gem_object_get_page(obj, 0);
+		if (page)
+			data = kmap_atomic(page);
+	}
+
+	if (data) {
+		if (overriding) {
+			bits = data->override_parameters_set_bits[id >> 5];
+			*overriding = (0 != (bits & (1 << (id % 32))));
+		}
+		if (value)
+			*value = data->override_parameters_values[id];
+
+		kunmap_atomic(data);
+	}
+}
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index 508642b..bf09f1b 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -69,6 +69,26 @@ enum slpc_event_id {
 #define SLPC_EVENT(id, argc) ((u32) (id) << 8 | (argc))
 #define SLPC_EVENT_STATUS_MASK	0xFF
 
+enum slpc_param_id {
+	SLPC_PARAM_TASK_ENABLE_GTPERF = 0,
+	SLPC_PARAM_TASK_DISABLE_GTPERF = 1,
+	SLPC_PARAM_TASK_ENABLE_BALANCER = 2,
+	SLPC_PARAM_TASK_DISABLE_BALANCER = 3,
+	SLPC_PARAM_TASK_ENABLE_DCC = 4,
+	SLPC_PARAM_TASK_DISABLE_DCC = 5,
+	SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ = 6,
+	SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ = 7,
+	SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ = 8,
+	SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ = 9,
+	SLPC_PARAM_DFPS_THRESHOLD_MAX_FPS = 10,
+	SLPC_PARAM_GLOBAL_DISABLE_GT_FREQ_MANAGEMENT = 11,
+	SLPC_PARAM_DFPS_DISABLE_FRAMERATE_STALLING = 12,
+	SLPC_PARAM_GLOBAL_DISABLE_RC6_MODE_CHANGE = 13,
+	SLPC_PARAM_GLOBAL_OC_UNSLICE_FREQ_MHZ = 14,
+	SLPC_PARAM_GLOBAL_OC_SLICE_FREQ_MHZ = 15,
+	SLPC_PARAM_GLOBAL_DISABE_IA_GT_BALANCING = 16,
+};
+
 enum slpc_global_state {
 	SLPC_GLOBAL_STATE_NOT_RUNNING = 0,
 	SLPC_GLOBAL_STATE_INITIALIZING = 1,
@@ -181,5 +201,9 @@ void intel_slpc_update_display_mode_info(struct drm_device *dev);
 void intel_slpc_update_atomic_commit_info(struct drm_device *dev,
 					  struct drm_atomic_state *state);
 void intel_slpc_update_display_rr_info(struct drm_device *dev, u32 refresh_rate);
-
+void intel_slpc_unset_param(struct drm_device *dev, enum slpc_param_id id);
+void intel_slpc_set_param(struct drm_device *dev, enum slpc_param_id id,
+			  u32 value);
+void intel_slpc_get_param(struct drm_device *dev, enum slpc_param_id id,
+			  int *overriding, u32 *value);
 #endif
-- 
1.9.1

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[PATCH 18/21] drm/i915/slpc: Add slpc support for max/min freq

[tom.orourke]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

Update sysfs and debugfs functions to set SLPC
parameters when setting max/min frequency.

v2: Update for SLPC 2015.2.4 (params for both slice and unslice)
    Replace HAS_SLPC with intel_slpc_active() (Paulo)

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 16 ++++++++++++++++
 drivers/gpu/drm/i915/i915_sysfs.c   | 18 ++++++++++++++++++
 2 files changed, 34 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 1295d8b..f77d32c 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -5014,6 +5014,14 @@ i915_max_freq_set(void *data, u64 val)
 	}
 
 	dev_priv->rps.max_freq_softlimit = val;
+	if (intel_slpc_active(dev)) {
+		intel_slpc_set_param(dev,
+				     SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ,
+				     (u32) intel_gpu_freq(dev_priv, val));
+		intel_slpc_set_param(dev,
+				     SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ,
+				     (u32) intel_gpu_freq(dev_priv, val));
+	}
 
 	intel_set_rps(dev, val);
 
@@ -5081,6 +5089,14 @@ i915_min_freq_set(void *data, u64 val)
 	}
 
 	dev_priv->rps.min_freq_softlimit = val;
+	if (intel_slpc_active(dev)) {
+		intel_slpc_set_param(dev,
+				     SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
+				     (u32) intel_gpu_freq(dev_priv, val));
+		intel_slpc_set_param(dev,
+				     SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ,
+				     (u32) intel_gpu_freq(dev_priv, val));
+	}
 
 	intel_set_rps(dev, val);
 
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index 826e40c..091a936 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -393,6 +393,15 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev,
 
 	dev_priv->rps.max_freq_softlimit = val;
 
+	if (intel_slpc_active(dev)) {
+		intel_slpc_set_param(dev,
+				     SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ,
+				     (u32) intel_gpu_freq(dev_priv, val));
+		intel_slpc_set_param(dev,
+				     SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ,
+				     (u32) intel_gpu_freq(dev_priv, val));
+	}
+
 	val = clamp_t(int, dev_priv->rps.cur_freq,
 		      dev_priv->rps.min_freq_softlimit,
 		      dev_priv->rps.max_freq_softlimit);
@@ -457,6 +466,15 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev,
 
 	dev_priv->rps.min_freq_softlimit = val;
 
+	if (intel_slpc_active(dev)) {
+		intel_slpc_set_param(dev,
+				     SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
+				     (u32) intel_gpu_freq(dev_priv, val));
+		intel_slpc_set_param(dev,
+				     SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ,
+				     (u32) intel_gpu_freq(dev_priv, val));
+	}
+
 	val = clamp_t(int, dev_priv->rps.cur_freq,
 		      dev_priv->rps.min_freq_softlimit,
 		      dev_priv->rps.max_freq_softlimit);
-- 
1.9.1

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[PATCH 19/21] drm/i915/slpc: Add enable/disable debugfs for slpc

[tom.orourke]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

Adds debugfs hooks for each slpc task.

The enable/disable debugfs files are
i915_slpc_gtperf, i915_slpc_balancer, and i915_slpc_dcc.

Each of these can take the values:
"default", "enabled", or "disabled"

v2: update for SLPC v2015.2.4
    dfps and turbo merged and renamed "gtperf"
    ibc split out and renamed "balancer"
v3: Avoid magic numbers (Jon Bloomfield)

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 250 ++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_slpc.h   |   5 +
 2 files changed, 255 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index f77d32c..8b39a13 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1157,6 +1157,253 @@ DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
 			i915_next_seqno_get, i915_next_seqno_set,
 			"0x%llx\n");
 
+static int slpc_enable_disable_get(struct drm_device *dev, u64 *val,
+				   enum slpc_param_id enable_id,
+				   enum slpc_param_id disable_id)
+{
+	int override_enable, override_disable;
+	u32 value_enable, value_disable;
+	int ret = 0;
+
+	if (!intel_slpc_active(dev)) {
+		ret = -ENODEV;
+	} else if (val) {
+		intel_slpc_get_param(dev, enable_id, &override_enable,
+				     &value_enable);
+		intel_slpc_get_param(dev, disable_id, &override_disable,
+				     &value_disable);
+
+		/* set the output value:
+		* 0: default
+		* 1: enabled
+		* 2: disabled
+		* 3: unknown (should not happen)
+		*/
+		if (override_disable && (1 == value_disable))
+			*val = SLPC_PARAM_TASK_DISABLED;
+		else if (override_enable && (1 == value_enable))
+			*val = SLPC_PARAM_TASK_ENABLED;
+		else if (!override_enable && !override_disable)
+			*val = SLPC_PARAM_TASK_DEFAULT;
+		else
+			*val = SLPC_PARAM_TASK_UNKNOWN;
+
+	} else {
+		ret = -EINVAL;
+	}
+
+	return ret;
+}
+
+static int slpc_enable_disable_set(struct drm_device *dev, u64 val,
+				   enum slpc_param_id enable_id,
+				   enum slpc_param_id disable_id)
+{
+	int ret = 0;
+
+	if (!intel_slpc_active(dev)) {
+		ret = -ENODEV;
+	} else if (SLPC_PARAM_TASK_DEFAULT == val) {
+		/* set default */
+		intel_slpc_unset_param(dev, enable_id);
+		intel_slpc_unset_param(dev, disable_id);
+	} else if (SLPC_PARAM_TASK_ENABLED == val) {
+		/* set enable */
+		intel_slpc_set_param(dev, enable_id, 1);
+		intel_slpc_unset_param(dev, disable_id);
+	} else if (SLPC_PARAM_TASK_DISABLED == val) {
+		/* set disable */
+		intel_slpc_set_param(dev, disable_id, 1);
+		intel_slpc_unset_param(dev, enable_id);
+	} else {
+		ret = -EINVAL;
+	}
+
+	return ret;
+}
+
+static void slpc_param_show(struct seq_file *m, enum slpc_param_id enable_id,
+			    enum slpc_param_id disable_id)
+{
+	struct drm_device *dev = m->private;
+	const char *status;
+	u64 val;
+	int ret;
+
+	ret = slpc_enable_disable_get(dev, &val, enable_id, disable_id);
+
+	if (ret) {
+		seq_printf(m, "error %d\n", ret);
+	} else {
+		switch (val) {
+		case SLPC_PARAM_TASK_DEFAULT:
+			status = "default\n";
+			break;
+
+		case SLPC_PARAM_TASK_ENABLED:
+			status = "enabled\n";
+			break;
+
+		case SLPC_PARAM_TASK_DISABLED:
+			status = "disabled\n";
+			break;
+
+		default:
+			status = "unknown\n";
+			break;
+		}
+
+		seq_puts(m, status);
+	}
+}
+
+static int slpc_param_write(struct seq_file *m, const char __user *ubuf,
+			    size_t len, enum slpc_param_id enable_id,
+			    enum slpc_param_id disable_id)
+{
+	struct drm_device *dev = m->private;
+	u64 val;
+	int ret = 0;
+	char buf[10];
+
+	if (len >= sizeof(buf))
+		ret = -EINVAL;
+	else if (copy_from_user(buf, ubuf, len))
+		ret = -EFAULT;
+	else
+		buf[len] = '\0';
+
+	if (!ret) {
+		if (!strncmp(buf, "default", 7))
+			val = SLPC_PARAM_TASK_DEFAULT;
+		else if (!strncmp(buf, "enabled", 7))
+			val = SLPC_PARAM_TASK_ENABLED;
+		else if (!strncmp(buf, "disabled", 8))
+			val = SLPC_PARAM_TASK_DISABLED;
+		else
+			ret = -EINVAL;
+	}
+
+	if (!ret)
+		ret = slpc_enable_disable_set(dev, val, enable_id, disable_id);
+
+	return ret;
+}
+
+static int slpc_gtperf_show(struct seq_file *m, void *data)
+{
+	slpc_param_show(m, SLPC_PARAM_TASK_ENABLE_GTPERF,
+			SLPC_PARAM_TASK_DISABLE_GTPERF);
+
+	return 0;
+}
+
+static int slpc_gtperf_open(struct inode *inode, struct file *file)
+{
+	struct drm_connector *dev = inode->i_private;
+
+	return single_open(file, slpc_gtperf_show, dev);
+}
+
+static ssize_t slpc_gtperf_write(struct file *file, const char __user *ubuf,
+			      size_t len, loff_t *offp)
+{
+	struct seq_file *m = file->private_data;
+	int ret = 0;
+
+	ret = slpc_param_write(m, ubuf, len, SLPC_PARAM_TASK_ENABLE_GTPERF,
+			       SLPC_PARAM_TASK_DISABLE_GTPERF);
+	if (ret)
+		return (size_t) ret;
+
+	return len;
+}
+
+static const struct file_operations i915_slpc_gtperf_fops = {
+	.owner	 = THIS_MODULE,
+	.open	 = slpc_gtperf_open,
+	.release = single_release,
+	.read	 = seq_read,
+	.write	 = slpc_gtperf_write,
+	.llseek	 = seq_lseek
+};
+
+static int slpc_balancer_show(struct seq_file *m, void *data)
+{
+	slpc_param_show(m, SLPC_PARAM_TASK_ENABLE_BALANCER,
+			SLPC_PARAM_TASK_DISABLE_BALANCER);
+
+	return 0;
+}
+
+static int slpc_balancer_open(struct inode *inode, struct file *file)
+{
+	struct drm_connector *dev = inode->i_private;
+
+	return single_open(file, slpc_balancer_show, dev);
+}
+
+static ssize_t slpc_balancer_write(struct file *file, const char __user *ubuf,
+			      size_t len, loff_t *offp)
+{
+	struct seq_file *m = file->private_data;
+	int ret = 0;
+
+	ret = slpc_param_write(m, ubuf, len, SLPC_PARAM_TASK_ENABLE_BALANCER,
+			       SLPC_PARAM_TASK_DISABLE_BALANCER);
+	if (ret)
+		return (size_t) ret;
+
+	return len;
+}
+
+static const struct file_operations i915_slpc_balancer_fops = {
+	.owner	 = THIS_MODULE,
+	.open	 = slpc_balancer_open,
+	.release = single_release,
+	.read	 = seq_read,
+	.write	 = slpc_balancer_write,
+	.llseek	 = seq_lseek
+};
+
+static int slpc_dcc_show(struct seq_file *m, void *data)
+{
+	slpc_param_show(m, SLPC_PARAM_TASK_ENABLE_DCC,
+			SLPC_PARAM_TASK_DISABLE_DCC);
+
+	return 0;
+}
+
+static int slpc_dcc_open(struct inode *inode, struct file *file)
+{
+	struct drm_connector *dev = inode->i_private;
+
+	return single_open(file, slpc_dcc_show, dev);
+}
+
+static ssize_t slpc_dcc_write(struct file *file, const char __user *ubuf,
+			      size_t len, loff_t *offp)
+{
+	struct seq_file *m = file->private_data;
+	int ret = 0;
+
+	ret = slpc_param_write(m, ubuf, len, SLPC_PARAM_TASK_ENABLE_DCC,
+			       SLPC_PARAM_TASK_DISABLE_DCC);
+	if (ret)
+		return (size_t) ret;
+
+	return len;
+}
+
+static const struct file_operations i915_slpc_dcc_fops = {
+	.owner	 = THIS_MODULE,
+	.open	 = slpc_dcc_open,
+	.release = single_release,
+	.read	 = seq_read,
+	.write	 = slpc_dcc_write,
+	.llseek	 = seq_lseek
+};
+
 static int i915_frequency_info(struct seq_file *m, void *unused)
 {
 	struct drm_info_node *node = m->private;
@@ -5475,6 +5722,9 @@ static const struct i915_debugfs_files {
 	const struct file_operations *fops;
 } i915_debugfs_files[] = {
 	{"i915_wedged", &i915_wedged_fops},
+	{"i915_slpc_gtperf", &i915_slpc_gtperf_fops},
+	{"i915_slpc_balancer", &i915_slpc_balancer_fops},
+	{"i915_slpc_dcc", &i915_slpc_dcc_fops},
 	{"i915_max_freq", &i915_max_freq_fops},
 	{"i915_min_freq", &i915_min_freq_fops},
 	{"i915_cache_sharing", &i915_cache_sharing_fops},
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index bf09f1b..a7b2be8 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -89,6 +89,11 @@ enum slpc_param_id {
 	SLPC_PARAM_GLOBAL_DISABE_IA_GT_BALANCING = 16,
 };
 
+#define SLPC_PARAM_TASK_DEFAULT 0
+#define SLPC_PARAM_TASK_ENABLED 1
+#define SLPC_PARAM_TASK_DISABLED 2
+#define SLPC_PARAM_TASK_UNKNOWN 3
+
 enum slpc_global_state {
 	SLPC_GLOBAL_STATE_NOT_RUNNING = 0,
 	SLPC_GLOBAL_STATE_INITIALIZING = 1,
-- 
1.9.1

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[PATCH 20/21] drm/i915/slpc: Add i915_slpc_info to debugfs

[tom.orourke]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

i915_slpc_info shows the contents of SLPC shared data
parsed into text format.

v2: reformat slpc info (Radek)
    squashed query task state info
    in slpc info, kunmap before seq_print (Paulo)
    return void instead of ignored return value (Paulo)
v3: Avoid magic numbers and use local variables (Jon Bloomfield)

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 184 ++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_slpc.c   |  23 +++++
 drivers/gpu/drm/i915/intel_slpc.h   |   3 +
 3 files changed, 210 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 8b39a13..5f3780c 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1404,6 +1404,189 @@ static const struct file_operations i915_slpc_dcc_fops = {
 	.llseek	 = seq_lseek
 };
 
+static int i915_slpc_info(struct seq_file *m, void *unused)
+{
+	struct drm_info_node *node = m->private;
+	struct drm_device *dev = node->minor->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_i915_gem_object *obj;
+	struct page *page;
+	void *pv = NULL;
+	struct slpc_shared_data data;
+	int i, value;
+	enum slpc_global_state global_state;
+	enum slpc_platform_sku platform_sku;
+	enum slpc_host_os host_os;
+	enum slpc_power_plan power_plan;
+	enum slpc_power_source power_source;
+
+	obj = dev_priv->guc.slpc.shared_data_obj;
+	if (obj) {
+		intel_slpc_query_task_state(dev);
+
+		page = i915_gem_object_get_page(obj, 0);
+		if (page)
+			pv = kmap_atomic(page);
+	}
+
+	if (pv) {
+		data = *(struct slpc_shared_data *) pv;
+		kunmap_atomic(pv);
+
+		seq_printf(m, "SLPC Version: %d.%d.%d (0x%8x)\n",
+			   data.slpc_version >> 16,
+			   (data.slpc_version >> 8) & 0xFF,
+			   data.slpc_version & 0xFF,
+			   data.slpc_version);
+		seq_printf(m, "shared data size: %d\n", data.shared_data_size);
+
+		global_state = (enum slpc_global_state) data.global_state;
+		seq_printf(m, "global state: %d (", global_state);
+		switch (global_state) {
+		case SLPC_GLOBAL_STATE_NOT_RUNNING:
+			seq_puts(m, "not running)\n");
+			break;
+		case SLPC_GLOBAL_STATE_INITIALIZING:
+			seq_puts(m, "initializing)\n");
+			break;
+		case SLPC_GLOBAL_STATE_RESETTING:
+			seq_puts(m, "resetting)\n");
+			break;
+		case SLPC_GLOBAL_STATE_RUNNING:
+			seq_puts(m, "running)\n");
+			break;
+		case SLPC_GLOBAL_STATE_SHUTTING_DOWN:
+			seq_puts(m, "shutting down)\n");
+			break;
+		case SLPC_GLOBAL_STATE_ERROR:
+			seq_puts(m, "error)\n");
+			break;
+		default:
+			seq_puts(m, "unknown)\n");
+			break;
+		}
+
+		platform_sku = (enum slpc_platform_sku)
+				data.platform_info.platform_sku;
+		seq_printf(m, "sku: %d (", platform_sku);
+		switch (platform_sku) {
+		case SLPC_PLATFORM_SKU_UNDEFINED:
+			seq_puts(m, "undefined)\n");
+			break;
+		case SLPC_PLATFORM_SKU_ULX:
+			seq_puts(m, "ULX)\n");
+			break;
+		case SLPC_PLATFORM_SKU_ULT:
+			seq_puts(m, "ULT)\n");
+			break;
+		case SLPC_PLATFORM_SKU_T:
+			seq_puts(m, "T)\n");
+			break;
+		case SLPC_PLATFORM_SKU_MOBL:
+			seq_puts(m, "Mobile)\n");
+			break;
+		case SLPC_PLATFORM_SKU_DT:
+			seq_puts(m, "DT)\n");
+			break;
+		case SLPC_PLATFORM_SKU_UNKNOWN:
+		default:
+			seq_puts(m, "unknown)\n");
+			break;
+		}
+		seq_printf(m, "slice count: %d\n",
+			   data.platform_info.slice_count);
+
+		host_os = (enum slpc_host_os) data.platform_info.host_os;
+		seq_printf(m, "host OS: %d (", host_os);
+		switch (host_os) {
+		case SLPC_HOST_OS_UNDEFINED:
+			seq_puts(m, "undefined)\n");
+			break;
+		case SLPC_HOST_OS_WINDOWS_8:
+			seq_puts(m, "Windows 8)\n");
+			break;
+		default:
+			seq_puts(m, "unknown)\n");
+			break;
+		}
+
+		seq_printf(m, "power plan/source: 0x%x\n\tplan:\t",
+			   data.platform_info.power_plan_source);
+		power_plan = (enum slpc_power_plan) SLPC_POWER_PLAN(
+					data.platform_info.power_plan_source);
+		power_source = (enum slpc_power_source) SLPC_POWER_SOURCE(
+					data.platform_info.power_plan_source);
+		switch (power_plan) {
+		case SLPC_POWER_PLAN_UNDEFINED:
+			seq_puts(m, "undefined");
+			break;
+		case SLPC_POWER_PLAN_BATTERY_SAVER:
+			seq_puts(m, "battery saver");
+			break;
+		case SLPC_POWER_PLAN_BALANCED:
+			seq_puts(m, "balanced");
+			break;
+		case SLPC_POWER_PLAN_PERFORMANCE:
+			seq_puts(m, "performance");
+			break;
+		case SLPC_POWER_PLAN_UNKNOWN:
+		default:
+			seq_puts(m, "unknown");
+			break;
+		}
+		seq_puts(m, "\n\tsource:\t");
+		switch (power_source) {
+		case SLPC_POWER_SOURCE_UNDEFINED:
+			seq_puts(m, "undefined\n");
+			break;
+		case SLPC_POWER_SOURCE_AC:
+			seq_puts(m, "AC\n");
+			break;
+		case SLPC_POWER_SOURCE_DC:
+			seq_puts(m, "DC\n");
+			break;
+		case SLPC_POWER_SOURCE_UNKNOWN:
+		default:
+			seq_puts(m, "unknown\n");
+			break;
+		}
+
+		seq_printf(m, "IA frequency (MHz):\n\tP0: %d\n\tP1: %d\n\tPe: %d\n\tPn: %d\n",
+			   data.platform_info.P0_freq * 50,
+			   data.platform_info.P1_freq * 50,
+			   data.platform_info.Pe_freq * 50,
+			   data.platform_info.Pn_freq * 50);
+		seq_printf(m, "RAPL package power limits:\n\t0x%08x\n\t0x%08x\n",
+			   data.platform_info.package_rapl_limit_high,
+			   data.platform_info.package_rapl_limit_low);
+		seq_printf(m, "task state data: 0x%08x\n",
+			   data.task_state_data);
+		seq_printf(m, "\tturbo active: %d\n",
+			   (data.task_state_data & 1));
+		seq_printf(m, "\tdfps stall possible: %d\n\tgame mode: %d\n\tdfps target fps: %d\n",
+			   (data.task_state_data & 2),
+			   (data.task_state_data & 4),
+			   (data.task_state_data >> 3) & 0xFF);
+
+		seq_puts(m, "override parameter bitfield\n");
+		for (i = 0; i < SLPC_OVERRIDE_BITFIELD_SIZE; i++)
+			seq_printf(m, "%d: 0x%08x\n", i,
+				   data.override_parameters_set_bits[i]);
+
+		seq_puts(m, "override parameters (only non-zero shown)\n");
+		for (i = 0; i < SLPC_MAX_OVERRIDE_PARAMETERS; i++) {
+			value = data.override_parameters_values[i];
+			if (value)
+				seq_printf(m, "%d: 0x%8x\n", i, value);
+		}
+
+	} else {
+		seq_puts(m, "no SLPC info available\n");
+	}
+
+	return 0;
+}
+
 static int i915_frequency_info(struct seq_file *m, void *unused)
 {
 	struct drm_info_node *node = m->private;
@@ -5680,6 +5863,7 @@ static const struct drm_info_list i915_debugfs_list[] = {
 	{"i915_guc_info", i915_guc_info, 0},
 	{"i915_guc_load_status", i915_guc_load_status_info, 0},
 	{"i915_guc_log_dump", i915_guc_log_dump, 0},
+	{"i915_slpc_info", i915_slpc_info, 0},
 	{"i915_frequency_info", i915_frequency_info, 0},
 	{"i915_hangcheck_info", i915_hangcheck_info, 0},
 	{"i915_drpc_info", i915_drpc_info, 0},
diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index 7b14a45..92e68ce 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -118,6 +118,23 @@ static void host2guc_slpc_unset_param(struct drm_device *dev,
 	host2guc_slpc(dev_priv, data, 3);
 }
 
+static void host2guc_slpc_query_task_state(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_i915_gem_object *obj = dev_priv->guc.slpc.shared_data_obj;
+	u32 data[4];
+	u64 shared_data_gtt_offset = i915_gem_obj_ggtt_offset(obj);
+
+	data[0] = HOST2GUC_ACTION_SLPC_REQUEST;
+	data[1] = SLPC_EVENT(SLPC_EVENT_QUERY_TASK_STATE, 2);
+	data[2] = lower_32_bits(shared_data_gtt_offset);
+	data[3] = upper_32_bits(shared_data_gtt_offset);
+
+	WARN_ON(0 != data[3]);
+
+	host2guc_slpc(dev_priv, data, 4);
+}
+
 static u8 slpc_get_platform_sku(struct drm_i915_gem_object *obj)
 {
 	struct drm_device *dev = obj->base.dev;
@@ -491,3 +508,9 @@ void intel_slpc_get_param(struct drm_device *dev, enum slpc_param_id id,
 		kunmap_atomic(data);
 	}
 }
+
+void intel_slpc_query_task_state(struct drm_device *dev)
+{
+	if (intel_slpc_active(dev))
+		host2guc_slpc_query_task_state(dev);
+}
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index a7b2be8..95c8218 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -134,6 +134,8 @@ enum slpc_power_source {
 };
 
 #define SLPC_POWER_PLAN_SOURCE(plan, source) ((plan) | ((source) << 6))
+#define SLPC_POWER_PLAN(plan_source) ((plan_source) & 0x3F)
+#define SLPC_POWER_SOURCE(plan_source) ((plan_source) >> 6)
 
 struct slpc_platform_info {
 	u8 platform_sku;
@@ -211,4 +213,5 @@ void intel_slpc_set_param(struct drm_device *dev, enum slpc_param_id id,
 			  u32 value);
 void intel_slpc_get_param(struct drm_device *dev, enum slpc_param_id id,
 			  int *overriding, u32 *value);
+void intel_slpc_query_task_state(struct drm_device *dev);
 #endif
-- 
1.9.1

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[PATCH 21/21] drm/i915/slpc: Fail intel_runtime_suspend if SLPC or RPS not active

[tom.orourke]

From: Sagar Arun Kamble <sagar.a.kamble@intel.com>

intel_runtime_suspend failed with warning if RPS was disabled.
With SLPC enabled, RPS is disabled. With SLPC, warning is now changed
to consider SLPC active status as well. This will ensure runtime suspend
proceeds when SLPC enabled.

v2: Commit message update. (Tom)

Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index cc22fa0..00a2713 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1474,7 +1474,8 @@ static int intel_runtime_suspend(struct device *device)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	int ret;
 
-	if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6(dev))))
+	if (WARN_ON_ONCE(!((dev_priv->rps.enabled || intel_slpc_active(dev)) &&
+			   intel_enable_rc6(dev))))
 		return -ENODEV;
 
 	if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
-- 
1.9.1

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Re: [PATCH 10/21] drm/i915/slpc: Update current requested frequency

[Chris Wilson]

On Wed, Apr 27, 2016 at 06:10:54PM -0700, tom.orourke@intel.com wrote:
> From: Tom O'Rourke <Tom.O'Rourke@intel.com>
> 
> When SLPC is controlling requested frequency, the rps.cur_freq
> value is not used to make the frequency request.
> 
> Before using rps.cur_freq in sysfs or debugfs, read
> requested frequency from register to get the value
> most recently requested by SLPC firmware.
> 
> v2: replace HAS_SLPC with intel_slpc_active (Paulo)
> v3: Avoid magic numbers (Nick)
>     Use a function for repeated code (Jon)
> 
> Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c | 6 ++++++
>  drivers/gpu/drm/i915/i915_drv.h     | 5 +++++
>  drivers/gpu/drm/i915/i915_reg.h     | 1 +
>  drivers/gpu/drm/i915/i915_sysfs.c   | 3 +++
>  4 files changed, 15 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 8b8d6f0..1295d8b 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1168,6 +1168,9 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
>  
>  	flush_delayed_work(&dev_priv->rps.delayed_resume_work);
>  
> +	if (intel_slpc_active(dev))
> +		dev_priv->rps.cur_freq = gen9_read_requested_freq(dev_priv);

No. This must remain our own cur_freq.

What you want to report is the HW current requested frequency, but the
reporting of our SW state must remain just that.

Do not fudge our bookkeeping when reporting it, you are just papering
over the very bug it is trying to report.

> +
>  	if (IS_GEN5(dev)) {
>  		u16 rgvswctl = I915_READ16(MEMSWCTL);
>  		u16 rgvstat = I915_READ16(MEMSTAT_ILK);
> @@ -2399,6 +2402,9 @@ static int i915_rps_boost_info(struct seq_file *m, void *data)
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	struct drm_file *file;
>  
> +	if (intel_slpc_active(dev))
> +		dev_priv->rps.cur_freq = gen9_read_requested_freq(dev_priv);

This is just silly since this whole mechanism is nerfed.

> diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
> index 2d576b7..826e40c 100644
> --- a/drivers/gpu/drm/i915/i915_sysfs.c
> +++ b/drivers/gpu/drm/i915/i915_sysfs.c
> @@ -318,6 +318,9 @@ static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
>  	intel_runtime_pm_get(dev_priv);
>  
>  	mutex_lock(&dev_priv->rps.hw_lock);
> +	if (intel_slpc_active(dev))
> +		dev_priv->rps.cur_freq = gen9_read_requested_freq(dev_priv);

We don't have a sysfs for reporting the HW requested frequency. If you
make the change here for SLPC, make the change for the other gen as
well. It's the important distinction between using cur_freq and RPNSWREQ.
-Chris

-- 
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Re: [PATCH 07/21] drm/i915/slpc: If using SLPC, do not set frequency

[Chris Wilson]

On Wed, Apr 27, 2016 at 06:10:51PM -0700, tom.orourke@intel.com wrote:
> From: Tom O'Rourke <Tom.O'Rourke@intel.com>
> 
> When frequency requests are made by SLPC, host driver
> should not attempt to make frequency requests due to
> potential conflicts.
> 
> Host-based turbo operations are already avoided when
> SLPC is used.  This change covers other frequency
> requests such as from sysfs or debugfs interfaces.
> 
> A later patch in this series updates sysfs/debugfs
> interfaces for setting max/min frequencies with SLPC.

Since under your scheme, this function is only called from those user
interfaces, why haven't you implemented it here? As the intel_set_* it
is meant to providing the uniform API supporting as many generation as
possible, without having to spread that knowledge around. You have not
explained the API change.
-Chris

-- 
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Re: [PATCH 09/21] drm/i915/slpc: Setup rps frequency values during SLPC init

[Chris Wilson]

On Wed, Apr 27, 2016 at 06:10:53PM -0700, tom.orourke@intel.com wrote:
> From: Tom O'Rourke <Tom.O'Rourke@intel.com>
> 
> v2: Add mutex lock/unlock
> 
> Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_drv.h  | 1 +
>  drivers/gpu/drm/i915/intel_pm.c   | 2 +-
>  drivers/gpu/drm/i915/intel_slpc.c | 5 +++++
>  3 files changed, 7 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 47e538a..006a8c7 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1612,6 +1612,7 @@ void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
>  void intel_pm_setup(struct drm_device *dev);
>  void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
>  void intel_gpu_ips_teardown(void);
> +void gen6_init_rps_frequencies(struct drm_device *dev);

??? You appear to be exporting a private gen-specific routine.

Why? You haven't explained why!

From the looks of it you have a bootstrap ordering issue.

Why did you choose to do this? Why didn't you choose to export a more
general setup routine? Why couldn't you use an existing setup point? Why
couldn't we reorder as required?
-Chris

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Re: [PATCH 03/21] drm/i915/slpc: Add slpc_version_check

[Chris Wilson]

On Wed, Apr 27, 2016 at 06:10:47PM -0700, tom.orourke@intel.com wrote:
> From: Tom O'Rourke <Tom.O'Rourke@intel.com>
> 
> The SLPC interface has changed and could continue to
> change.  Only GuC versions known to be compatible are
> supported here.
> 
> On Skylake, GuC firmware v6 is supported.  Other
> platforms and versions can be added here later.
> 
> This patch also adds has_slpc to skylake info.
> 
> v2: Move slpc_version_check to intel_guc_ucode_init
> v3: fix whitespace (Sagar)
> ---
>  drivers/gpu/drm/i915/i915_drv.c         |  1 +
>  drivers/gpu/drm/i915/intel_guc_loader.c | 14 ++++++++++++++
>  2 files changed, 15 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index d37c0a6..cc22fa0 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -334,6 +334,7 @@ static const struct intel_device_info intel_skylake_info = {
>  	BDW_FEATURES,
>  	.is_skylake = 1,
>  	.gen = 9,
> +	.has_slpc = 1,
>  };
>  
>  static const struct intel_device_info intel_skylake_gt3_info = {
> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
> index 876e5da..87702cd 100644
> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> @@ -116,6 +116,18 @@ static void direct_interrupts_to_guc(struct drm_i915_private *dev_priv)
>  	I915_WRITE(GUC_WD_VECS_IER, ~irqs);
>  }
>  
> +static void slpc_version_check(struct drm_device *dev,
> +			       struct intel_guc_fw *guc_fw)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	struct intel_device_info *info;
> +
> +	if (IS_SKYLAKE(dev) && (guc_fw->guc_fw_major_found != 6)) {
> +		info = (struct intel_device_info *) &dev_priv->info;
> +		info->has_slpc = 0;

dev_priv->info.has_slpc = 0;

And pass around dev_priv. Nothing here uses dev.
-Chris

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Re: [PATCH 21/21] drm/i915/slpc: Fail intel_runtime_suspend if SLPC or RPS not active

[Chris Wilson]

On Wed, Apr 27, 2016 at 06:11:05PM -0700, tom.orourke@intel.com wrote:
> From: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> 
> intel_runtime_suspend failed with warning if RPS was disabled.
> With SLPC enabled, RPS is disabled. With SLPC, warning is now changed
> to consider SLPC active status as well. This will ensure runtime suspend
> proceeds when SLPC enabled.
> 
> v2: Commit message update. (Tom)
> 
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index cc22fa0..00a2713 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1474,7 +1474,8 @@ static int intel_runtime_suspend(struct device *device)
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	int ret;
>  
> -	if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6(dev))))
> +	if (WARN_ON_ONCE(!((dev_priv->rps.enabled || intel_slpc_active(dev)) &&
> +			   intel_enable_rc6(dev))))

The real question here is why does runtime suspend depend on either of
these being enabled (espcially rps!).

Imre?
-Chris

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Re: [PATCH 01/21] drm/i915/slpc: Expose guc functions for use with SLPC

[Chris Wilson]

On Wed, Apr 27, 2016 at 06:10:45PM -0700, tom.orourke@intel.com wrote:
> From: Tom O'Rourke <Tom.O'Rourke@intel.com>
> 
> Expose host2guc_action for use by SLPC in intel_slpc.c.
> 
> Expose functions to allocate and release objects used
> by GuC to be used for SLPC shared memory object.
> 
> Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_guc_submission.c | 6 +++---
>  drivers/gpu/drm/i915/intel_guc.h           | 4 ++++
>  2 files changed, 7 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
> index 72d6665..aba1155 100644
> --- a/drivers/gpu/drm/i915/i915_guc_submission.c
> +++ b/drivers/gpu/drm/i915/i915_guc_submission.c
> @@ -75,7 +75,7 @@ static inline bool host2guc_action_response(struct drm_i915_private *dev_priv,
>  	return GUC2HOST_IS_RESPONSE(val);
>  }
>  
> -static int host2guc_action(struct intel_guc *guc, u32 *data, u32 len)
> +int host2guc_action(struct intel_guc *guc, u32 *data, u32 len)

That name doesn't fit well into our extern symbol naming scheme.

>  	struct drm_i915_private *dev_priv = guc_to_i915(guc);
>  	u32 status;
> @@ -581,7 +581,7 @@ int i915_guc_submit(struct i915_guc_client *client,
>   *
>   * Return:	A drm_i915_gem_object if successful, otherwise NULL.
>   */
> -static struct drm_i915_gem_object *gem_allocate_guc_obj(struct drm_device *dev,
> +struct drm_i915_gem_object *gem_allocate_guc_obj(struct drm_device *dev,
> -static void gem_release_guc_obj(struct drm_i915_gem_object *obj)
> +void gem_release_guc_obj(struct drm_i915_gem_object *obj)

These functions are not under GEM. Please rename them, they are provided
by the GuC using GEM, not vice verse.
-Chris

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Re: [PATCH 04/21] drm/i915/slpc: Add enable_slpc module parameter

[Chris Wilson]

On Wed, Apr 27, 2016 at 06:10:48PM -0700, tom.orourke@intel.com wrote:
>  static void slpc_version_check(struct drm_device *dev,
>  			       struct intel_guc_fw *guc_fw)
>  {
> @@ -126,6 +141,8 @@ static void slpc_version_check(struct drm_device *dev,
>  		info = (struct intel_device_info *) &dev_priv->info;
>  		info->has_slpc = 0;
>  	}
> +
> +	slpc_enable_sanitize(dev);
>  }
>  
>  static u32 get_gttype(struct drm_i915_private *dev_priv)
> @@ -657,6 +674,8 @@ void intel_guc_ucode_init(struct drm_device *dev)
>  		fw_path = "";	/* unknown device */
>  	}
>  
> +	slpc_enable_sanitize(dev);

Calling it twice is a very bad sign that you have your ordering wrong.
-Chris

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Re: [PATCH 12/21] drm/i915/slpc: Send shutdown event

[Chris Wilson]

On Wed, Apr 27, 2016 at 06:10:56PM -0700, tom.orourke@intel.com wrote:
> From: Tom O'Rourke <Tom.O'Rourke@intel.com>
> 
> Send SLPC shutdown event during disable, suspend, and reset
> operations.  Sending shutdown event while already shutdown
> is OK.
> 
> v2: return void instead of ignored error code (Paulo)
> 
> Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_slpc.c | 28 +++++++++++++++++++++++++---
>  1 file changed, 25 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
> index 3fd46ac..076d07b 100644
> --- a/drivers/gpu/drm/i915/intel_slpc.c
> +++ b/drivers/gpu/drm/i915/intel_slpc.c
> @@ -56,6 +56,23 @@ static void host2guc_slpc_reset(struct drm_device *dev)
>  	host2guc_slpc(dev_priv, data, 4);
>  }
>  
> +static void host2guc_slpc_shutdown(struct drm_device *dev)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	struct drm_i915_gem_object *obj = dev_priv->guc.slpc.shared_data_obj;
> +	u32 data[4];
> +	u64 shared_data_gtt_offset = i915_gem_obj_ggtt_offset(obj);
> +
> +	data[0] = HOST2GUC_ACTION_SLPC_REQUEST;
> +	data[1] = SLPC_EVENT(SLPC_EVENT_SHUTDOWN, 2);
> +	data[2] = lower_32_bits(shared_data_gtt_offset);
> +	data[3] = upper_32_bits(shared_data_gtt_offset);
> +
> +	WARN_ON(0 != data[3]);

Why WARN here? Why not WARN during setup and clamp the GGTT to what the
GuC supports? Shutting the stable door after the horse has bolted...

What happens to the guc if this WARN fires? Is it even sensible to be
programming the hardware to a value you know is bogus? These are the
questions you raise by having an unhandled WARN.
-Chris

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Re: [PATCH 08/21] drm/i915/slpc: Allocate/Release/Initialize SLPC shared data

[Chris Wilson]

On Wed, Apr 27, 2016 at 06:10:52PM -0700, tom.orourke@intel.com wrote:
>  void intel_slpc_init(struct drm_device *dev)
>  {
> -	return;
> +	struct drm_i915_private *dev_priv = dev->dev_private;

So what you wanted was dev_priv not dev!

> +	struct drm_i915_gem_object *obj;
> +
> +	/* Allocate shared data structure */
> +	obj = dev_priv->guc.slpc.shared_data_obj;

This function (init) should be called exactly once. Do you intend to
also be part of the the init_hw phase?
-Chris

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✓ Fi.CI.BAT: success for Add support for GuC-based SLPC (rev4)

[Patchwork]

== Series Details ==

Series: Add support for GuC-based SLPC (rev4)
URL   : https://patchwork.freedesktop.org/series/2691/
State : success

== Summary ==

Series 2691v4 Add support for GuC-based SLPC
http://patchwork.freedesktop.org/api/1.0/series/2691/revisions/4/mbox/


bdw-nuci7        total:201  pass:189  dwarn:0   dfail:0   fail:0   skip:12 
bdw-ultra        total:201  pass:176  dwarn:0   dfail:0   fail:0   skip:25 
byt-nuc          total:200  pass:159  dwarn:0   dfail:0   fail:0   skip:41 
hsw-brixbox      total:201  pass:175  dwarn:0   dfail:0   fail:0   skip:26 
ilk-hp8440p      total:201  pass:140  dwarn:0   dfail:0   fail:0   skip:61 
ivb-t430s        total:201  pass:170  dwarn:0   dfail:0   fail:0   skip:31 
skl-i7k-2        total:201  pass:174  dwarn:0   dfail:0   fail:0   skip:27 
skl-nuci5        total:201  pass:190  dwarn:0   dfail:0   fail:0   skip:11 
snb-dellxps      total:201  pass:159  dwarn:0   dfail:0   fail:0   skip:42 

Results at /archive/results/CI_IGT_test/Patchwork_2098/

c5c937220f88dcadac8da2377e141cf998968efc drm-intel-nightly: 2016y-04m-27d-19h-36m-40s UTC integration manifest
e6ed997 drm/i915/slpc: Fail intel_runtime_suspend if SLPC or RPS not active
9411821 drm/i915/slpc: Add i915_slpc_info to debugfs
33e5020 drm/i915/slpc: Add enable/disable debugfs for slpc
d5c7a8e drm/i915/slpc: Add slpc support for max/min freq
eedb7c6 drm/i915/slpc: Add parameter unset/set/get functions
d5f3f37 drm/i915/slpc: Add slpc_status enum values
03b71c67 drm/i915/slpc: Notification of Refresh Rate change
c4ea5c2 drm/i915/slpc: Notification of Display mode change
9cb7438 drm/i915/slpc: Add Display mode event related data structures
4e6aad8 drm/i915/slpc: Send shutdown event
ec89896 drm/i915/slpc: Send reset event
4672870 drm/i915/slpc: Update current requested frequency
deb9ae3 drm/i915/slpc: Setup rps frequency values during SLPC init
09475da drm/i915/slpc: Allocate/Release/Initialize SLPC shared data
0014e5b drm/i915/slpc: If using SLPC, do not set frequency
c7c31aa drm/i915/slpc: Enable SLPC in guc if supported
660a241 drm/i915/slpc: Use intel_slpc_* functions if supported
3643533 drm/i915/slpc: Add enable_slpc module parameter
78b2ce6 drm/i915/slpc: Add slpc_version_check
7879d85 drm/i915/slpc: Add has_slpc capability flag
c451928 drm/i915/slpc: Expose guc functions for use with SLPC

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Re: [PATCH 19/21] drm/i915/slpc: Add enable/disable debugfs for slpc

[Chris Wilson]

On Wed, Apr 27, 2016 at 06:11:03PM -0700, tom.orourke@intel.com wrote:
> +static ssize_t slpc_balancer_write(struct file *file, const char __user *ubuf,
> +			      size_t len, loff_t *offp)
> +{
> +	struct seq_file *m = file->private_data;
> +	int ret = 0;
> +
> +	ret = slpc_param_write(m, ubuf, len, SLPC_PARAM_TASK_ENABLE_BALANCER,
> +			       SLPC_PARAM_TASK_DISABLE_BALANCER);
> +	if (ret)
> +		return (size_t) ret;

(ssize_t)(size_t)(int)

Spot the problem?

	return slpc_param_write(file->private_data, ubuf, len,
				SLPC_PARAM_TASK_ENABLE_BALANCER,
				SLPC_PARAM_TASK_DISABLE_BALANCER);
-Chris

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Re: [PATCH 21/21] drm/i915/slpc: Fail intel_runtime_suspend if SLPC or RPS not active

[Imre Deak]

On to, 2016-04-28 at 07:56 +0100, Chris Wilson wrote:
> On Wed, Apr 27, 2016 at 06:11:05PM -0700, tom.orourke@intel.com wrote:
> > From: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> > 
> > intel_runtime_suspend failed with warning if RPS was disabled.
> > With SLPC enabled, RPS is disabled. With SLPC, warning is now changed
> > to consider SLPC active status as well. This will ensure runtime suspend
> > proceeds when SLPC enabled.
> > 
> > v2: Commit message update. (Tom)
> > 
> > Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> > Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_drv.c | 3 ++-
> >  1 file changed, 2 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> > index cc22fa0..00a2713 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.c
> > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > @@ -1474,7 +1474,8 @@ static int intel_runtime_suspend(struct device *device)
> >  	struct drm_i915_private *dev_priv = dev->dev_private;
> >  	int ret;
> >  
> > -	if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6(dev))))
> > +	if (WARN_ON_ONCE(!((dev_priv->rps.enabled || intel_slpc_active(dev)) &&
> > +			   intel_enable_rc6(dev))))
> 
> The real question here is why does runtime suspend depend on either of
> these being enabled (espcially rps!).

We need RC6 enabled across a runtime suspend/resume since we depend on
the RC6 context to be retained across these transitions. There is no
separate knob for RPS and we enable RC6 and RPS together, that's why
rps.enabled is checked.

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Re: [PATCH 21/21] drm/i915/slpc: Fail intel_runtime_suspend if SLPC or RPS not active

[Chris Wilson]

On Thu, Apr 28, 2016 at 10:57:20AM +0300, Imre Deak wrote:
> On to, 2016-04-28 at 07:56 +0100, Chris Wilson wrote:
> > On Wed, Apr 27, 2016 at 06:11:05PM -0700, tom.orourke@intel.com wrote:
> > > From: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> > > 
> > > intel_runtime_suspend failed with warning if RPS was disabled.
> > > With SLPC enabled, RPS is disabled. With SLPC, warning is now changed
> > > to consider SLPC active status as well. This will ensure runtime suspend
> > > proceeds when SLPC enabled.
> > > 
> > > v2: Commit message update. (Tom)
> > > 
> > > Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> > > Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/i915_drv.c | 3 ++-
> > >  1 file changed, 2 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> > > index cc22fa0..00a2713 100644
> > > --- a/drivers/gpu/drm/i915/i915_drv.c
> > > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > > @@ -1474,7 +1474,8 @@ static int intel_runtime_suspend(struct device *device)
> > >  	struct drm_i915_private *dev_priv = dev->dev_private;
> > >  	int ret;
> > >  
> > > -	if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6(dev))))
> > > +	if (WARN_ON_ONCE(!((dev_priv->rps.enabled || intel_slpc_active(dev)) &&
> > > +			   intel_enable_rc6(dev))))
> > 
> > The real question here is why does runtime suspend depend on either of
> > these being enabled (espcially rps!).
> 
> We need RC6 enabled across a runtime suspend/resume since we depend on
> the RC6 context to be retained across these transitions. There is no
> separate knob for RPS and we enable RC6 and RPS together, that's why
> rps.enabled is checked.

So, from the standpoint of this series, we should be separating the two
and giving rc6 its own bit of bookkeeping.
-Chris

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Re: [PATCH 15/21] drm/i915/slpc: Notification of Refresh Rate change

[Daniel Vetter]

On Wed, Apr 27, 2016 at 06:10:59PM -0700, tom.orourke@intel.com wrote:
> From: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> 
> This patch will inform GuC SLPC about changes in the refresh rate
> due to Seamless DRRS. Refresh rate changes due to Static DRRS will
> be notified via commit path.
> 
> v2: Rebased on previous changed patch and printed error message if
> H2G action fails.
> v2(torourke): Updates suggested by Paulo: replace HAS_SLPC with
> intel_slpc_active. return void instead of ignored error code.
> 
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>

So all this display notification stuff looks real fancy, but we have it
already in the kernel. We notice when we're late in a frame, and then
aggressively ramp up.

I want to see an implementation that reuses that infrastructure and just
tells guc to hurry up, and then benchmark against this one (wrt overall
frame latency distribution in spikey workloads). All this complexity and
an entire 2nd codepath needs to be justified in a unified driver, and I
see exactly none of that going on.

Also we need to figure out what kind of exact&minimal lie we need to feed
guc in this case, that needs some collab with the firmware team.
-Daniel

> ---
>  drivers/gpu/drm/i915/intel_dp.c   |  2 ++
>  drivers/gpu/drm/i915/intel_slpc.c | 23 +++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_slpc.h |  1 +
>  3 files changed, 26 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index c12c414..3d41f7b 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -5379,6 +5379,8 @@ static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
>  	dev_priv->drrs.refresh_rate_type = index;
>  
>  	DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
> +
> +	intel_slpc_update_display_rr_info(dev, refresh_rate);
>  }
>  
>  /**
> diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
> index 7f26284..9e0bc96 100644
> --- a/drivers/gpu/drm/i915/intel_slpc.c
> +++ b/drivers/gpu/drm/i915/intel_slpc.c
> @@ -364,3 +364,26 @@ void intel_slpc_update_atomic_commit_info(struct drm_device *dev,
>  	if (notify)
>  		host2guc_slpc_display_mode_change(dev);
>  }
> +
> +void intel_slpc_update_display_rr_info(struct drm_device *dev, u32 refresh_rate)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	struct drm_crtc *crtc;
> +	struct intel_display_pipe_info *per_pipe_info;
> +	struct intel_slpc_display_mode_event_params *display_params;
> +
> +	if (!intel_slpc_active(dev))
> +		return;
> +
> +	if (!refresh_rate)
> +		return;
> +
> +	display_params = &dev_priv->guc.slpc.display_mode_params;
> +	crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
> +
> +	per_pipe_info = &display_params->per_pipe_info[to_intel_crtc(crtc)->pipe];
> +	per_pipe_info->refresh_rate = refresh_rate;
> +	per_pipe_info->vsync_ft_usec = 1000000 / refresh_rate;
> +
> +	host2guc_slpc_display_mode_change(dev);
> +}
> diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
> index 39b4657..0b251a1 100644
> --- a/drivers/gpu/drm/i915/intel_slpc.h
> +++ b/drivers/gpu/drm/i915/intel_slpc.h
> @@ -153,5 +153,6 @@ void intel_slpc_reset(struct drm_device *dev);
>  void intel_slpc_update_display_mode_info(struct drm_device *dev);
>  void intel_slpc_update_atomic_commit_info(struct drm_device *dev,
>  					  struct drm_atomic_state *state);
> +void intel_slpc_update_display_rr_info(struct drm_device *dev, u32 refresh_rate);
>  
>  #endif
> -- 
> 1.9.1
> 
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

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Re: [PATCH 15/21] drm/i915/slpc: Notification of Refresh Rate change

[Daniel Vetter]

On Thu, Apr 28, 2016 at 10:38:27AM +0200, Daniel Vetter wrote:
> On Wed, Apr 27, 2016 at 06:10:59PM -0700, tom.orourke@intel.com wrote:
> > From: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> > 
> > This patch will inform GuC SLPC about changes in the refresh rate
> > due to Seamless DRRS. Refresh rate changes due to Static DRRS will
> > be notified via commit path.
> > 
> > v2: Rebased on previous changed patch and printed error message if
> > H2G action fails.
> > v2(torourke): Updates suggested by Paulo: replace HAS_SLPC with
> > intel_slpc_active. return void instead of ignored error code.
> > 
> > Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> > Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
> 
> So all this display notification stuff looks real fancy, but we have it
> already in the kernel. We notice when we're late in a frame, and then
> aggressively ramp up.
> 
> I want to see an implementation that reuses that infrastructure and just
> tells guc to hurry up, and then benchmark against this one (wrt overall
> frame latency distribution in spikey workloads). All this complexity and
> an entire 2nd codepath needs to be justified in a unified driver, and I
> see exactly none of that going on.

+ power consumption benchmarks ofc, since current code also aggressively
downclocks again when the burst is over. My concern here is that
fundamentally guc just doesn't know enough to make a good decision here,
or at least it can react only much later. Whereas the kernel actually
knows what atomic display update it has pending, and what exactly it needs
to boost to get that to the screen asap.
-Daniel
-- 
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Re: [PATCH v4 00/21] Add support for GuC-based SLPC

[O'Rourke, Tom]

On Wed, Apr 27, 2016 at 06:10:44PM -0700, tom.orourke@intel.com wrote:
> From: Tom O'Rourke <Tom.O'Rourke@intel.com>
> 
> SLPC (Single Loop Power Controller) is a replacement for
> some host-based power management features.  The SLPC
> implemenation runs in firmware on GuC.
> 
> This series has been tested with SKL guc firmware
> version 6.1.
> 
> The graphics power management features in SLPC in those
> versions are called GTPERF, BALANCER, and DCC.
> 
> GTPERF is a combination of DFPS (Dynamic FPS) and Turbo.
> DFPS adjusts requested graphics frequency to maintain
> target framerate.  Turbo adjusts requested graphics
> frequency to maintain target GT busyness; this includes
> an adaptive boost turbo method.
> 
> BALANCER adjusts balance between power budgets for IA
> and GT in power limited scenarios.  BALANCER is only
> active when all display pipes are in "game" mode.
> 
> DCC (Duty Cycle Control) adjusts requested graphics
> frequency and stalls guc-scheduler to maintain actual
> graphics frequency in efficient range.
> 
> The v3 series can be found in the archive at
> "[Intel-gfx] [PATCH v3 00/25] Add support for GuC-based SLPC"
> https://lists.freedesktop.org/archives/intel-gfx/2016-April/091771.html
> 
> This v4 series incorporates feedback from internal code 
> reviews for Android and Yocto projects.  This series also 
> drops the Broxton patches; the Broxton firmware has not 
> been published yet.  Broxton support can be added later 
> when the Broxton firmware is available. 
> 
> Also, the "DO NOT MERGE" patches to enable SLPC and guc 
> submission by default have been dropped.  These can be 
> added later after SLPC has been shown to outperform 
> host-based power management; this may require a newer 
> version of the GuC firmware.
> 
> With SLPC disabled by default, this series should be 
> safe to merge now. 
> 
> VIZ-6773, VIZ-6889

Thank you to Chris, Daniel and Imre for your comments.  
I agree that some of the suggested changes should be made.  

Whether those changes should be made before merging or with 
later patches will be someone else's problem.  

I won't be sending another version of this series.

Thanks,
Tom O'Rourke

> 
> Sagar Arun Kamble (4):
>   drm/i915/slpc: Add Display mode event related data structures
>   drm/i915/slpc: Notification of Display mode change
>   drm/i915/slpc: Notification of Refresh Rate change
>   drm/i915/slpc: Fail intel_runtime_suspend if SLPC or RPS not active
> 
> Tom O'Rourke (17):
>   drm/i915/slpc: Expose guc functions for use with SLPC
>   drm/i915/slpc: Add has_slpc capability flag
>   drm/i915/slpc: Add slpc_version_check
>   drm/i915/slpc: Add enable_slpc module parameter
>   drm/i915/slpc: Use intel_slpc_* functions if supported
>   drm/i915/slpc: Enable SLPC in guc if supported
>   drm/i915/slpc: If using SLPC, do not set frequency
>   drm/i915/slpc: Allocate/Release/Initialize SLPC shared data
>   drm/i915/slpc: Setup rps frequency values during SLPC init
>   drm/i915/slpc: Update current requested frequency
>   drm/i915/slpc: Send reset event
>   drm/i915/slpc: Send shutdown event
>   drm/i915/slpc: Add slpc_status enum values
>   drm/i915/slpc: Add parameter unset/set/get functions
>   drm/i915/slpc: Add slpc support for max/min freq
>   drm/i915/slpc: Add enable/disable debugfs for slpc
>   drm/i915/slpc: Add i915_slpc_info to debugfs
> 
>  drivers/gpu/drm/i915/Makefile              |   5 +-
>  drivers/gpu/drm/i915/i915_debugfs.c        | 456 +++++++++++++++++++++++++
>  drivers/gpu/drm/i915/i915_drv.c            |   4 +-
>  drivers/gpu/drm/i915/i915_drv.h            |   7 +
>  drivers/gpu/drm/i915/i915_guc_submission.c |   6 +-
>  drivers/gpu/drm/i915/i915_params.c         |   6 +
>  drivers/gpu/drm/i915/i915_params.h         |   1 +
>  drivers/gpu/drm/i915/i915_reg.h            |   1 +
>  drivers/gpu/drm/i915/i915_sysfs.c          |  21 ++
>  drivers/gpu/drm/i915/intel_display.c       |   2 +
>  drivers/gpu/drm/i915/intel_dp.c            |   2 +
>  drivers/gpu/drm/i915/intel_drv.h           |  11 +
>  drivers/gpu/drm/i915/intel_guc.h           |  13 +
>  drivers/gpu/drm/i915/intel_guc_loader.c    |  36 ++
>  drivers/gpu/drm/i915/intel_pm.c            |  42 ++-
>  drivers/gpu/drm/i915/intel_slpc.c          | 516 +++++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_slpc.h          | 217 ++++++++++++
>  17 files changed, 1329 insertions(+), 17 deletions(-)
>  create mode 100644 drivers/gpu/drm/i915/intel_slpc.c
>  create mode 100644 drivers/gpu/drm/i915/intel_slpc.h
> 
> -- 
> 1.9.1
> 
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Re: [PATCH v4 00/21] Add support for GuC-based SLPC

[Chris Wilson]

On Thu, Apr 28, 2016 at 04:01:14PM -0700, O'Rourke, Tom wrote:
> On Wed, Apr 27, 2016 at 06:10:44PM -0700, tom.orourke@intel.com wrote:
> > From: Tom O'Rourke <Tom.O'Rourke@intel.com>
> > 
> > SLPC (Single Loop Power Controller) is a replacement for
> > some host-based power management features.  The SLPC
> > implemenation runs in firmware on GuC.
> > 
> > This series has been tested with SKL guc firmware
> > version 6.1.
> > 
> > The graphics power management features in SLPC in those
> > versions are called GTPERF, BALANCER, and DCC.
> > 
> > GTPERF is a combination of DFPS (Dynamic FPS) and Turbo.
> > DFPS adjusts requested graphics frequency to maintain
> > target framerate.  Turbo adjusts requested graphics
> > frequency to maintain target GT busyness; this includes
> > an adaptive boost turbo method.
> > 
> > BALANCER adjusts balance between power budgets for IA
> > and GT in power limited scenarios.  BALANCER is only
> > active when all display pipes are in "game" mode.
> > 
> > DCC (Duty Cycle Control) adjusts requested graphics
> > frequency and stalls guc-scheduler to maintain actual
> > graphics frequency in efficient range.
> > 
> > The v3 series can be found in the archive at
> > "[Intel-gfx] [PATCH v3 00/25] Add support for GuC-based SLPC"
> > https://lists.freedesktop.org/archives/intel-gfx/2016-April/091771.html
> > 
> > This v4 series incorporates feedback from internal code 
> > reviews for Android and Yocto projects.  This series also 
> > drops the Broxton patches; the Broxton firmware has not 
> > been published yet.  Broxton support can be added later 
> > when the Broxton firmware is available. 
> > 
> > Also, the "DO NOT MERGE" patches to enable SLPC and guc 
> > submission by default have been dropped.  These can be 
> > added later after SLPC has been shown to outperform 
> > host-based power management; this may require a newer 
> > version of the GuC firmware.
> > 
> > With SLPC disabled by default, this series should be 
> > safe to merge now. 
> > 
> > VIZ-6773, VIZ-6889
> 
> Thank you to Chris, Daniel and Imre for your comments.  
> I agree that some of the suggested changes should be made.  
> 
> Whether those changes should be made before merging or with 
> later patches will be someone else's problem.  
> 
> I won't be sending another version of this series.

Thank you for the series, but if you are not willing to maintain it or
at the very least bring it to the point where it can be enabled by
default (and by virtue have several people familar with the hw,
implementation and user interactions), why should any one else?
-Chris

-- 
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Re: [PATCH 15/21] drm/i915/slpc: Notification of Refresh Rate change

[Ville Syrjälä]

On Wed, Apr 27, 2016 at 06:10:59PM -0700, tom.orourke@intel.com wrote:
> From: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> 
> This patch will inform GuC SLPC about changes in the refresh rate
> due to Seamless DRRS. Refresh rate changes due to Static DRRS will
> be notified via commit path.
> 
> v2: Rebased on previous changed patch and printed error message if
> H2G action fails.
> v2(torourke): Updates suggested by Paulo: replace HAS_SLPC with
> intel_slpc_active. return void instead of ignored error code.
> 
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp.c   |  2 ++
>  drivers/gpu/drm/i915/intel_slpc.c | 23 +++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_slpc.h |  1 +
>  3 files changed, 26 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index c12c414..3d41f7b 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -5379,6 +5379,8 @@ static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
>  	dev_priv->drrs.refresh_rate_type = index;
>  
>  	DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
> +
> +	intel_slpc_update_display_rr_info(dev, refresh_rate);
>  }
>  
>  /**
> diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
> index 7f26284..9e0bc96 100644
> --- a/drivers/gpu/drm/i915/intel_slpc.c
> +++ b/drivers/gpu/drm/i915/intel_slpc.c
> @@ -364,3 +364,26 @@ void intel_slpc_update_atomic_commit_info(struct drm_device *dev,
>  	if (notify)
>  		host2guc_slpc_display_mode_change(dev);
>  }
> +
> +void intel_slpc_update_display_rr_info(struct drm_device *dev, u32 refresh_rate)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	struct drm_crtc *crtc;
> +	struct intel_display_pipe_info *per_pipe_info;
> +	struct intel_slpc_display_mode_event_params *display_params;
> +
> +	if (!intel_slpc_active(dev))
> +		return;
> +
> +	if (!refresh_rate)
> +		return;
> +
> +	display_params = &dev_priv->guc.slpc.display_mode_params;
> +	crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
> +
> +	per_pipe_info = &display_params->per_pipe_info[to_intel_crtc(crtc)->pipe];
> +	per_pipe_info->refresh_rate = refresh_rate;
> +	per_pipe_info->vsync_ft_usec = 1000000 / refresh_rate;
> +
> +	host2guc_slpc_display_mode_change(dev);
> +}

Other people already commented, but I'll just add that this in any case
looks rather bogus. Only updated for a single pipe when it has drrs
enabled, non-drrs and all the other pipes left out. What's that about?

> diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
> index 39b4657..0b251a1 100644
> --- a/drivers/gpu/drm/i915/intel_slpc.h
> +++ b/drivers/gpu/drm/i915/intel_slpc.h
> @@ -153,5 +153,6 @@ void intel_slpc_reset(struct drm_device *dev);
>  void intel_slpc_update_display_mode_info(struct drm_device *dev);
>  void intel_slpc_update_atomic_commit_info(struct drm_device *dev,
>  					  struct drm_atomic_state *state);
> +void intel_slpc_update_display_rr_info(struct drm_device *dev, u32 refresh_rate);
>  
>  #endif
> -- 
> 1.9.1
> 
> _______________________________________________
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Re: [PATCH 21/21] drm/i915/slpc: Fail intel_runtime_suspend if SLPC or RPS not active

[Imre Deak]

On to, 2016-04-28 at 09:00 +0100, Chris Wilson wrote:
> On Thu, Apr 28, 2016 at 10:57:20AM +0300, Imre Deak wrote:
> > On to, 2016-04-28 at 07:56 +0100, Chris Wilson wrote:
> > > On Wed, Apr 27, 2016 at 06:11:05PM -0700, tom.orourke@intel.com
> > > wrote:
> > > > From: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> > > > 
> > > > intel_runtime_suspend failed with warning if RPS was disabled.
> > > > With SLPC enabled, RPS is disabled. With SLPC, warning is now
> > > > changed
> > > > to consider SLPC active status as well. This will ensure
> > > > runtime suspend
> > > > proceeds when SLPC enabled.
> > > > 
> > > > v2: Commit message update. (Tom)
> > > > 
> > > > Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> > > > Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
> > > > ---
> > > >  drivers/gpu/drm/i915/i915_drv.c | 3 ++-
> > > >  1 file changed, 2 insertions(+), 1 deletion(-)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/i915_drv.c
> > > > b/drivers/gpu/drm/i915/i915_drv.c
> > > > index cc22fa0..00a2713 100644
> > > > --- a/drivers/gpu/drm/i915/i915_drv.c
> > > > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > > > @@ -1474,7 +1474,8 @@ static int intel_runtime_suspend(struct
> > > > device *device)
> > > >  	struct drm_i915_private *dev_priv = dev->dev_private;
> > > >  	int ret;
> > > >  
> > > > -	if (WARN_ON_ONCE(!(dev_priv->rps.enabled &&
> > > > intel_enable_rc6(dev))))
> > > > +	if (WARN_ON_ONCE(!((dev_priv->rps.enabled ||
> > > > intel_slpc_active(dev)) &&
> > > > +			   intel_enable_rc6(dev))))
> > > 
> > > The real question here is why does runtime suspend depend on
> > > either of
> > > these being enabled (espcially rps!).
> > 
> > We need RC6 enabled across a runtime suspend/resume since we depend
> > on
> > the RC6 context to be retained across these transitions. There is
> > no
> > separate knob for RPS and we enable RC6 and RPS together, that's
> > why
> > rps.enabled is checked.
> 
> So, from the standpoint of this series, we should be separating the
> two
> and giving rc6 its own bit of bookkeeping.

Yes, separating RC6 and RPS enabling would be the clean way for this
and other purposes too. This patchset enables RC6
from intel_enable_gt_powersave() directly in case SLPC is enabled but
schedules a work for enabling RC6 if SLPC is not enabled. So while the
above works it could be done in a cleaner way.

--Imre
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