From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47271) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ay3Ck-0003SN-4D for qemu-devel@nongnu.org; Wed, 04 May 2016 16:15:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ay3CY-0004Eb-5B for qemu-devel@nongnu.org; Wed, 04 May 2016 16:15:24 -0400 Received: from smtp1-g21.free.fr ([212.27.42.1]:33638) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ay3CX-00043P-P9 for qemu-devel@nongnu.org; Wed, 04 May 2016 16:15:18 -0400 From: Laurent Vivier Date: Wed, 4 May 2016 22:12:02 +0200 Message-Id: <1462392752-17703-23-git-send-email-laurent@vivier.eu> In-Reply-To: <1462392752-17703-1-git-send-email-laurent@vivier.eu> References: <1462392752-17703-1-git-send-email-laurent@vivier.eu> Subject: [Qemu-devel] [PATCH 22/52] target-m68k: Introduce DisasCompare List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: gerg@uclinux.org, schwab@linux-m68k.org, agraf@suse.de, rth@twiddle.net, Laurent Vivier From: Richard Henderson Signed-off-by: Richard Henderson Signed-off-by: Laurent Vivier --- target-m68k/translate.c | 85 +++++++++++++++++++++++++++++++++++-------------- 1 file changed, 61 insertions(+), 24 deletions(-) diff --git a/target-m68k/translate.c b/target-m68k/translate.c index c3d7318..efd4d9c 100644 --- a/target-m68k/translate.c +++ b/target-m68k/translate.c @@ -756,8 +756,15 @@ static TCGv gen_ea(CPUM68KState *env, DisasContext *s, uint16_t insn, return NULL_QREG; } -/* This generates a conditional branch, clobbering all temporaries. */ -static void gen_jmpcc(DisasContext *s, int cond, TCGLabel *l1) +typedef struct { + TCGCond tcond; + bool g1; + bool g2; + TCGv v1; + TCGv v2; +} DisasCompare; + +static void gen_cc_cond(DisasCompare *c, DisasContext *s, int cond) { TCGv tmp, tmp2; TCGCond tcond; @@ -765,61 +772,92 @@ static void gen_jmpcc(DisasContext *s, int cond, TCGLabel *l1) /* TODO: Optimize compare/branch pairs rather than always flushing flag state to CC_OP_FLAGS. */ gen_flush_flags(s); - update_cc_op(s); + + c->g1 = 1; + c->g2 = 0; + c->v2 = tcg_const_i32(0); + switch (cond) { case 0: /* T */ - tcg_gen_br(l1); - return; case 1: /* F */ - return; + c->v1 = c->v2; + tcond = TCG_COND_NEVER; + break; case 2: /* HI (!C && !Z) -> !(C || Z)*/ case 3: /* LS (C || Z) */ - tmp = tcg_temp_new(); - tcg_gen_setcondi_i32(TCG_COND_EQ, tmp, QREG_CC_Z, 0); + c->v1 = tmp = tcg_temp_new(); + c->g1 = 0; + tcg_gen_setcond_i32(TCG_COND_EQ, tmp, QREG_CC_Z, c->v2); tcg_gen_or_i32(tmp, tmp, QREG_CC_C); - tcond = (cond & 1 ? TCG_COND_NE: TCG_COND_EQ); + tcond = TCG_COND_NE; break; case 4: /* CC (!C) */ case 5: /* CS (C) */ - tmp = QREG_CC_C; - tcond = (cond & 1 ? TCG_COND_NE : TCG_COND_EQ); + c->v1 = QREG_CC_C; + tcond = TCG_COND_NE; break; case 6: /* NE (!Z) */ case 7: /* EQ (Z) */ - tmp = QREG_CC_Z; - tcond = (cond & 1 ? TCG_COND_EQ : TCG_COND_NE); + c->v1 = QREG_CC_Z; + tcond = TCG_COND_EQ; break; case 8: /* VC (!V) */ case 9: /* VS (V) */ - tmp = QREG_CC_V; - tcond = (cond & 1 ? TCG_COND_LT : TCG_COND_GE); + c->v1 = QREG_CC_V; + tcond = TCG_COND_LT; break; case 10: /* PL (!N) */ case 11: /* MI (N) */ - tmp = QREG_CC_N; - tcond = (cond & 1 ? TCG_COND_LT : TCG_COND_GE); + c->v1 = QREG_CC_N; + tcond = TCG_COND_LT; break; case 12: /* GE (!(N ^ V)) */ case 13: /* LT (N ^ V) */ - tmp = tcg_temp_new(); + c->v1 = tmp = tcg_temp_new(); + c->g1 = 0; tcg_gen_xor_i32(tmp, QREG_CC_N, QREG_CC_V); - tcond = (cond & 1 ? TCG_COND_LT : TCG_COND_GE); + tcond = TCG_COND_LT; break; case 14: /* GT (!(Z || (N ^ V))) */ case 15: /* LE (Z || (N ^ V)) */ - tmp = tcg_temp_new(); - tcg_gen_setcondi_i32(TCG_COND_EQ, tmp, QREG_CC_Z, 0); + c->v1 = tmp = tcg_temp_new(); + c->g1 = 0; + tcg_gen_setcond_i32(TCG_COND_EQ, tmp, QREG_CC_Z, c->v2); tcg_gen_neg_i32(tmp, tmp); tmp2 = tcg_temp_new(); tcg_gen_xor_i32(tmp2, QREG_CC_N, QREG_CC_V); tcg_gen_or_i32(tmp, tmp, tmp2); - tcond = (cond & 1 ? TCG_COND_LT : TCG_COND_GE); + tcg_temp_free(tmp2); + tcond = TCG_COND_LT; break; default: /* Should ever happen. */ abort(); } - tcg_gen_brcondi_i32(tcond, tmp, 0, l1); + if ((cond & 1) == 0) { + tcond = tcg_invert_cond(tcond); + } + c->tcond = tcond; +} + +static void free_cond(DisasCompare *c) +{ + if (!c->g1) { + tcg_temp_free(c->v1); + } + if (!c->g2) { + tcg_temp_free(c->v2); + } +} + +static void gen_jmpcc(DisasContext *s, int cond, TCGLabel *l1) +{ + DisasCompare c; + + gen_cc_cond(&c, s, cond); + update_cc_op(s); + tcg_gen_brcond_i32(c.tcond, c.v1, c.v2, l1); + free_cond(&c); } DISAS_INSN(scc) @@ -1674,7 +1712,6 @@ DISAS_INSN(branch) /* bsr */ gen_push(s, tcg_const_i32(s->pc)); } - update_cc_op(s); if (op > 1) { /* Bcc */ l1 = gen_new_label(); -- 2.5.5