From mboxrd@z Thu Jan 1 00:00:00 1970 From: Simon Glass Date: Thu, 5 May 2016 07:28:10 -0600 Subject: [U-Boot] [PATCH v2 06/18] net: macb: Flush correct cache portion when sending In-Reply-To: <1462454902-6093-1-git-send-email-sjg@chromium.org> References: <1462454902-6093-1-git-send-email-sjg@chromium.org> Message-ID: <1462454902-6093-7-git-send-email-sjg@chromium.org> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de The end address of the cache flush must be cache-line-aligned since otherwise (at least on ARM926-EJS) the request is ignored. When the cache is enabled this means that packets are not sent. Signed-off-by: Simon Glass Reviewed-by: Heiko Schocher Acked-by: Joe Hershberger --- Changes in v2: None drivers/net/macb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/macb.c b/drivers/net/macb.c index f0af40c..ecdfc1b 100644 --- a/drivers/net/macb.c +++ b/drivers/net/macb.c @@ -280,7 +280,7 @@ static int _macb_send(struct macb_device *macb, const char *name, void *packet, barrier(); macb_flush_ring_desc(macb, TX); /* Do we need check paddr and length is dcache line aligned? */ - flush_dcache_range(paddr, paddr + length); + flush_dcache_range(paddr, paddr + ALIGN(length, ARCH_DMA_MINALIGN)); macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART)); /* -- 2.8.0.rc3.226.g39d4020