From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48826) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1azkfT-0006NN-3i for qemu-devel@nongnu.org; Mon, 09 May 2016 08:52:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1azkfM-0005Of-2G for qemu-devel@nongnu.org; Mon, 09 May 2016 08:52:08 -0400 Received: from mx1.redhat.com ([209.132.183.28]:36878) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1azkfL-0005Nl-TA for qemu-devel@nongnu.org; Mon, 09 May 2016 08:52:03 -0400 From: Gerd Hoffmann Date: Mon, 9 May 2016 14:51:50 +0200 Message-Id: <1462798310-21395-6-git-send-email-kraxel@redhat.com> In-Reply-To: <1462798310-21395-1-git-send-email-kraxel@redhat.com> References: <1462798310-21395-1-git-send-email-kraxel@redhat.com> Subject: [Qemu-devel] [PULL 5/5] vga: make sure vga register setup for vbe stays intact (CVE-2016-3712). List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , Gerd Hoffmann Call vbe_update_vgaregs() when the guest touches GFX, SEQ or CRT registers, to make sure the vga registers will always have the values needed by vbe mode. This makes sure the sanity checks applied by vbe_fixup_regs() are effective. Without this guests can muck with shift_control, can turn on planar vga modes or text mode emulation while VBE is active, making qemu take code paths meant for CGA compatibility, but with the very large display widths and heigts settable using VBE registers. Which is good for one or another buffer overflow. Not that critical as they typically read overflows happening somewhere in the display code. So guests can DoS by crashing qemu with a segfault, but it is probably not possible to break out of the VM. Fixes: CVE-2016-3712 Reported-by: Zuozhi Fzz Reported-by: P J P Signed-off-by: Gerd Hoffmann --- hw/display/vga.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/hw/display/vga.c b/hw/display/vga.c index eeeb9c8..4a55ec6 100644 --- a/hw/display/vga.c +++ b/hw/display/vga.c @@ -142,6 +142,8 @@ static uint32_t expand4[256]; static uint16_t expand2[256]; static uint8_t expand4to8[16]; +static void vbe_update_vgaregs(VGACommonState *s); + static inline bool vbe_enabled(VGACommonState *s) { return s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED; @@ -484,6 +486,7 @@ void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val) printf("vga: write SR%x = 0x%02x\n", s->sr_index, val); #endif s->sr[s->sr_index] = val & sr_mask[s->sr_index]; + vbe_update_vgaregs(s); if (s->sr_index == VGA_SEQ_CLOCK_MODE) { s->update_retrace_info(s); } @@ -515,6 +518,7 @@ void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val) printf("vga: write GR%x = 0x%02x\n", s->gr_index, val); #endif s->gr[s->gr_index] = val & gr_mask[s->gr_index]; + vbe_update_vgaregs(s); vga_update_memory_access(s); break; case VGA_CRT_IM: @@ -533,10 +537,12 @@ void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val) if (s->cr_index == VGA_CRTC_OVERFLOW) { s->cr[VGA_CRTC_OVERFLOW] = (s->cr[VGA_CRTC_OVERFLOW] & ~0x10) | (val & 0x10); + vbe_update_vgaregs(s); } return; } s->cr[s->cr_index] = val; + vbe_update_vgaregs(s); switch(s->cr_index) { case VGA_CRTC_H_TOTAL: -- 1.8.3.1