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From: Krzysztof Kozlowski <krzk@kernel.org>
To: Kukjin Kim <kgene@kernel.org>,
	Krzysztof Kozlowski <k.kozlowski@samsung.com>,
	Sylwester Nawrocki <s.nawrocki@samsung.com>,
	Tomasz Figa <tomasz.figa@gmail.com>,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@codeaurora.org>,
	linux-arm-kernel@lists.infradead.org,
	linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org
Cc: Javier Martinez Canillas <javier@osg.samsung.com>,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzk@kernel.org>
Subject: [PATCH v3 21/27] ARM: dts: exynos: Add USB to Exynos5410
Date: Tue, 10 May 2016 22:09:24 +0200	[thread overview]
Message-ID: <1462910970-1812-22-git-send-email-krzk@kernel.org> (raw)
In-Reply-To: <1462910970-1812-1-git-send-email-krzk@kernel.org>

Move USB 3.0 DWC and 2.0 EHCI/OHCI nodes from exynos5420.dtsi to
exynos54xx.dtsi common for entire family. For Exynos542x/5800 this
should not have functional impact but for Exynos5410 this effectively
adds USB support.

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>

---

TODO: lack of regulator causes errors:
	usb usb4-port1: over-current condition
?
---
 arch/arm/boot/dts/exynos5410.dtsi |  39 +++++++++++
 arch/arm/boot/dts/exynos5420.dtsi | 133 +++++++++++---------------------------
 arch/arm/boot/dts/exynos54xx.dtsi |  79 ++++++++++++++++++++++
 3 files changed, 157 insertions(+), 94 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi
index 850343d3c2af..dd4d6d752865 100644
--- a/arch/arm/boot/dts/exynos5410.dtsi
+++ b/arch/arm/boot/dts/exynos5410.dtsi
@@ -185,4 +185,43 @@
 		  3 0 0x07000000 0x20000>;
 };
 
+&usbdrd3_0 {
+	clocks = <&clock CLK_USBD300>;
+	clock-names = "usbdrd30";
+};
+
+&usbdrd_phy0 {
+	clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
+	clock-names = "phy", "ref";
+	samsung,pmu-syscon = <&pmu_system_controller>;
+};
+
+&usbdrd3_1 {
+	clocks = <&clock CLK_USBD301>;
+	clock-names = "usbdrd30";
+};
+
+&usbdrd_phy1 {
+	clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
+	clock-names = "phy", "ref";
+	samsung,pmu-syscon = <&pmu_system_controller>;
+};
+
+&usbhost1 {
+	clocks = <&clock CLK_USBH20>;
+	clock-names = "usbhost";
+};
+
+&usbhost2 {
+	clocks = <&clock CLK_USBH20>;
+	clock-names = "usbhost";
+};
+
+&usb2_phy {
+	clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
+	clock-names = "phy", "ref";
+	samsung,sysreg-phandle = <&sysreg_system_controller>;
+	samsung,pmureg-phandle = <&pmu_system_controller>;
+};
+
 #include "exynos5410-pinctrl.dtsi"
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index ebf2ed3c5ff8..8fa65eb8027d 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -41,8 +41,6 @@
 		spi0 = &spi_0;
 		spi1 = &spi_1;
 		spi2 = &spi_2;
-		usbdrdphy0 = &usbdrd_phy0;
-		usbdrdphy1 = &usbdrd_phy1;
 	};
 
 	/*
@@ -770,98 +768,6 @@
 			clock-names = "secss";
 		};
 
-		usbdrd3_0: usb3-0 {
-			compatible = "samsung,exynos5250-dwusb3";
-			clocks = <&clock CLK_USBD300>;
-			clock-names = "usbdrd30";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges;
-
-			usbdrd_dwc3_0: dwc3@12000000 {
-				compatible = "snps,dwc3";
-				reg = <0x12000000 0x10000>;
-				interrupts = <0 72 0>;
-				phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>;
-				phy-names = "usb2-phy", "usb3-phy";
-			};
-		};
-
-		usbdrd_phy0: phy@12100000 {
-			compatible = "samsung,exynos5420-usbdrd-phy";
-			reg = <0x12100000 0x100>;
-			clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
-			clock-names = "phy", "ref";
-			samsung,pmu-syscon = <&pmu_system_controller>;
-			#phy-cells = <1>;
-		};
-
-		usbdrd3_1: usb3-1 {
-			compatible = "samsung,exynos5250-dwusb3";
-			clocks = <&clock CLK_USBD301>;
-			clock-names = "usbdrd30";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges;
-
-			usbdrd_dwc3_1: dwc3@12400000 {
-				compatible = "snps,dwc3";
-				reg = <0x12400000 0x10000>;
-				interrupts = <0 73 0>;
-				phys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>;
-				phy-names = "usb2-phy", "usb3-phy";
-			};
-		};
-
-		usbdrd_phy1: phy@12500000 {
-			compatible = "samsung,exynos5420-usbdrd-phy";
-			reg = <0x12500000 0x100>;
-			clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
-			clock-names = "phy", "ref";
-			samsung,pmu-syscon = <&pmu_system_controller>;
-			#phy-cells = <1>;
-		};
-
-		usbhost2: usb@12110000 {
-			compatible = "samsung,exynos4210-ehci";
-			reg = <0x12110000 0x100>;
-			interrupts = <0 71 0>;
-
-			clocks = <&clock CLK_USBH20>;
-			clock-names = "usbhost";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			port@0 {
-				reg = <0>;
-				phys = <&usb2_phy 1>;
-			};
-		};
-
-		usbhost1: usb@12120000 {
-			compatible = "samsung,exynos4210-ohci";
-			reg = <0x12120000 0x100>;
-			interrupts = <0 71 0>;
-
-			clocks = <&clock CLK_USBH20>;
-			clock-names = "usbhost";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			port@0 {
-				reg = <0>;
-				phys = <&usb2_phy 1>;
-			};
-		};
-
-		usb2_phy: phy@12130000 {
-			compatible = "samsung,exynos5250-usb2-phy";
-			reg = <0x12130000 0x100>;
-			clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
-			clock-names = "phy", "ref";
-			#phy-cells = <1>;
-			samsung,sysreg-phandle = <&sysreg_system_controller>;
-			samsung,pmureg-phandle = <&pmu_system_controller>;
-		};
-
 		sysmmu_g2dr: sysmmu@0x10A60000 {
 			compatible = "samsung,exynos-sysmmu";
 			reg = <0x10A60000 0x1000>;
@@ -1153,4 +1059,43 @@
 	clock-names = "uart", "clk_uart_baud0";
 };
 
+&usbdrd3_0 {
+	clocks = <&clock CLK_USBD300>;
+	clock-names = "usbdrd30";
+};
+
+&usbdrd_phy0 {
+	clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
+	clock-names = "phy", "ref";
+	samsung,pmu-syscon = <&pmu_system_controller>;
+};
+
+&usbdrd3_1 {
+	clocks = <&clock CLK_USBD301>;
+	clock-names = "usbdrd30";
+};
+
+&usbdrd_phy1 {
+	clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
+	clock-names = "phy", "ref";
+	samsung,pmu-syscon = <&pmu_system_controller>;
+};
+
+&usbhost1 {
+	clocks = <&clock CLK_USBH20>;
+	clock-names = "usbhost";
+};
+
+&usbhost2 {
+	clocks = <&clock CLK_USBH20>;
+	clock-names = "usbhost";
+};
+
+&usb2_phy {
+	clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
+	clock-names = "phy", "ref";
+	samsung,sysreg-phandle = <&sysreg_system_controller>;
+	samsung,pmureg-phandle = <&pmu_system_controller>;
+};
+
 #include "exynos5420-pinctrl.dtsi"
diff --git a/arch/arm/boot/dts/exynos54xx.dtsi b/arch/arm/boot/dts/exynos54xx.dtsi
index 9ce625bd79c1..a9a062708237 100644
--- a/arch/arm/boot/dts/exynos54xx.dtsi
+++ b/arch/arm/boot/dts/exynos54xx.dtsi
@@ -20,6 +20,11 @@
 / {
 	compatible = "samsung,exynos5";
 
+	aliases {
+		usbdrdphy0 = &usbdrd_phy0;
+		usbdrdphy1 = &usbdrd_phy1;
+	};
+
 	soc: soc {
 		sysram@02020000 {
 			compatible = "mmio-sram";
@@ -64,5 +69,79 @@
 						<11 &gic 0 131 0>;
 			};
 		};
+
+		usbdrd3_0: usb3-0 {
+			compatible = "samsung,exynos5250-dwusb3";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			usbdrd_dwc3_0: dwc3@12000000 {
+				compatible = "snps,dwc3";
+				reg = <0x12000000 0x10000>;
+				interrupts = <0 72 0>;
+				phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>;
+				phy-names = "usb2-phy", "usb3-phy";
+			};
+		};
+
+		usbdrd_phy0: phy@12100000 {
+			compatible = "samsung,exynos5420-usbdrd-phy";
+			reg = <0x12100000 0x100>;
+			#phy-cells = <1>;
+		};
+
+		usbdrd3_1: usb3-1 {
+			compatible = "samsung,exynos5250-dwusb3";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			usbdrd_dwc3_1: dwc3@12400000 {
+				compatible = "snps,dwc3";
+				reg = <0x12400000 0x10000>;
+				interrupts = <0 73 0>;
+				phys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>;
+				phy-names = "usb2-phy", "usb3-phy";
+			};
+		};
+
+		usbdrd_phy1: phy@12500000 {
+			compatible = "samsung,exynos5420-usbdrd-phy";
+			reg = <0x12500000 0x100>;
+			#phy-cells = <1>;
+		};
+
+		usbhost2: usb@12110000 {
+			compatible = "samsung,exynos4210-ehci";
+			reg = <0x12110000 0x100>;
+			interrupts = <0 71 0>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+			port@0 {
+				reg = <0>;
+				phys = <&usb2_phy 1>;
+			};
+		};
+
+		usbhost1: usb@12120000 {
+			compatible = "samsung,exynos4210-ohci";
+			reg = <0x12120000 0x100>;
+			interrupts = <0 71 0>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+			port@0 {
+				reg = <0>;
+				phys = <&usb2_phy 1>;
+			};
+		};
+
+		usb2_phy: phy@12130000 {
+			compatible = "samsung,exynos5250-usb2-phy";
+			reg = <0x12130000 0x100>;
+			#phy-cells = <1>;
+		};
 	};
 };
-- 
2.5.0

WARNING: multiple messages have this Message-ID
From: krzk@kernel.org (Krzysztof Kozlowski)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 21/27] ARM: dts: exynos: Add USB to Exynos5410
Date: Tue, 10 May 2016 22:09:24 +0200	[thread overview]
Message-ID: <1462910970-1812-22-git-send-email-krzk@kernel.org> (raw)
In-Reply-To: <1462910970-1812-1-git-send-email-krzk@kernel.org>

Move USB 3.0 DWC and 2.0 EHCI/OHCI nodes from exynos5420.dtsi to
exynos54xx.dtsi common for entire family. For Exynos542x/5800 this
should not have functional impact but for Exynos5410 this effectively
adds USB support.

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>

---

TODO: lack of regulator causes errors:
	usb usb4-port1: over-current condition
?
---
 arch/arm/boot/dts/exynos5410.dtsi |  39 +++++++++++
 arch/arm/boot/dts/exynos5420.dtsi | 133 +++++++++++---------------------------
 arch/arm/boot/dts/exynos54xx.dtsi |  79 ++++++++++++++++++++++
 3 files changed, 157 insertions(+), 94 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi
index 850343d3c2af..dd4d6d752865 100644
--- a/arch/arm/boot/dts/exynos5410.dtsi
+++ b/arch/arm/boot/dts/exynos5410.dtsi
@@ -185,4 +185,43 @@
 		  3 0 0x07000000 0x20000>;
 };
 
+&usbdrd3_0 {
+	clocks = <&clock CLK_USBD300>;
+	clock-names = "usbdrd30";
+};
+
+&usbdrd_phy0 {
+	clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
+	clock-names = "phy", "ref";
+	samsung,pmu-syscon = <&pmu_system_controller>;
+};
+
+&usbdrd3_1 {
+	clocks = <&clock CLK_USBD301>;
+	clock-names = "usbdrd30";
+};
+
+&usbdrd_phy1 {
+	clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
+	clock-names = "phy", "ref";
+	samsung,pmu-syscon = <&pmu_system_controller>;
+};
+
+&usbhost1 {
+	clocks = <&clock CLK_USBH20>;
+	clock-names = "usbhost";
+};
+
+&usbhost2 {
+	clocks = <&clock CLK_USBH20>;
+	clock-names = "usbhost";
+};
+
+&usb2_phy {
+	clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
+	clock-names = "phy", "ref";
+	samsung,sysreg-phandle = <&sysreg_system_controller>;
+	samsung,pmureg-phandle = <&pmu_system_controller>;
+};
+
 #include "exynos5410-pinctrl.dtsi"
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index ebf2ed3c5ff8..8fa65eb8027d 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -41,8 +41,6 @@
 		spi0 = &spi_0;
 		spi1 = &spi_1;
 		spi2 = &spi_2;
-		usbdrdphy0 = &usbdrd_phy0;
-		usbdrdphy1 = &usbdrd_phy1;
 	};
 
 	/*
@@ -770,98 +768,6 @@
 			clock-names = "secss";
 		};
 
-		usbdrd3_0: usb3-0 {
-			compatible = "samsung,exynos5250-dwusb3";
-			clocks = <&clock CLK_USBD300>;
-			clock-names = "usbdrd30";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges;
-
-			usbdrd_dwc3_0: dwc3 at 12000000 {
-				compatible = "snps,dwc3";
-				reg = <0x12000000 0x10000>;
-				interrupts = <0 72 0>;
-				phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>;
-				phy-names = "usb2-phy", "usb3-phy";
-			};
-		};
-
-		usbdrd_phy0: phy at 12100000 {
-			compatible = "samsung,exynos5420-usbdrd-phy";
-			reg = <0x12100000 0x100>;
-			clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
-			clock-names = "phy", "ref";
-			samsung,pmu-syscon = <&pmu_system_controller>;
-			#phy-cells = <1>;
-		};
-
-		usbdrd3_1: usb3-1 {
-			compatible = "samsung,exynos5250-dwusb3";
-			clocks = <&clock CLK_USBD301>;
-			clock-names = "usbdrd30";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges;
-
-			usbdrd_dwc3_1: dwc3 at 12400000 {
-				compatible = "snps,dwc3";
-				reg = <0x12400000 0x10000>;
-				interrupts = <0 73 0>;
-				phys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>;
-				phy-names = "usb2-phy", "usb3-phy";
-			};
-		};
-
-		usbdrd_phy1: phy at 12500000 {
-			compatible = "samsung,exynos5420-usbdrd-phy";
-			reg = <0x12500000 0x100>;
-			clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
-			clock-names = "phy", "ref";
-			samsung,pmu-syscon = <&pmu_system_controller>;
-			#phy-cells = <1>;
-		};
-
-		usbhost2: usb at 12110000 {
-			compatible = "samsung,exynos4210-ehci";
-			reg = <0x12110000 0x100>;
-			interrupts = <0 71 0>;
-
-			clocks = <&clock CLK_USBH20>;
-			clock-names = "usbhost";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			port at 0 {
-				reg = <0>;
-				phys = <&usb2_phy 1>;
-			};
-		};
-
-		usbhost1: usb at 12120000 {
-			compatible = "samsung,exynos4210-ohci";
-			reg = <0x12120000 0x100>;
-			interrupts = <0 71 0>;
-
-			clocks = <&clock CLK_USBH20>;
-			clock-names = "usbhost";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			port at 0 {
-				reg = <0>;
-				phys = <&usb2_phy 1>;
-			};
-		};
-
-		usb2_phy: phy at 12130000 {
-			compatible = "samsung,exynos5250-usb2-phy";
-			reg = <0x12130000 0x100>;
-			clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
-			clock-names = "phy", "ref";
-			#phy-cells = <1>;
-			samsung,sysreg-phandle = <&sysreg_system_controller>;
-			samsung,pmureg-phandle = <&pmu_system_controller>;
-		};
-
 		sysmmu_g2dr: sysmmu at 0x10A60000 {
 			compatible = "samsung,exynos-sysmmu";
 			reg = <0x10A60000 0x1000>;
@@ -1153,4 +1059,43 @@
 	clock-names = "uart", "clk_uart_baud0";
 };
 
+&usbdrd3_0 {
+	clocks = <&clock CLK_USBD300>;
+	clock-names = "usbdrd30";
+};
+
+&usbdrd_phy0 {
+	clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
+	clock-names = "phy", "ref";
+	samsung,pmu-syscon = <&pmu_system_controller>;
+};
+
+&usbdrd3_1 {
+	clocks = <&clock CLK_USBD301>;
+	clock-names = "usbdrd30";
+};
+
+&usbdrd_phy1 {
+	clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
+	clock-names = "phy", "ref";
+	samsung,pmu-syscon = <&pmu_system_controller>;
+};
+
+&usbhost1 {
+	clocks = <&clock CLK_USBH20>;
+	clock-names = "usbhost";
+};
+
+&usbhost2 {
+	clocks = <&clock CLK_USBH20>;
+	clock-names = "usbhost";
+};
+
+&usb2_phy {
+	clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
+	clock-names = "phy", "ref";
+	samsung,sysreg-phandle = <&sysreg_system_controller>;
+	samsung,pmureg-phandle = <&pmu_system_controller>;
+};
+
 #include "exynos5420-pinctrl.dtsi"
diff --git a/arch/arm/boot/dts/exynos54xx.dtsi b/arch/arm/boot/dts/exynos54xx.dtsi
index 9ce625bd79c1..a9a062708237 100644
--- a/arch/arm/boot/dts/exynos54xx.dtsi
+++ b/arch/arm/boot/dts/exynos54xx.dtsi
@@ -20,6 +20,11 @@
 / {
 	compatible = "samsung,exynos5";
 
+	aliases {
+		usbdrdphy0 = &usbdrd_phy0;
+		usbdrdphy1 = &usbdrd_phy1;
+	};
+
 	soc: soc {
 		sysram at 02020000 {
 			compatible = "mmio-sram";
@@ -64,5 +69,79 @@
 						<11 &gic 0 131 0>;
 			};
 		};
+
+		usbdrd3_0: usb3-0 {
+			compatible = "samsung,exynos5250-dwusb3";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			usbdrd_dwc3_0: dwc3 at 12000000 {
+				compatible = "snps,dwc3";
+				reg = <0x12000000 0x10000>;
+				interrupts = <0 72 0>;
+				phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>;
+				phy-names = "usb2-phy", "usb3-phy";
+			};
+		};
+
+		usbdrd_phy0: phy at 12100000 {
+			compatible = "samsung,exynos5420-usbdrd-phy";
+			reg = <0x12100000 0x100>;
+			#phy-cells = <1>;
+		};
+
+		usbdrd3_1: usb3-1 {
+			compatible = "samsung,exynos5250-dwusb3";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			usbdrd_dwc3_1: dwc3 at 12400000 {
+				compatible = "snps,dwc3";
+				reg = <0x12400000 0x10000>;
+				interrupts = <0 73 0>;
+				phys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>;
+				phy-names = "usb2-phy", "usb3-phy";
+			};
+		};
+
+		usbdrd_phy1: phy at 12500000 {
+			compatible = "samsung,exynos5420-usbdrd-phy";
+			reg = <0x12500000 0x100>;
+			#phy-cells = <1>;
+		};
+
+		usbhost2: usb at 12110000 {
+			compatible = "samsung,exynos4210-ehci";
+			reg = <0x12110000 0x100>;
+			interrupts = <0 71 0>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+			port at 0 {
+				reg = <0>;
+				phys = <&usb2_phy 1>;
+			};
+		};
+
+		usbhost1: usb at 12120000 {
+			compatible = "samsung,exynos4210-ohci";
+			reg = <0x12120000 0x100>;
+			interrupts = <0 71 0>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+			port at 0 {
+				reg = <0>;
+				phys = <&usb2_phy 1>;
+			};
+		};
+
+		usb2_phy: phy at 12130000 {
+			compatible = "samsung,exynos5250-usb2-phy";
+			reg = <0x12130000 0x100>;
+			#phy-cells = <1>;
+		};
 	};
 };
-- 
2.5.0

  parent reply	other threads:[~2016-05-10 20:11 UTC|newest]

Thread overview: 76+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-05-10 20:09 [PATCH v3 00/27] ARM: dts: exynos: Add initial support for Odroid XU Krzysztof Kozlowski
2016-05-10 20:09 ` Krzysztof Kozlowski
2016-05-10 20:09 ` [PATCH v3 01/27] dt-bindings: clock: Add license and reformat Exynos5410 clock IDs Krzysztof Kozlowski
2016-05-10 20:09   ` Krzysztof Kozlowski
2016-05-10 20:09 ` [PATCH v3 02/27] dt-bindings: clock: Add PWM and USB clock IDs to Exynos5410 Krzysztof Kozlowski
2016-05-10 20:09   ` Krzysztof Kozlowski
2016-05-10 20:09 ` [PATCH v3 03/27] ARM: dts: exynos: Add fin_pll node for clock driver Krzysztof Kozlowski
2016-05-10 20:09   ` Krzysztof Kozlowski
2016-05-10 20:09 ` [PATCH v3 04/27] clk: samsung: exynos5410: Provide fin_pll external fixed clock Krzysztof Kozlowski
2016-05-10 20:09   ` Krzysztof Kozlowski
2016-05-10 20:09 ` [PATCH v3 05/27] ARM: dts: exynos: Switch MCT node to a new fin_pll clock Krzysztof Kozlowski
2016-05-10 20:09   ` Krzysztof Kozlowski
2016-05-10 20:09 ` [PATCH v3 06/27] ARM: dts: exynos: Remove old fixed-clock provider on SMDK5410 Krzysztof Kozlowski
2016-05-10 20:09   ` Krzysztof Kozlowski
2016-05-10 20:09 ` [PATCH v3 07/27] clk: samsung: exynos5410: Rename fin_pll from temporary to regular name Krzysztof Kozlowski
2016-05-10 20:09   ` Krzysztof Kozlowski
2016-05-10 20:09 ` [PATCH v3 08/27] clk: samsung: exynos5410: Add serial3, USB and PWM clocks Krzysztof Kozlowski
2016-05-10 20:09   ` Krzysztof Kozlowski
2016-05-10 20:09 ` [PATCH v3 09/27] ARM: dts: exynos: Re-order alphabetically Exynos5420 SD0/SD1 pinctrl nodes Krzysztof Kozlowski
2016-05-10 20:09   ` Krzysztof Kozlowski
2016-05-10 20:09 ` [PATCH v3 10/27] ARM: dts: exynos: Use lowercase for Exynos5410 CPU node labels Krzysztof Kozlowski
2016-05-10 20:09   ` Krzysztof Kozlowski
2016-05-10 20:09 ` [PATCH v3 11/27] ARM: dts: exynos: Configure Exynos5410 pinctrl for eMMC and SD card Krzysztof Kozlowski
2016-05-10 20:09   ` Krzysztof Kozlowski
2016-05-10 20:09 ` [PATCH v3 12/27] ARM: dts: exynos: Split Odroid XU3 LEDs to separate DTSI Krzysztof Kozlowski
2016-05-10 20:09   ` Krzysztof Kozlowski
2016-05-10 20:09 ` [PATCH v3 13/27] ARM: dts: exynos: Move common nodes to exynos5.dtsi Krzysztof Kozlowski
2016-05-10 20:09   ` Krzysztof Kozlowski
2016-05-10 20:09 ` [PATCH v3 14/27] ARM: dts: exynos: Prepare for inclusion of exynos5.dtsi in exynos5410.dtsi Krzysztof Kozlowski
2016-05-10 20:09   ` Krzysztof Kozlowski
2016-05-10 20:09 ` [PATCH v3 15/27] ARM: dts: exynos: Use phandle to get parent node in exynos5250-snow Krzysztof Kozlowski
2016-05-10 20:09   ` Krzysztof Kozlowski
2016-05-10 20:09 ` [PATCH v3 16/27] ARM: dts: exynos: Move Exynos5250 and Exynos5420 nodes under soc Krzysztof Kozlowski
2016-05-10 20:09 ` [PATCH v3 17/27] ARM: dts: exynos: Include common exynos5 in exynos5410.dtsi Krzysztof Kozlowski
2016-05-10 20:09   ` Krzysztof Kozlowski
2016-05-10 20:09 ` [PATCH v3 18/27] ARM: dts: exynos: Enable UART3 on Exynos5410 Krzysztof Kozlowski
2016-05-10 20:09   ` Krzysztof Kozlowski
2016-05-10 20:09 ` [PATCH v3 19/27] ARM: dts: exynos: MCT is not an interrupt controller and extend length of iomap Krzysztof Kozlowski
2016-05-10 20:09   ` Krzysztof Kozlowski
2016-05-10 20:09 ` [PATCH v3 20/27] ARM: dts: exynos: Move common Exynos5410/542x/5800 nodes to new DTSI Krzysztof Kozlowski
2016-05-10 20:09   ` Krzysztof Kozlowski
2016-05-10 20:09 ` Krzysztof Kozlowski [this message]
2016-05-10 20:09   ` [PATCH v3 21/27] ARM: dts: exynos: Add USB to Exynos5410 Krzysztof Kozlowski
2016-05-10 20:09 ` [PATCH v3 22/27] ARM: dts: exynos: Add initial support for Odroid XU board Krzysztof Kozlowski
2016-05-10 20:09   ` Krzysztof Kozlowski
2016-05-10 20:09 ` [PATCH v3 23/27] dt-bindings: clock: Add I2C, HSI2C and RTC clock IDs to Exynos5410 Krzysztof Kozlowski
2016-05-10 20:09   ` Krzysztof Kozlowski
2016-05-11 12:31   ` Javier Martinez Canillas
2016-05-11 12:31     ` Javier Martinez Canillas
2016-05-10 20:09 ` [PATCH v3 24/27] clk: samsung: exynos5410: Add I2C, HSI2C and RTC clocks Krzysztof Kozlowski
2016-05-10 20:09   ` Krzysztof Kozlowski
2016-05-11 12:32   ` Javier Martinez Canillas
2016-05-11 12:32     ` Javier Martinez Canillas
2016-05-10 20:09 ` [PATCH v3 25/27] ARM: dts: exynos: Move HSI2C nodes to exynos54xx.dtsi Krzysztof Kozlowski
2016-05-10 20:09   ` Krzysztof Kozlowski
2016-05-11 12:33   ` Javier Martinez Canillas
2016-05-11 12:33     ` Javier Martinez Canillas
2016-05-10 20:09 ` [PATCH v3 26/27] ARM: dts: exynos: Add I2C, PWM and UART pinctrl to Exynos5410 Krzysztof Kozlowski
2016-05-10 20:09   ` Krzysztof Kozlowski
2016-05-11 12:36   ` Javier Martinez Canillas
2016-05-11 12:36     ` Javier Martinez Canillas
2016-05-11 12:36     ` Javier Martinez Canillas
2016-05-10 20:09 ` [PATCH v3 27/27] ARM: dts: exynos: Add RTC and I2C " Krzysztof Kozlowski
2016-05-10 20:09   ` Krzysztof Kozlowski
2016-05-11 12:44   ` Javier Martinez Canillas
2016-05-11 12:44     ` Javier Martinez Canillas
2016-05-11 12:54     ` Krzysztof Kozlowski
2016-05-11 12:54       ` Krzysztof Kozlowski
2016-05-11 15:41 ` [PATCH v3 00/27] ARM: dts: exynos: Add initial support for Odroid XU Javier Martinez Canillas
2016-05-11 15:41   ` Javier Martinez Canillas
2016-05-11 18:14   ` Krzysztof Kozlowski
2016-05-11 18:14     ` Krzysztof Kozlowski
2016-05-13 12:03 ` Robin Murphy
2016-05-13 12:03   ` Robin Murphy
2016-05-13 12:11   ` Krzysztof Kozlowski
2016-05-13 12:11     ` Krzysztof Kozlowski

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