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From: Krzysztof Kozlowski <krzk@kernel.org>
To: Kukjin Kim <kgene@kernel.org>,
	Krzysztof Kozlowski <k.kozlowski@samsung.com>,
	Sylwester Nawrocki <s.nawrocki@samsung.com>,
	Tomasz Figa <tomasz.figa@gmail.com>,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@codeaurora.org>,
	linux-arm-kernel@lists.infradead.org,
	linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org
Cc: Javier Martinez Canillas <javier@osg.samsung.com>,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzk@kernel.org>
Subject: [PATCH v3 04/27] clk: samsung: exynos5410: Provide fin_pll external fixed clock
Date: Tue, 10 May 2016 22:09:07 +0200	[thread overview]
Message-ID: <1462910970-1812-5-git-send-email-krzk@kernel.org> (raw)
In-Reply-To: <1462910970-1812-1-git-send-email-krzk@kernel.org>

Just like clock driver for Exynos542x/5800, provide the fixed clock here
so the clock bindings and their consumers would be consistent and
similar.

However a clock named "fin_pll" is already provided by generic
fixed-clock and it is both referenced in the clock driver (by name) and
in DT (by phandle). To make the transition smooth, first introduce the
new external fixed clock here under temporary, different name and switch
internal users to it.

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
---
 drivers/clk/samsung/clk-exynos5410.c | 42 +++++++++++++++++++++++++-----------
 1 file changed, 29 insertions(+), 13 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos5410.c b/drivers/clk/samsung/clk-exynos5410.c
index d5d5dcabc4a9..35f2cb36f7ef 100644
--- a/drivers/clk/samsung/clk-exynos5410.c
+++ b/drivers/clk/samsung/clk-exynos5410.c
@@ -59,23 +59,29 @@ enum exynos5410_plls {
 };
 
 /* list of all parent clocks */
-PNAME(apll_p)		= { "fin_pll", "fout_apll", };
-PNAME(bpll_p)		= { "fin_pll", "fout_bpll", };
-PNAME(cpll_p)		= { "fin_pll", "fout_cpll" };
-PNAME(mpll_p)		= { "fin_pll", "fout_mpll", };
-PNAME(kpll_p)		= { "fin_pll", "fout_kpll", };
+PNAME(apll_p)		= { "fin_pll_new", "fout_apll", };
+PNAME(bpll_p)		= { "fin_pll_new", "fout_bpll", };
+PNAME(cpll_p)		= { "fin_pll_new", "fout_cpll" };
+PNAME(mpll_p)		= { "fin_pll_new", "fout_mpll", };
+PNAME(kpll_p)		= { "fin_pll_new", "fout_kpll", };
 
 PNAME(mout_cpu_p)	= { "mout_apll", "sclk_mpll", };
 PNAME(mout_kfc_p)	= { "mout_kpll", "sclk_mpll", };
 
-PNAME(mpll_user_p)	= { "fin_pll", "sclk_mpll", };
-PNAME(bpll_user_p)	= { "fin_pll", "sclk_bpll", };
+PNAME(mpll_user_p)	= { "fin_pll_new", "sclk_mpll", };
+PNAME(bpll_user_p)	= { "fin_pll_new", "sclk_bpll", };
 PNAME(mpll_bpll_p)	= { "sclk_mpll_muxed", "sclk_bpll_muxed", };
 
-PNAME(group2_p)		= { "fin_pll", "fin_pll", "none", "none",
+PNAME(group2_p)		= { "fin_pll_new", "fin_pll_new", "none", "none",
 			"none", "none", "sclk_mpll_bpll",
 			 "none", "none", "sclk_cpll" };
 
+/* fixed rate clocks generated outside the soc */
+static struct samsung_fixed_rate_clock
+		exynos5x_fixed_rate_ext_clks[] __initdata = {
+	FRATE(CLK_FIN_PLL, "fin_pll_new", NULL, 0, 0),
+};
+
 static struct samsung_mux_clock exynos5410_mux_clks[] __initdata = {
 	MUX(0, "mout_apll", apll_p, SRC_CPU, 0, 1),
 	MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
@@ -168,18 +174,24 @@ static struct samsung_gate_clock exynos5410_gate_clks[] __initdata = {
 };
 
 static struct samsung_pll_clock exynos5410_plls[nr_plls] __initdata = {
-	[apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
+	[apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll_new", APLL_LOCK,
 		APLL_CON0, NULL),
-	[cpll] = PLL(pll_35xx, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK,
+	[cpll] = PLL(pll_35xx, CLK_FOUT_CPLL, "fout_cpll", "fin_pll_new", CPLL_LOCK,
 		CPLL_CON0, NULL),
-	[mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK,
+	[mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll_new", MPLL_LOCK,
 		MPLL_CON0, NULL),
-	[bpll] = PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK,
+	[bpll] = PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll_new", BPLL_LOCK,
 		BPLL_CON0, NULL),
-	[kpll] = PLL(pll_35xx, CLK_FOUT_KPLL, "fout_kpll", "fin_pll", KPLL_LOCK,
+	[kpll] = PLL(pll_35xx, CLK_FOUT_KPLL, "fout_kpll", "fin_pll_new", KPLL_LOCK,
 		KPLL_CON0, NULL),
 };
 
+/* Same as in Exynos5420 */
+static const struct of_device_id ext_clk_match[] __initconst = {
+	{ .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, },
+	{ },
+};
+
 /* register exynos5410 clocks */
 static void __init exynos5410_clk_init(struct device_node *np)
 {
@@ -192,6 +204,10 @@ static void __init exynos5410_clk_init(struct device_node *np)
 
 	ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
 
+	samsung_clk_of_register_fixed_ext(ctx, exynos5x_fixed_rate_ext_clks,
+			ARRAY_SIZE(exynos5x_fixed_rate_ext_clks),
+			ext_clk_match);
+
 	samsung_clk_register_pll(ctx, exynos5410_plls,
 			ARRAY_SIZE(exynos5410_plls), reg_base);
 
-- 
2.5.0

WARNING: multiple messages have this Message-ID
From: krzk@kernel.org (Krzysztof Kozlowski)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 04/27] clk: samsung: exynos5410: Provide fin_pll external fixed clock
Date: Tue, 10 May 2016 22:09:07 +0200	[thread overview]
Message-ID: <1462910970-1812-5-git-send-email-krzk@kernel.org> (raw)
In-Reply-To: <1462910970-1812-1-git-send-email-krzk@kernel.org>

Just like clock driver for Exynos542x/5800, provide the fixed clock here
so the clock bindings and their consumers would be consistent and
similar.

However a clock named "fin_pll" is already provided by generic
fixed-clock and it is both referenced in the clock driver (by name) and
in DT (by phandle). To make the transition smooth, first introduce the
new external fixed clock here under temporary, different name and switch
internal users to it.

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
---
 drivers/clk/samsung/clk-exynos5410.c | 42 +++++++++++++++++++++++++-----------
 1 file changed, 29 insertions(+), 13 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos5410.c b/drivers/clk/samsung/clk-exynos5410.c
index d5d5dcabc4a9..35f2cb36f7ef 100644
--- a/drivers/clk/samsung/clk-exynos5410.c
+++ b/drivers/clk/samsung/clk-exynos5410.c
@@ -59,23 +59,29 @@ enum exynos5410_plls {
 };
 
 /* list of all parent clocks */
-PNAME(apll_p)		= { "fin_pll", "fout_apll", };
-PNAME(bpll_p)		= { "fin_pll", "fout_bpll", };
-PNAME(cpll_p)		= { "fin_pll", "fout_cpll" };
-PNAME(mpll_p)		= { "fin_pll", "fout_mpll", };
-PNAME(kpll_p)		= { "fin_pll", "fout_kpll", };
+PNAME(apll_p)		= { "fin_pll_new", "fout_apll", };
+PNAME(bpll_p)		= { "fin_pll_new", "fout_bpll", };
+PNAME(cpll_p)		= { "fin_pll_new", "fout_cpll" };
+PNAME(mpll_p)		= { "fin_pll_new", "fout_mpll", };
+PNAME(kpll_p)		= { "fin_pll_new", "fout_kpll", };
 
 PNAME(mout_cpu_p)	= { "mout_apll", "sclk_mpll", };
 PNAME(mout_kfc_p)	= { "mout_kpll", "sclk_mpll", };
 
-PNAME(mpll_user_p)	= { "fin_pll", "sclk_mpll", };
-PNAME(bpll_user_p)	= { "fin_pll", "sclk_bpll", };
+PNAME(mpll_user_p)	= { "fin_pll_new", "sclk_mpll", };
+PNAME(bpll_user_p)	= { "fin_pll_new", "sclk_bpll", };
 PNAME(mpll_bpll_p)	= { "sclk_mpll_muxed", "sclk_bpll_muxed", };
 
-PNAME(group2_p)		= { "fin_pll", "fin_pll", "none", "none",
+PNAME(group2_p)		= { "fin_pll_new", "fin_pll_new", "none", "none",
 			"none", "none", "sclk_mpll_bpll",
 			 "none", "none", "sclk_cpll" };
 
+/* fixed rate clocks generated outside the soc */
+static struct samsung_fixed_rate_clock
+		exynos5x_fixed_rate_ext_clks[] __initdata = {
+	FRATE(CLK_FIN_PLL, "fin_pll_new", NULL, 0, 0),
+};
+
 static struct samsung_mux_clock exynos5410_mux_clks[] __initdata = {
 	MUX(0, "mout_apll", apll_p, SRC_CPU, 0, 1),
 	MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
@@ -168,18 +174,24 @@ static struct samsung_gate_clock exynos5410_gate_clks[] __initdata = {
 };
 
 static struct samsung_pll_clock exynos5410_plls[nr_plls] __initdata = {
-	[apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
+	[apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll_new", APLL_LOCK,
 		APLL_CON0, NULL),
-	[cpll] = PLL(pll_35xx, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK,
+	[cpll] = PLL(pll_35xx, CLK_FOUT_CPLL, "fout_cpll", "fin_pll_new", CPLL_LOCK,
 		CPLL_CON0, NULL),
-	[mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK,
+	[mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll_new", MPLL_LOCK,
 		MPLL_CON0, NULL),
-	[bpll] = PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK,
+	[bpll] = PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll_new", BPLL_LOCK,
 		BPLL_CON0, NULL),
-	[kpll] = PLL(pll_35xx, CLK_FOUT_KPLL, "fout_kpll", "fin_pll", KPLL_LOCK,
+	[kpll] = PLL(pll_35xx, CLK_FOUT_KPLL, "fout_kpll", "fin_pll_new", KPLL_LOCK,
 		KPLL_CON0, NULL),
 };
 
+/* Same as in Exynos5420 */
+static const struct of_device_id ext_clk_match[] __initconst = {
+	{ .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, },
+	{ },
+};
+
 /* register exynos5410 clocks */
 static void __init exynos5410_clk_init(struct device_node *np)
 {
@@ -192,6 +204,10 @@ static void __init exynos5410_clk_init(struct device_node *np)
 
 	ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
 
+	samsung_clk_of_register_fixed_ext(ctx, exynos5x_fixed_rate_ext_clks,
+			ARRAY_SIZE(exynos5x_fixed_rate_ext_clks),
+			ext_clk_match);
+
 	samsung_clk_register_pll(ctx, exynos5410_plls,
 			ARRAY_SIZE(exynos5410_plls), reg_base);
 
-- 
2.5.0

  parent reply	other threads:[~2016-05-10 20:10 UTC|newest]

Thread overview: 76+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-05-10 20:09 [PATCH v3 00/27] ARM: dts: exynos: Add initial support for Odroid XU Krzysztof Kozlowski
2016-05-10 20:09 ` Krzysztof Kozlowski
2016-05-10 20:09 ` [PATCH v3 01/27] dt-bindings: clock: Add license and reformat Exynos5410 clock IDs Krzysztof Kozlowski
2016-05-10 20:09   ` Krzysztof Kozlowski
2016-05-10 20:09 ` [PATCH v3 02/27] dt-bindings: clock: Add PWM and USB clock IDs to Exynos5410 Krzysztof Kozlowski
2016-05-10 20:09   ` Krzysztof Kozlowski
2016-05-10 20:09 ` [PATCH v3 03/27] ARM: dts: exynos: Add fin_pll node for clock driver Krzysztof Kozlowski
2016-05-10 20:09   ` Krzysztof Kozlowski
2016-05-10 20:09 ` Krzysztof Kozlowski [this message]
2016-05-10 20:09   ` [PATCH v3 04/27] clk: samsung: exynos5410: Provide fin_pll external fixed clock Krzysztof Kozlowski
2016-05-10 20:09 ` [PATCH v3 05/27] ARM: dts: exynos: Switch MCT node to a new fin_pll clock Krzysztof Kozlowski
2016-05-10 20:09   ` Krzysztof Kozlowski
2016-05-10 20:09 ` [PATCH v3 06/27] ARM: dts: exynos: Remove old fixed-clock provider on SMDK5410 Krzysztof Kozlowski
2016-05-10 20:09   ` Krzysztof Kozlowski
2016-05-10 20:09 ` [PATCH v3 07/27] clk: samsung: exynos5410: Rename fin_pll from temporary to regular name Krzysztof Kozlowski
2016-05-10 20:09   ` Krzysztof Kozlowski
2016-05-10 20:09 ` [PATCH v3 08/27] clk: samsung: exynos5410: Add serial3, USB and PWM clocks Krzysztof Kozlowski
2016-05-10 20:09   ` Krzysztof Kozlowski
2016-05-10 20:09 ` [PATCH v3 09/27] ARM: dts: exynos: Re-order alphabetically Exynos5420 SD0/SD1 pinctrl nodes Krzysztof Kozlowski
2016-05-10 20:09   ` Krzysztof Kozlowski
2016-05-10 20:09 ` [PATCH v3 10/27] ARM: dts: exynos: Use lowercase for Exynos5410 CPU node labels Krzysztof Kozlowski
2016-05-10 20:09   ` Krzysztof Kozlowski
2016-05-10 20:09 ` [PATCH v3 11/27] ARM: dts: exynos: Configure Exynos5410 pinctrl for eMMC and SD card Krzysztof Kozlowski
2016-05-10 20:09   ` Krzysztof Kozlowski
2016-05-10 20:09 ` [PATCH v3 12/27] ARM: dts: exynos: Split Odroid XU3 LEDs to separate DTSI Krzysztof Kozlowski
2016-05-10 20:09   ` Krzysztof Kozlowski
2016-05-10 20:09 ` [PATCH v3 13/27] ARM: dts: exynos: Move common nodes to exynos5.dtsi Krzysztof Kozlowski
2016-05-10 20:09   ` Krzysztof Kozlowski
2016-05-10 20:09 ` [PATCH v3 14/27] ARM: dts: exynos: Prepare for inclusion of exynos5.dtsi in exynos5410.dtsi Krzysztof Kozlowski
2016-05-10 20:09   ` Krzysztof Kozlowski
2016-05-10 20:09 ` [PATCH v3 15/27] ARM: dts: exynos: Use phandle to get parent node in exynos5250-snow Krzysztof Kozlowski
2016-05-10 20:09   ` Krzysztof Kozlowski
2016-05-10 20:09 ` [PATCH v3 16/27] ARM: dts: exynos: Move Exynos5250 and Exynos5420 nodes under soc Krzysztof Kozlowski
2016-05-10 20:09 ` [PATCH v3 17/27] ARM: dts: exynos: Include common exynos5 in exynos5410.dtsi Krzysztof Kozlowski
2016-05-10 20:09   ` Krzysztof Kozlowski
2016-05-10 20:09 ` [PATCH v3 18/27] ARM: dts: exynos: Enable UART3 on Exynos5410 Krzysztof Kozlowski
2016-05-10 20:09   ` Krzysztof Kozlowski
2016-05-10 20:09 ` [PATCH v3 19/27] ARM: dts: exynos: MCT is not an interrupt controller and extend length of iomap Krzysztof Kozlowski
2016-05-10 20:09   ` Krzysztof Kozlowski
2016-05-10 20:09 ` [PATCH v3 20/27] ARM: dts: exynos: Move common Exynos5410/542x/5800 nodes to new DTSI Krzysztof Kozlowski
2016-05-10 20:09   ` Krzysztof Kozlowski
2016-05-10 20:09 ` [PATCH v3 21/27] ARM: dts: exynos: Add USB to Exynos5410 Krzysztof Kozlowski
2016-05-10 20:09   ` Krzysztof Kozlowski
2016-05-10 20:09 ` [PATCH v3 22/27] ARM: dts: exynos: Add initial support for Odroid XU board Krzysztof Kozlowski
2016-05-10 20:09   ` Krzysztof Kozlowski
2016-05-10 20:09 ` [PATCH v3 23/27] dt-bindings: clock: Add I2C, HSI2C and RTC clock IDs to Exynos5410 Krzysztof Kozlowski
2016-05-10 20:09   ` Krzysztof Kozlowski
2016-05-11 12:31   ` Javier Martinez Canillas
2016-05-11 12:31     ` Javier Martinez Canillas
2016-05-10 20:09 ` [PATCH v3 24/27] clk: samsung: exynos5410: Add I2C, HSI2C and RTC clocks Krzysztof Kozlowski
2016-05-10 20:09   ` Krzysztof Kozlowski
2016-05-11 12:32   ` Javier Martinez Canillas
2016-05-11 12:32     ` Javier Martinez Canillas
2016-05-10 20:09 ` [PATCH v3 25/27] ARM: dts: exynos: Move HSI2C nodes to exynos54xx.dtsi Krzysztof Kozlowski
2016-05-10 20:09   ` Krzysztof Kozlowski
2016-05-11 12:33   ` Javier Martinez Canillas
2016-05-11 12:33     ` Javier Martinez Canillas
2016-05-10 20:09 ` [PATCH v3 26/27] ARM: dts: exynos: Add I2C, PWM and UART pinctrl to Exynos5410 Krzysztof Kozlowski
2016-05-10 20:09   ` Krzysztof Kozlowski
2016-05-11 12:36   ` Javier Martinez Canillas
2016-05-11 12:36     ` Javier Martinez Canillas
2016-05-11 12:36     ` Javier Martinez Canillas
2016-05-10 20:09 ` [PATCH v3 27/27] ARM: dts: exynos: Add RTC and I2C " Krzysztof Kozlowski
2016-05-10 20:09   ` Krzysztof Kozlowski
2016-05-11 12:44   ` Javier Martinez Canillas
2016-05-11 12:44     ` Javier Martinez Canillas
2016-05-11 12:54     ` Krzysztof Kozlowski
2016-05-11 12:54       ` Krzysztof Kozlowski
2016-05-11 15:41 ` [PATCH v3 00/27] ARM: dts: exynos: Add initial support for Odroid XU Javier Martinez Canillas
2016-05-11 15:41   ` Javier Martinez Canillas
2016-05-11 18:14   ` Krzysztof Kozlowski
2016-05-11 18:14     ` Krzysztof Kozlowski
2016-05-13 12:03 ` Robin Murphy
2016-05-13 12:03   ` Robin Murphy
2016-05-13 12:11   ` Krzysztof Kozlowski
2016-05-13 12:11     ` Krzysztof Kozlowski

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