From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751916AbcELCFl (ORCPT ); Wed, 11 May 2016 22:05:41 -0400 Received: from ozlabs.org ([103.22.144.67]:35643 "EHLO ozlabs.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751450AbcELCFj convert rfc822-to-8bit (ORCPT ); Wed, 11 May 2016 22:05:39 -0400 Message-ID: <1463018737.28449.38.camel@neuling.org> Subject: Re: [RFC][PATCH 4/7] sched: Replace sd_busy/nr_busy_cpus with sched_domain_shared From: Michael Neuling To: Peter Zijlstra , Matt Fleming Cc: mingo@kernel.org, linux-kernel@vger.kernel.org, clm@fb.com, mgalbraith@suse.de, tglx@linutronix.de, fweisbec@gmail.com, srikar@linux.vnet.ibm.com, anton@samba.org, oliver , "Shreyas B. Prabhu" Date: Thu, 12 May 2016 12:05:37 +1000 In-Reply-To: <20160511182402.GD3205@twins.programming.kicks-ass.net> References: <20160509104807.284575300@infradead.org> <20160509105210.642395937@infradead.org> <20160511115555.GT2839@codeblueprint.co.uk> <20160511123345.GD3192@twins.programming.kicks-ass.net> <20160511182402.GD3205@twins.programming.kicks-ass.net> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8BIT X-Mailer: Evolution 3.18.5.2-0ubuntu1 Mime-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 2016-05-11 at 20:24 +0200, Peter Zijlstra wrote: > On Wed, May 11, 2016 at 02:33:45PM +0200, Peter Zijlstra wrote: > > > > Hmm, PPC folks; what does your topology look like? > > > > Currently your sched_domain_topology, as per arch/powerpc/kernel/smp.c > > seems to suggest your cores do not share cache at all. > > > > https://en.wikipedia.org/wiki/POWER7 seems to agree and states > > > >   "4 MB L3 cache per C1 core" > > > > And http://www-03.ibm.com/systems/resources/systems_power_software_i_pe > > rfmgmt_underthehood.pdf > > also explicitly draws pictures with the L3 per core. > > > > _however_, that same document describes L3 inter-core fill and lateral > > cast-out, which sounds like the L3s work together to form a node wide > > caching system. > > > > Do we want to model this co-operative L3 slices thing as a sort of > > node-wide LLC for the purpose of the scheduler ? > Going back a generation; Power6 seems to have a shared L3 (off package) > between the two cores on the package. The current topology does not > reflect that at all. > > And going forward a generation; Power8 seems to share the per-core > (chiplet) L3 amonst all cores (chiplets) + is has the centaur (memory > controller) 16M L4. Yep, L1/L2/L3 is per core on POWER8 and POWER7.  POWER6 and POWER5 (both dual core chips) had a shared off chip cache The POWER8 L4 is really a bit different as it's out in the memory controller.  It's more of a memory DIMM buffer as it can only cache data associated with the physical addresses on those DIMMS. > So it seems the current topology setup is not describing these chips > very well. Also note that the arch topology code can runtime select a > topology, so you could make that topo setup micro-arch specific. We are planning on making some topology changes for the upcoming P9 which will share L2/L3 amongst pairs of cores (24 cores per chip). FWIW our P9 upstreaming is still in it's infancy since P9 is not released yet. Mike