From mboxrd@z Thu Jan 1 00:00:00 1970 From: Maxime Ripard Subject: [PATCH 06/20] drm/sun4i: allow dclk to modify its parent rate Date: Mon, 16 May 2016 14:47:06 +0200 Message-ID: <1463402840-17062-7-git-send-email-maxime.ripard@free-electrons.com> References: <1463402840-17062-1-git-send-email-maxime.ripard@free-electrons.com> Return-path: In-Reply-To: <1463402840-17062-1-git-send-email-maxime.ripard@free-electrons.com> Sender: linux-clk-owner@vger.kernel.org To: Rob Herring , Chen-Yu Tsai , Mike Turquette , Stephen Boyd , Daniel Vetter , David Airlie Cc: Boris Brezillon , Laurent Pinchart , dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, Maxime Ripard List-Id: devicetree@vger.kernel.org The pixel clock being only a divider of its parent clock, depending on the resolution, it's expected to change its parent rate. Add that flag so that the clock framework knows it. Fixes: 9026e0d122ac ("drm: Add Allwinner A10 Display Engine support") Signed-off-by: Maxime Ripard --- drivers/gpu/drm/sun4i/sun4i_dotclock.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/sun4i/sun4i_dotclock.c b/drivers/gpu/drm/sun4i/sun4i_dotclock.c index 1ddf6d7a7107..5b3463197c48 100644 --- a/drivers/gpu/drm/sun4i/sun4i_dotclock.c +++ b/drivers/gpu/drm/sun4i/sun4i_dotclock.c @@ -170,6 +170,7 @@ int sun4i_dclk_create(struct device *dev, struct sun4i_tcon *tcon) init.ops = &sun4i_dclk_ops; init.parent_names = &parent_name; init.num_parents = 1; + init.flags = CLK_SET_RATE_PARENT; dclk->regmap = tcon->regs; dclk->hw.init = &init; -- 2.8.2 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: From: Maxime Ripard To: Rob Herring , Chen-Yu Tsai , Mike Turquette , Stephen Boyd , Daniel Vetter , David Airlie Subject: [PATCH 06/20] drm/sun4i: allow dclk to modify its parent rate Date: Mon, 16 May 2016 14:47:06 +0200 Message-Id: <1463402840-17062-7-git-send-email-maxime.ripard@free-electrons.com> In-Reply-To: <1463402840-17062-1-git-send-email-maxime.ripard@free-electrons.com> References: <1463402840-17062-1-git-send-email-maxime.ripard@free-electrons.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Boris Brezillon , devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, Laurent Pinchart , Maxime Ripard , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+mturquette=baylibre.com@lists.infradead.org List-ID: The pixel clock being only a divider of its parent clock, depending on the resolution, it's expected to change its parent rate. Add that flag so that the clock framework knows it. Fixes: 9026e0d122ac ("drm: Add Allwinner A10 Display Engine support") Signed-off-by: Maxime Ripard --- drivers/gpu/drm/sun4i/sun4i_dotclock.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/sun4i/sun4i_dotclock.c b/drivers/gpu/drm/sun4i/sun4i_dotclock.c index 1ddf6d7a7107..5b3463197c48 100644 --- a/drivers/gpu/drm/sun4i/sun4i_dotclock.c +++ b/drivers/gpu/drm/sun4i/sun4i_dotclock.c @@ -170,6 +170,7 @@ int sun4i_dclk_create(struct device *dev, struct sun4i_tcon *tcon) init.ops = &sun4i_dclk_ops; init.parent_names = &parent_name; init.num_parents = 1; + init.flags = CLK_SET_RATE_PARENT; dclk->regmap = tcon->regs; dclk->hw.init = &init; -- 2.8.2 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 From: maxime.ripard@free-electrons.com (Maxime Ripard) Date: Mon, 16 May 2016 14:47:06 +0200 Subject: [PATCH 06/20] drm/sun4i: allow dclk to modify its parent rate In-Reply-To: <1463402840-17062-1-git-send-email-maxime.ripard@free-electrons.com> References: <1463402840-17062-1-git-send-email-maxime.ripard@free-electrons.com> Message-ID: <1463402840-17062-7-git-send-email-maxime.ripard@free-electrons.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org The pixel clock being only a divider of its parent clock, depending on the resolution, it's expected to change its parent rate. Add that flag so that the clock framework knows it. Fixes: 9026e0d122ac ("drm: Add Allwinner A10 Display Engine support") Signed-off-by: Maxime Ripard --- drivers/gpu/drm/sun4i/sun4i_dotclock.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/sun4i/sun4i_dotclock.c b/drivers/gpu/drm/sun4i/sun4i_dotclock.c index 1ddf6d7a7107..5b3463197c48 100644 --- a/drivers/gpu/drm/sun4i/sun4i_dotclock.c +++ b/drivers/gpu/drm/sun4i/sun4i_dotclock.c @@ -170,6 +170,7 @@ int sun4i_dclk_create(struct device *dev, struct sun4i_tcon *tcon) init.ops = &sun4i_dclk_ops; init.parent_names = &parent_name; init.num_parents = 1; + init.flags = CLK_SET_RATE_PARENT; dclk->regmap = tcon->regs; dclk->hw.init = &init; -- 2.8.2