From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752743AbcE2HEx (ORCPT ); Sun, 29 May 2016 03:04:53 -0400 Received: from mirror2.csie.ntu.edu.tw ([140.112.30.76]:59854 "EHLO wens.csie.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752439AbcE2HEs (ORCPT ); Sun, 29 May 2016 03:04:48 -0400 From: Chen-Yu Tsai To: Ulf Hansson , Maxime Ripard Cc: Chen-Yu Tsai , Hans de Goede , linux-mmc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 0/3] mmc: sunxi: Fix MMC DDR modes for Allwinner A80 Date: Sun, 29 May 2016 15:04:41 +0800 Message-Id: <1464505484-3661-1-git-send-email-wens@csie.org> X-Mailer: git-send-email 2.8.1 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi everyone, This series fixes and re-enables eMMC HS-DDR support for Allwinner A80 SoC. The issue with the original code was the mmc clock timings were incorrect, and thus we had disabled HS-DDR on A80 for the previous release. Patch 1 is a fix for mmc core. Arnd's patch to remove IS_ERR_VALUE replaced it with an incorrect check on return values, thus blocking the code path for HS-DDR and higher timing modes. This patch instead checks for a positive return code, which is how mmc_select_bus_width indicates a success. Patch 2 fixes the HS-DDR clock timings for the A80. Patch 3 re-enables HS-DDR mode for the A80. Regards ChenYu Chen-Yu Tsai (3): mmc: fix mmc mode selection for HS-DDR and higher mmc: sunxi: Fix DDR MMC timings for A80 mmc: sunxi: Re-enable eMMC HS-DDR modes on Allwinner A80 drivers/mmc/core/mmc.c | 4 ++-- drivers/mmc/host/sunxi-mmc.c | 9 ++------- 2 files changed, 4 insertions(+), 9 deletions(-) -- 2.8.1 From mboxrd@z Thu Jan 1 00:00:00 1970 From: wens@csie.org (Chen-Yu Tsai) Date: Sun, 29 May 2016 15:04:41 +0800 Subject: [PATCH 0/3] mmc: sunxi: Fix MMC DDR modes for Allwinner A80 Message-ID: <1464505484-3661-1-git-send-email-wens@csie.org> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi everyone, This series fixes and re-enables eMMC HS-DDR support for Allwinner A80 SoC. The issue with the original code was the mmc clock timings were incorrect, and thus we had disabled HS-DDR on A80 for the previous release. Patch 1 is a fix for mmc core. Arnd's patch to remove IS_ERR_VALUE replaced it with an incorrect check on return values, thus blocking the code path for HS-DDR and higher timing modes. This patch instead checks for a positive return code, which is how mmc_select_bus_width indicates a success. Patch 2 fixes the HS-DDR clock timings for the A80. Patch 3 re-enables HS-DDR mode for the A80. Regards ChenYu Chen-Yu Tsai (3): mmc: fix mmc mode selection for HS-DDR and higher mmc: sunxi: Fix DDR MMC timings for A80 mmc: sunxi: Re-enable eMMC HS-DDR modes on Allwinner A80 drivers/mmc/core/mmc.c | 4 ++-- drivers/mmc/host/sunxi-mmc.c | 9 ++------- 2 files changed, 4 insertions(+), 9 deletions(-) -- 2.8.1