From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
To: qemu-ppc@nongnu.org
Cc: qemu-devel@nongnu.org, David Gibson <david@gibson.dropbear.id.au>,
Cedric Le Goater <clg@kaod.org>,
Benjamin Herrenschmidt <benh@kernel.crashing.org>
Subject: [Qemu-devel] [PATCH 6/9] ppc: Fix mtmsr decoding
Date: Tue, 7 Jun 2016 12:50:25 +1000 [thread overview]
Message-ID: <1465267828-10326-6-git-send-email-benh@kernel.crashing.org> (raw)
In-Reply-To: <1465267828-10326-1-git-send-email-benh@kernel.crashing.org>
We had code to handle the L bit in the opcode but we didn't
allow it in the decode mask.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
target-ppc/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index b34289f..3255184 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -9944,7 +9944,7 @@ GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
#if defined(TARGET_PPC64)
GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
#endif
-GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC),
+GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC),
GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC),
GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
--
2.5.5
next prev parent reply other threads:[~2016-06-07 2:56 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-06-07 2:50 [Qemu-devel] [PATCH 1/9] ppc: Properly tag the translation cache based on MMU mode Benjamin Herrenschmidt
2016-06-07 2:50 ` [Qemu-devel] [PATCH 2/9] ppc: Fix tlb invalidations on 6xx/7xx/7xxx 32-bit processors Benjamin Herrenschmidt
2016-06-07 2:50 ` [Qemu-devel] [PATCH 3/9] ppc: Batch TLB flushes on 32-bit 6xx/7xx/7xxx in hash mode Benjamin Herrenschmidt
2016-06-07 2:50 ` [Qemu-devel] [PATCH 4/9] ppc: POWER7 had ACOP and PID registers Benjamin Herrenschmidt
2016-06-07 2:50 ` [Qemu-devel] [PATCH 5/9] ppc: POWER7 has lq/stq instructions and stq need to check ISA Benjamin Herrenschmidt
2016-06-07 2:50 ` Benjamin Herrenschmidt [this message]
2016-06-07 2:50 ` [Qemu-devel] [PATCH 7/9] ppc: Fix slbia decode Benjamin Herrenschmidt
2016-06-07 2:50 ` [Qemu-devel] [PATCH 8/9] ppc: Add missing slbfee. instruction on ppc64 BookS processors Benjamin Herrenschmidt
2016-07-05 17:23 ` [Qemu-devel] [Qemu-ppc] " Cédric Le Goater
2016-07-05 22:10 ` Benjamin Herrenschmidt
2016-07-06 6:57 ` Cédric Le Goater
2016-07-06 7:24 ` Benjamin Herrenschmidt
2016-07-06 7:53 ` Cédric Le Goater
2016-07-06 8:14 ` Benjamin Herrenschmidt
2016-06-07 2:50 ` [Qemu-devel] [PATCH 9/9] ppc: Do not take exceptions on unknown SPRs in privileged mode Benjamin Herrenschmidt
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