From mboxrd@z Thu Jan 1 00:00:00 1970 From: Nadav Amit Subject: [PATCH v2] iommu/vt-d: Avoid write-tearing on PTE clear Date: Fri, 10 Jun 2016 15:12:32 -0700 Message-ID: <1465596752-73460-1-git-send-email-namit@vmware.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org Errors-To: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org To: dwmw2-wEGCiKHe2LqWVfeAwA7xHQ@public.gmane.org Cc: Nadav Amit , iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org List-Id: iommu@lists.linux-foundation.org When a PTE is cleared, the write may be teared or perform by multiple writes. In addition, in 32-bit kernel, writes are currently performed using a single 64-bit write, which does not guarantee order. The byte-code right now does not seem to cause a problem, but it may still occur in theory. Avoid this scenario by using WRITE_ONCE, and order the writes on 32-bit kernels. Signed-off-by: Nadav Amit --- V2: Use two WRITE_ONCE on 32-bit to avoid reordering --- drivers/iommu/intel-iommu.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/intel-iommu.c b/drivers/iommu/intel-iommu.c index e1852e8..6ffd3d3 100644 --- a/drivers/iommu/intel-iommu.c +++ b/drivers/iommu/intel-iommu.c @@ -326,9 +326,26 @@ struct dma_pte { u64 val; }; +#ifndef CONFIG_64BIT +union split_dma_pte { + struct { + u32 val_low; + u32 val_high; + }; + u64 val; +}; +#endif + static inline void dma_clear_pte(struct dma_pte *pte) { - pte->val = 0; +#ifdef CONFIG_64BIT + WRITE_ONCE(pte->val, 0); +#else + union split_dma_pte *sdma_pte = (union split_dma_pte *)pte; + + WRITE_ONCE(sdma_pte->val_low, 0); + WRITE_ONCE(sdma_pte->val_high, 0); +#endif } static inline u64 dma_pte_addr(struct dma_pte *pte) -- 2.7.4